[llvm] [RISCV] Add combine for shadd family of instructions. (PR #130829)

[Min-Yih Hsu via llvm-commits]

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@@ -14325,10 +14325,11 @@ static bool checkAddiForShift(SDValue AddI, int64_t &AddConst,
 
   APInt AddVal;
   SDValue SHLVal;
-  sd_match(AddI, m_Add(m_Value(SHLVal), m_ConstInt(AddVal)));
+  assert(sd_match(AddI, m_Add(m_Value(SHLVal), m_ConstInt(AddVal))) &&
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mshockwave wrote:

This entire sd_match statement will not be executed if LLVM is not built with assertion enabled (e.g. normal Release build). I would recommend something like this:
```
bool IsAddI = sd_match(AddI, ...);
assert(IsAddI && "...");
(void)IsAddI;
```

https://github.com/llvm/llvm-project/pull/130829