[llvm] [RISCV] Lower BUILD_VECTOR with i64 type to VID on RV32 if possible (PR #132339)

[Philip Reames via llvm-commits]

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@@ -1281,6 +1281,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
         if (!Subtarget.is64Bit() && VT.getVectorElementType() == MVT::i64) {
           setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
           setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom);
+
+          // Lower BUILD_VECTOR with i64 type to VID on RV32 if possible.
+          setOperationAction(ISD::BUILD_VECTOR, MVT::i64, Custom);
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preames wrote:

Shouldn't this be VT, not MVT::i64?  (i.e. the vector type, not the scalar element type)

https://github.com/llvm/llvm-project/pull/132339