[llvm] [NVPTX] Improve 64bit FSH/ROT lowering when shift amount is constant (PR #131371)

[Justin Fargnoli via llvm-commits]

https://github.com/justinfargnoli commented:

Can you add an additional section to your PR description where you describe why we need new `NVPTXISD` nodes to handle this case and under what conditions we can begin using `ISD` nodes and perhaps even port this to `LegalizeDAG`? 

Also, which test case is the regression? 

https://github.com/llvm/llvm-project/pull/131371