[llvm] [X86] Prevent APX NDD compression when it creates a partial write (PR #132051)

[Phoebe Wang via llvm-commits]

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@@ -0,0 +1,96 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -mtriple=x86_64-unknown -mattr=+ndd,+egpr -run-pass=break-false-deps -o - | FileCheck --check-prefixes=MIR,RCDEFAULT %s
+# RUN: llc %s -mtriple=x86_64-unknown -mattr=+ndd,+egpr -run-pass=break-false-deps -partial-reg-update-clearance=1 -o - | FileCheck --check-prefixes=MIR,RC1 %s
+#
+# Check that BreakFalseDeps detects cases where an ND instruction would cause a partial register write
+# if compressed to a legacy op. MIR has been modified to force different register assignments.
+#
+# For partial_write, the ADD16rr_ND is compressible, but will become a partial write after compression.
+# Compression is inhibited if the eax definition is within the partial-reg-update-clearance threshold.
+#
+# For no_partial_write, the ADD16rr_ND is incompressible hence it cannot become a partial write.
+# This case checks that an implicit-def of eax is not added by breakPartialRegDependency.
+#
+--- |
+  define signext i16 @partial_write(ptr %p, i32 %a, i32 %b, i16 signext %x, i16 signext %y) #0 {
+  entry:
+    %add = add nsw i32 %b, %a
+    store i32 %add, ptr %p, align 4, !tbaa !1
+    %add1 = trunc i32 %add to i16
+    %add2 = add i16 %add1, %x
+    ret i16 %add2
+  }
+
+  define signext i16 @no_partial_write(ptr %p, i32 %a, i32 %b, i16 signext %x, i16 signext %y) #0 {
+  entry:
+    %add = add nsw i32 %b, %a
+    store i32 %add, ptr %p, align 4, !tbaa !1
+    %add1 = trunc i32 %add to i16
+    %add2 = add i16 %add1, %x
+    ret i16 %add2
+  }
+  attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: write) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx16,+cx8,+egpr,+fxsr,+mmx,+ndd,+sse,+sse2,+x87" "tune-cpu"="generic" }
+
+  !llvm.module.flags = !{!0}
+
+  !0 = !{i32 1, !"wchar_size", i32 4}
+  !1 = !{!2, !2, i64 0}
+  !2 = !{!"int", !3, i64 0}
+  !3 = !{!"omnipotent char", !4, i64 0}
+  !4 = !{!"Simple C/C++ TBAA"}
+...
+---
+name:            partial_write
+tracksRegLiveness: true
+noVRegs:         true
+noPhis:          true
+isSSA:           false
+body:             |
+  bb.0.entry:
+    liveins: $ecx, $edx, $esi, $rdi
+    ; RCDEFAULT-LABEL: name: partial_write
+    ; RCDEFAULT: liveins: $ecx, $edx, $esi, $rdi
+    ; RCDEFAULT-NEXT: {{  $}}
+    ; RCDEFAULT-NEXT: renamable $eax = nsw ADD32rr_ND killed renamable $edx, killed renamable $esi, implicit-def dead $eflags
+    ; RCDEFAULT-NEXT: MOV32mr killed renamable $rdi, 1, $noreg, 0, $noreg, renamable $eax :: (store (s32) into %ir.p, !tbaa !1)
+    ; RCDEFAULT-NEXT: renamable $ax = ADD16rr_ND renamable $ax, renamable $cx, implicit-def dead $eflags, implicit killed $ecx, implicit $eax, implicit-def $rax
+    ; RCDEFAULT-NEXT: RET64 $ax
+    ;
+    ; RC1-LABEL: name: partial_write
+    ; RC1: liveins: $ecx, $edx, $esi, $rdi
+    ; RC1-NEXT: {{  $}}
+    ; RC1-NEXT: renamable $eax = nsw ADD32rr_ND killed renamable $edx, killed renamable $esi, implicit-def dead $eflags
+    ; RC1-NEXT: MOV32mr killed renamable $rdi, 1, $noreg, 0, $noreg, renamable $eax :: (store (s32) into %ir.p, !tbaa !1)
+    ; RC1-NEXT: renamable $ax = ADD16rr_ND renamable $ax, renamable $cx, implicit-def dead $eflags, implicit killed $ecx, implicit $eax
+    ; RC1-NEXT: RET64 $ax
+    renamable $eax = nsw ADD32rr_ND killed renamable $edx, killed renamable $esi, implicit-def dead $eflags
+    MOV32mr killed renamable $rdi, 1, $noreg, 0, $noreg, renamable $eax :: (store (s32) into %ir.p, !tbaa !1)
+    renamable $ax = ADD16rr_ND renamable $ax, renamable $cx, implicit-def dead $eflags, implicit killed $ecx, implicit $eax
+    RET64 $ax
+...
+---
+name:            no_partial_write
+tracksRegLiveness: true
+noVRegs:         true
+noPhis:          true
+isSSA:           false
+body:             |
+  bb.0.entry:
+    liveins: $ecx, $edx, $esi, $rdi
+
+    ; MIR-LABEL: name: no_partial_write
+    ; MIR: liveins: $ecx, $edx, $esi, $rdi
+    ; MIR-NEXT: {{  $}}
+    ; MIR-NEXT: renamable $edx = nsw ADD32rr_ND killed renamable $edx, killed renamable $esi, implicit-def dead $eflags
+    ; MIR-NEXT: MOV32mr killed renamable $rdi, 1, $noreg, 0, $noreg, renamable $edx :: (store (s32) into %ir.p, !tbaa !1)
+    ; MIR-NEXT: renamable $ax = ADD16rr_ND renamable $dx, renamable $cx, implicit-def dead $eflags, implicit killed $ecx, implicit killed $edx
+    ; MIR-NEXT: RET64 $ax
+    renamable $edx = nsw ADD32rr_ND killed renamable $edx, killed renamable $esi, implicit-def dead $eflags
+    MOV32mr killed renamable $rdi, 1, $noreg, 0, $noreg, renamable $edx :: (store (s32) into %ir.p, !tbaa !1)
+    renamable $ax = ADD16rr_ND renamable $dx, renamable $cx, implicit-def dead $eflags, implicit killed $ecx, implicit killed $edx
+    RET64 $ax
+...
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+# MIR: {{.*}}
+# RC1: {{.*}}
+# RCDEFAULT: {{.*}}
----------------
phoebewang wrote:

What's the problem here? The prefixes are there, did you manually edit them? If you do, remove the autogenerated note and these comments.

https://github.com/llvm/llvm-project/pull/132051