[clang] [llvm] [X86][AVX10.2] Remove YMM rounding from VCVT[,T]PS2I[,U]BS (PR #132426)
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 21 10:10:03 PDT 2025
https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/132426
Ref: https://cdrdv2.intel.com/v1/dl/getContent/784343
>From 3d393696f47c30c48a485cf7ac1a0315287f8105 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe" <phoebe.wang at intel.com>
Date: Sat, 22 Mar 2025 01:07:17 +0800
Subject: [PATCH] [X86][AVX10.2] Remove YMM rounding from VCVT[,T]PS2I[,U]BS
Ref: https://cdrdv2.intel.com/v1/dl/getContent/784343
---
clang/include/clang/Basic/BuiltinsX86.td | 16 +-
clang/lib/Headers/avx10_2satcvtintrin.h | 196 ++------
clang/lib/Sema/SemaX86.cpp | 8 -
.../X86/avx10_2_512satcvt-builtins-error.c | 198 --------
.../test/CodeGen/X86/avx10_2satcvt-builtins.c | 142 ------
llvm/include/llvm/IR/IntrinsicsX86.td | 32 +-
llvm/lib/Target/X86/X86InstrAVX10.td | 19 -
llvm/lib/Target/X86/X86IntrinsicsInfo.h | 24 +-
.../CodeGen/X86/avx10_2satcvt-intrinsics.ll | 448 ++----------------
.../MC/Disassembler/X86/avx10.2-satcvt-32.txt | 64 ---
.../MC/Disassembler/X86/avx10.2-satcvt-64.txt | 64 ---
llvm/test/MC/X86/avx10.2satcvt-32-att.s | 64 ---
llvm/test/MC/X86/avx10.2satcvt-32-intel.s | 64 ---
llvm/test/MC/X86/avx10.2satcvt-64-att.s | 64 ---
llvm/test/MC/X86/avx10.2satcvt-64-intel.s | 64 ---
15 files changed, 100 insertions(+), 1367 deletions(-)
delete mode 100755 clang/test/CodeGen/X86/avx10_2_512satcvt-builtins-error.c
diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td
index ea0d6df4a33c2..0e3e6a120f83b 100644
--- a/clang/include/clang/Basic/BuiltinsX86.td
+++ b/clang/include/clang/Basic/BuiltinsX86.td
@@ -4886,7 +4886,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvtph2ibs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short, _Constant int)">;
+ def vcvtph2ibs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4898,7 +4898,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvtph2iubs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short, _Constant int)">;
+ def vcvtph2iubs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4910,7 +4910,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvtps2ibs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char, _Constant int)">;
+ def vcvtps2ibs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4922,7 +4922,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvtps2iubs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char, _Constant int)">;
+ def vcvtps2iubs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4958,7 +4958,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttph2ibs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short, _Constant int)">;
+ def vcvttph2ibs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4970,7 +4970,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttph2iubs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short, _Constant int)">;
+ def vcvttph2iubs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4982,7 +4982,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttps2ibs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char, _Constant int)">;
+ def vcvttps2ibs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4994,7 +4994,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttps2iubs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char, _Constant int)">;
+ def vcvttps2iubs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
diff --git a/clang/lib/Headers/avx10_2satcvtintrin.h b/clang/lib/Headers/avx10_2satcvtintrin.h
index f0e6eba4bab81..2f1fad9eff730 100644
--- a/clang/lib/Headers/avx10_2satcvtintrin.h
+++ b/clang/lib/Headers/avx10_2satcvtintrin.h
@@ -66,7 +66,7 @@
#define _mm_ipcvts_ph_epi8(A) \
((__m128i)__builtin_ia32_vcvtph2ibs128_mask( \
- (__v8hf)(__m128h)(A), (__v8hu)_mm_setzero_si128(), (__mmask8) - 1))
+ (__v8hf)(__m128h)(A), (__v8hu)_mm_setzero_si128(), (__mmask8)-1))
#define _mm_mask_ipcvts_ph_epi8(W, U, A) \
((__m128i)__builtin_ia32_vcvtph2ibs128_mask((__v8hf)(__m128h)(A), \
@@ -78,36 +78,20 @@
#define _mm256_ipcvts_ph_epi8(A) \
((__m256i)__builtin_ia32_vcvtph2ibs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16) - 1, \
- _MM_FROUND_CUR_DIRECTION))
+ (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16)-1))
#define _mm256_mask_ipcvts_ph_epi8(W, U, A) \
((__m256i)__builtin_ia32_vcvtph2ibs256_mask((__v16hf)(__m256h)(A), \
- (__v16hu)(W), (__mmask16)(U), \
- _MM_FROUND_CUR_DIRECTION))
+ (__v16hu)(W), (__mmask16)(U)))
#define _mm256_maskz_ipcvts_ph_epi8(U, A) \
((__m256i)__builtin_ia32_vcvtph2ibs256_mask( \
(__v16hf)(__m256h)(A), (__v16hu)(_mm256_setzero_si256()), \
- (__mmask16)(U), _MM_FROUND_CUR_DIRECTION))
-
-#define _mm256_ipcvts_roundph_epi8(A, R) \
- ((__m256i)__builtin_ia32_vcvtph2ibs256_mask((__v16hf)(__m256h)(A), \
- (__v16hu)_mm256_setzero_si256(), \
- (__mmask16) - 1, (const int)R))
-
-#define _mm256_mask_ipcvts_roundph_epi8(W, U, A, R) \
- ((__m256i)__builtin_ia32_vcvtph2ibs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)(W), (__mmask16)(U), (const int)R))
-
-#define _mm256_maskz_ipcvts_roundph_epi8(U, A, R) \
- ((__m256i)__builtin_ia32_vcvtph2ibs256_mask((__v16hf)(__m256h)(A), \
- (__v16hu)_mm256_setzero_si256(), \
- (__mmask16)(U), (const int)R))
+ (__mmask16)(U)))
#define _mm_ipcvts_ph_epu8(A) \
((__m128i)__builtin_ia32_vcvtph2iubs128_mask( \
- (__v8hf)(__m128h)(A), (__v8hu)_mm_setzero_si128(), (__mmask8) - 1))
+ (__v8hf)(__m128h)(A), (__v8hu)_mm_setzero_si128(), (__mmask8)-1))
#define _mm_mask_ipcvts_ph_epu8(W, U, A) \
((__m128i)__builtin_ia32_vcvtph2iubs128_mask((__v8hf)(__m128h)(A), \
@@ -119,36 +103,20 @@
#define _mm256_ipcvts_ph_epu8(A) \
((__m256i)__builtin_ia32_vcvtph2iubs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16) - 1, \
- _MM_FROUND_CUR_DIRECTION))
+ (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16)-1))
#define _mm256_mask_ipcvts_ph_epu8(W, U, A) \
((__m256i)__builtin_ia32_vcvtph2iubs256_mask((__v16hf)(__m256h)(A), \
- (__v16hu)(W), (__mmask16)(U), \
- _MM_FROUND_CUR_DIRECTION))
+ (__v16hu)(W), (__mmask16)(U)))
#define _mm256_maskz_ipcvts_ph_epu8(U, A) \
((__m256i)__builtin_ia32_vcvtph2iubs256_mask( \
(__v16hf)(__m256h)(A), (__v16hu)(_mm256_setzero_si256()), \
- (__mmask16)(U), _MM_FROUND_CUR_DIRECTION))
-
-#define _mm256_ipcvts_roundph_epu8(A, R) \
- ((__m256i)__builtin_ia32_vcvtph2iubs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16) - 1, \
- (const int)R))
-
-#define _mm256_mask_ipcvts_roundph_epu8(W, U, A, R) \
- ((__m256i)__builtin_ia32_vcvtph2iubs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)(W), (__mmask16)(U), (const int)R))
-
-#define _mm256_maskz_ipcvts_roundph_epu8(U, A, R) \
- ((__m256i)__builtin_ia32_vcvtph2iubs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16)(U), \
- (const int)R))
+ (__mmask16)(U)))
#define _mm_ipcvts_ps_epi8(A) \
((__m128i)__builtin_ia32_vcvtps2ibs128_mask( \
- (__v4sf)(__m128)(A), (__v4su)_mm_setzero_si128(), (__mmask8) - 1))
+ (__v4sf)(__m128)(A), (__v4su)_mm_setzero_si128(), (__mmask8)-1))
#define _mm_mask_ipcvts_ps_epi8(W, U, A) \
((__m128i)__builtin_ia32_vcvtps2ibs128_mask((__v4sf)(__m128)(A), \
@@ -160,36 +128,19 @@
#define _mm256_ipcvts_ps_epi8(A) \
((__m256i)__builtin_ia32_vcvtps2ibs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)_mm256_setzero_si256(), (__mmask8) - 1, \
- _MM_FROUND_CUR_DIRECTION))
+ (__v8sf)(__m256)(A), (__v8su)_mm256_setzero_si256(), (__mmask8)-1))
#define _mm256_mask_ipcvts_ps_epi8(W, U, A) \
((__m256i)__builtin_ia32_vcvtps2ibs256_mask((__v8sf)(__m256)(A), \
- (__v8su)(W), (__mmask8)(U), \
- _MM_FROUND_CUR_DIRECTION))
+ (__v8su)(W), (__mmask8)(U)))
#define _mm256_maskz_ipcvts_ps_epi8(U, A) \
((__m256i)__builtin_ia32_vcvtps2ibs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)(_mm256_setzero_si256()), (__mmask8)(U), \
- _MM_FROUND_CUR_DIRECTION))
-
-#define _mm256_ipcvts_roundps_epi8(A, R) \
- ((__m256i)__builtin_ia32_vcvtps2ibs256_mask((__v8sf)(__m256)(A), \
- (__v8su)_mm256_setzero_si256(), \
- (__mmask8) - 1, (const int)R))
-
-#define _mm256_mask_ipcvts_roundps_epi8(W, U, A, R) \
- ((__m256i)__builtin_ia32_vcvtps2ibs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)(W), (__mmask8)(U), (const int)R))
-
-#define _mm256_maskz_ipcvts_roundps_epi8(U, A, R) \
- ((__m256i)__builtin_ia32_vcvtps2ibs256_mask((__v8sf)(__m256)(A), \
- (__v8su)_mm256_setzero_si256(), \
- (__mmask8)(U), (const int)R))
+ (__v8sf)(__m256)(A), (__v8su)(_mm256_setzero_si256()), (__mmask8)(U)))
#define _mm_ipcvts_ps_epu8(A) \
((__m128i)__builtin_ia32_vcvtps2iubs128_mask( \
- (__v4sf)(__m128)(A), (__v4su)_mm_setzero_si128(), (__mmask8) - 1))
+ (__v4sf)(__m128)(A), (__v4su)_mm_setzero_si128(), (__mmask8)-1))
#define _mm_mask_ipcvts_ps_epu8(W, U, A) \
((__m128i)__builtin_ia32_vcvtps2iubs128_mask((__v4sf)(__m128)(A), \
@@ -201,32 +152,15 @@
#define _mm256_ipcvts_ps_epu8(A) \
((__m256i)__builtin_ia32_vcvtps2iubs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)_mm256_setzero_si256(), (__mmask8) - 1, \
- _MM_FROUND_CUR_DIRECTION))
+ (__v8sf)(__m256)(A), (__v8su)_mm256_setzero_si256(), (__mmask8)-1))
#define _mm256_mask_ipcvts_ps_epu8(W, U, A) \
((__m256i)__builtin_ia32_vcvtps2iubs256_mask((__v8sf)(__m256)(A), \
- (__v8su)(W), (__mmask8)(U), \
- _MM_FROUND_CUR_DIRECTION))
+ (__v8su)(W), (__mmask8)(U)))
#define _mm256_maskz_ipcvts_ps_epu8(U, A) \
((__m256i)__builtin_ia32_vcvtps2iubs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)(_mm256_setzero_si256()), (__mmask8)(U), \
- _MM_FROUND_CUR_DIRECTION))
-
-#define _mm256_ipcvts_roundps_epu8(A, R) \
- ((__m256i)__builtin_ia32_vcvtps2iubs256_mask((__v8sf)(__m256)(A), \
- (__v8su)_mm256_setzero_si256(), \
- (__mmask8) - 1, (const int)R))
-
-#define _mm256_mask_ipcvts_roundps_epu8(W, U, A, R) \
- ((__m256i)__builtin_ia32_vcvtps2iubs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)(W), (__mmask8)(U), (const int)R))
-
-#define _mm256_maskz_ipcvts_roundps_epu8(U, A, R) \
- ((__m256i)__builtin_ia32_vcvtps2iubs256_mask((__v8sf)(__m256)(A), \
- (__v8su)_mm256_setzero_si256(), \
- (__mmask8)(U), (const int)R))
+ (__v8sf)(__m256)(A), (__v8su)(_mm256_setzero_si256()), (__mmask8)(U)))
#define _mm_ipcvtts_bf16_epi8(A) \
((__m128i)__builtin_ia32_vcvttbf162ibs128((__v8bf)(__m128bh)(A)))
@@ -280,7 +214,7 @@
#define _mm_ipcvtts_ph_epi8(A) \
((__m128i)__builtin_ia32_vcvttph2ibs128_mask( \
- (__v8hf)(__m128h)(A), (__v8hu)_mm_setzero_si128(), (__mmask8) - 1))
+ (__v8hf)(__m128h)(A), (__v8hu)_mm_setzero_si128(), (__mmask8)-1))
#define _mm_mask_ipcvtts_ph_epi8(W, U, A) \
((__m128i)__builtin_ia32_vcvttph2ibs128_mask((__v8hf)(__m128h)(A), \
@@ -292,36 +226,20 @@
#define _mm256_ipcvtts_ph_epi8(A) \
((__m256i)__builtin_ia32_vcvttph2ibs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16) - 1, \
- _MM_FROUND_CUR_DIRECTION))
+ (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16)-1))
#define _mm256_mask_ipcvtts_ph_epi8(W, U, A) \
((__m256i)__builtin_ia32_vcvttph2ibs256_mask((__v16hf)(__m256h)(A), \
- (__v16hu)(W), (__mmask16)(U), \
- _MM_FROUND_CUR_DIRECTION))
+ (__v16hu)(W), (__mmask16)(U)))
#define _mm256_maskz_ipcvtts_ph_epi8(U, A) \
((__m256i)__builtin_ia32_vcvttph2ibs256_mask( \
(__v16hf)(__m256h)(A), (__v16hu)(_mm256_setzero_si256()), \
- (__mmask16)(U), _MM_FROUND_CUR_DIRECTION))
-
-#define _mm256_ipcvtts_roundph_epi8(A, R) \
- ((__m256i)__builtin_ia32_vcvttph2ibs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16) - 1, \
- (const int)R))
-
-#define _mm256_mask_ipcvtts_roundph_epi8(W, U, A, R) \
- ((__m256i)__builtin_ia32_vcvttph2ibs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)(W), (__mmask16)(U), (const int)R))
-
-#define _mm256_maskz_ipcvtts_roundph_epi8(U, A, R) \
- ((__m256i)__builtin_ia32_vcvttph2ibs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16)(U), \
- (const int)R))
+ (__mmask16)(U)))
#define _mm_ipcvtts_ph_epu8(A) \
((__m128i)__builtin_ia32_vcvttph2iubs128_mask( \
- (__v8hf)(__m128h)(A), (__v8hu)_mm_setzero_si128(), (__mmask8) - 1))
+ (__v8hf)(__m128h)(A), (__v8hu)_mm_setzero_si128(), (__mmask8)-1))
#define _mm_mask_ipcvtts_ph_epu8(W, U, A) \
((__m128i)__builtin_ia32_vcvttph2iubs128_mask((__v8hf)(__m128h)(A), \
@@ -333,36 +251,20 @@
#define _mm256_ipcvtts_ph_epu8(A) \
((__m256i)__builtin_ia32_vcvttph2iubs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16) - 1, \
- _MM_FROUND_CUR_DIRECTION))
+ (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16)-1))
#define _mm256_mask_ipcvtts_ph_epu8(W, U, A) \
((__m256i)__builtin_ia32_vcvttph2iubs256_mask((__v16hf)(__m256h)(A), \
- (__v16hu)(W), (__mmask16)(U), \
- _MM_FROUND_CUR_DIRECTION))
+ (__v16hu)(W), (__mmask16)(U)))
#define _mm256_maskz_ipcvtts_ph_epu8(U, A) \
((__m256i)__builtin_ia32_vcvttph2iubs256_mask( \
(__v16hf)(__m256h)(A), (__v16hu)(_mm256_setzero_si256()), \
- (__mmask16)(U), _MM_FROUND_CUR_DIRECTION))
-
-#define _mm256_ipcvtts_roundph_epu8(A, R) \
- ((__m256i)__builtin_ia32_vcvttph2iubs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16) - 1, \
- (const int)R))
-
-#define _mm256_mask_ipcvtts_roundph_epu8(W, U, A, R) \
- ((__m256i)__builtin_ia32_vcvttph2iubs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)(W), (__mmask16)(U), (const int)R))
-
-#define _mm256_maskz_ipcvtts_roundph_epu8(U, A, R) \
- ((__m256i)__builtin_ia32_vcvttph2iubs256_mask( \
- (__v16hf)(__m256h)(A), (__v16hu)_mm256_setzero_si256(), (__mmask16)(U), \
- (const int)R))
+ (__mmask16)(U)))
#define _mm_ipcvtts_ps_epi8(A) \
((__m128i)__builtin_ia32_vcvttps2ibs128_mask( \
- (__v4sf)(__m128)(A), (__v4su)_mm_setzero_si128(), (__mmask8) - 1))
+ (__v4sf)(__m128)(A), (__v4su)_mm_setzero_si128(), (__mmask8)-1))
#define _mm_mask_ipcvtts_ps_epi8(W, U, A) \
((__m128i)__builtin_ia32_vcvttps2ibs128_mask((__v4sf)(__m128)(A), \
@@ -374,36 +276,19 @@
#define _mm256_ipcvtts_ps_epi8(A) \
((__m256i)__builtin_ia32_vcvttps2ibs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)_mm256_setzero_si256(), (__mmask8) - 1, \
- _MM_FROUND_CUR_DIRECTION))
+ (__v8sf)(__m256)(A), (__v8su)_mm256_setzero_si256(), (__mmask8)-1))
#define _mm256_mask_ipcvtts_ps_epi8(W, U, A) \
((__m256i)__builtin_ia32_vcvttps2ibs256_mask((__v8sf)(__m256)(A), \
- (__v8su)(W), (__mmask8)(U), \
- _MM_FROUND_CUR_DIRECTION))
+ (__v8su)(W), (__mmask8)(U)))
#define _mm256_maskz_ipcvtts_ps_epi8(U, A) \
((__m256i)__builtin_ia32_vcvttps2ibs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)(_mm256_setzero_si256()), (__mmask8)(U), \
- _MM_FROUND_CUR_DIRECTION))
-
-#define _mm256_ipcvtts_roundps_epi8(A, R) \
- ((__m256i)__builtin_ia32_vcvttps2ibs256_mask((__v8sf)(__m256)(A), \
- (__v8su)_mm256_setzero_si256(), \
- (__mmask8) - 1, (const int)R))
-
-#define _mm256_mask_ipcvtts_roundps_epi8(W, U, A, R) \
- ((__m256i)__builtin_ia32_vcvttps2ibs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)(W), (__mmask8)(U), (const int)R))
-
-#define _mm256_maskz_ipcvtts_roundps_epi8(U, A, R) \
- ((__m256i)__builtin_ia32_vcvttps2ibs256_mask((__v8sf)(__m256)(A), \
- (__v8su)_mm256_setzero_si256(), \
- (__mmask8)(U), (const int)R))
+ (__v8sf)(__m256)(A), (__v8su)(_mm256_setzero_si256()), (__mmask8)(U)))
#define _mm_ipcvtts_ps_epu8(A) \
((__m128i)__builtin_ia32_vcvttps2iubs128_mask( \
- (__v4sf)(__m128)(A), (__v4su)_mm_setzero_si128(), (__mmask8) - 1))
+ (__v4sf)(__m128)(A), (__v4su)_mm_setzero_si128(), (__mmask8)-1))
#define _mm_mask_ipcvtts_ps_epu8(W, U, A) \
((__m128i)__builtin_ia32_vcvttps2iubs128_mask((__v4sf)(__m128)(A), \
@@ -415,30 +300,13 @@
#define _mm256_ipcvtts_ps_epu8(A) \
((__m256i)__builtin_ia32_vcvttps2iubs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)_mm256_setzero_si256(), (__mmask8) - 1, \
- _MM_FROUND_CUR_DIRECTION))
+ (__v8sf)(__m256)(A), (__v8su)_mm256_setzero_si256(), (__mmask8)-1))
#define _mm256_mask_ipcvtts_ps_epu8(W, U, A) \
((__m256i)__builtin_ia32_vcvttps2iubs256_mask((__v8sf)(__m256)(A), \
- (__v8su)(W), (__mmask8)(U), \
- _MM_FROUND_CUR_DIRECTION))
+ (__v8su)(W), (__mmask8)(U)))
#define _mm256_maskz_ipcvtts_ps_epu8(U, A) \
((__m256i)__builtin_ia32_vcvttps2iubs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)(_mm256_setzero_si256()), (__mmask8)(U), \
- _MM_FROUND_CUR_DIRECTION))
-
-#define _mm256_ipcvtts_roundps_epu8(A, R) \
- ((__m256i)__builtin_ia32_vcvttps2iubs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)_mm256_setzero_si256(), (__mmask8) - 1, \
- (const int)R))
-
-#define _mm256_mask_ipcvtts_roundps_epu8(W, U, A, R) \
- ((__m256i)__builtin_ia32_vcvttps2iubs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)(W), (__mmask8)(U), (const int)R))
-
-#define _mm256_maskz_ipcvtts_roundps_epu8(U, A, R) \
- ((__m256i)__builtin_ia32_vcvttps2iubs256_mask( \
- (__v8sf)(__m256)(A), (__v8su)_mm256_setzero_si256(), (__mmask8)(U), \
- (const int)R))
+ (__v8sf)(__m256)(A), (__v8su)(_mm256_setzero_si256()), (__mmask8)(U)))
#endif // __AVX10_2SATCVTINTRIN_H
diff --git a/clang/lib/Sema/SemaX86.cpp b/clang/lib/Sema/SemaX86.cpp
index e54a278225f1c..4c6f9f8cd28cd 100644
--- a/clang/lib/Sema/SemaX86.cpp
+++ b/clang/lib/Sema/SemaX86.cpp
@@ -88,10 +88,6 @@ bool SemaX86::CheckBuiltinRoundingOrSAE(unsigned BuiltinID, CallExpr *TheCall) {
case X86::BI__builtin_ia32_vcomiss:
case X86::BI__builtin_ia32_vcomish:
case X86::BI__builtin_ia32_vcvtph2ps512_mask:
- case X86::BI__builtin_ia32_vcvttph2ibs256_mask:
- case X86::BI__builtin_ia32_vcvttph2iubs256_mask:
- case X86::BI__builtin_ia32_vcvttps2ibs256_mask:
- case X86::BI__builtin_ia32_vcvttps2iubs256_mask:
case X86::BI__builtin_ia32_vcvttph2ibs512_mask:
case X86::BI__builtin_ia32_vcvttph2iubs512_mask:
case X86::BI__builtin_ia32_vcvttps2ibs512_mask:
@@ -230,10 +226,6 @@ bool SemaX86::CheckBuiltinRoundingOrSAE(unsigned BuiltinID, CallExpr *TheCall) {
case X86::BI__builtin_ia32_vcvtph2uqq512_mask:
case X86::BI__builtin_ia32_vcvtqq2ph512_mask:
case X86::BI__builtin_ia32_vcvtuqq2ph512_mask:
- case X86::BI__builtin_ia32_vcvtph2ibs256_mask:
- case X86::BI__builtin_ia32_vcvtph2iubs256_mask:
- case X86::BI__builtin_ia32_vcvtps2ibs256_mask:
- case X86::BI__builtin_ia32_vcvtps2iubs256_mask:
case X86::BI__builtin_ia32_vcvtph2ibs512_mask:
case X86::BI__builtin_ia32_vcvtph2iubs512_mask:
case X86::BI__builtin_ia32_vcvtps2ibs512_mask:
diff --git a/clang/test/CodeGen/X86/avx10_2_512satcvt-builtins-error.c b/clang/test/CodeGen/X86/avx10_2_512satcvt-builtins-error.c
deleted file mode 100755
index 64a16de3b5f61..0000000000000
--- a/clang/test/CodeGen/X86/avx10_2_512satcvt-builtins-error.c
+++ /dev/null
@@ -1,198 +0,0 @@
-// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2-512 \
-// RUN: -Wall -Werror -verify
-// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2-512 \
-// RUN: -Wall -Werror -verify
-
-#include <immintrin.h>
-
-__m512i test_mm512_ipcvts_roundph_epi8(__m512h __A) {
- return _mm512_ipcvts_roundph_epi8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_mask_ipcvts_roundph_epi8(__m512i __S, __mmask32 __A, __m512h __B) {
- return _mm512_mask_ipcvts_roundph_epi8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_maskz_ipcvts_roundph_epi8(__mmask32 __A, __m512h __B) {
- return _mm512_maskz_ipcvts_roundph_epi8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_ipcvts_roundph_epu8(__m512h __A) {
- return _mm512_ipcvts_roundph_epu8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_mask_ipcvts_roundph_epu8(__m512i __S, __mmask32 __A, __m512h __B) {
- return _mm512_mask_ipcvts_roundph_epu8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_maskz_ipcvts_roundph_epu8(__mmask32 __A, __m512h __B) {
- return _mm512_maskz_ipcvts_roundph_epu8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_ipcvts_roundps_epi8(__m512 __A) {
- return _mm512_ipcvts_roundps_epi8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_mask_ipcvts_roundps_epi8(__m512i __S, __mmask16 __A, __m512 __B) {
- return _mm512_mask_ipcvts_roundps_epi8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_maskz_ipcvts_roundps_epi8(__mmask16 __A, __m512 __B) {
- return _mm512_maskz_ipcvts_roundps_epi8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_ipcvts_roundps_epu8(__m512 __A) {
- return _mm512_ipcvts_roundps_epu8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_mask_ipcvts_roundps_epu8(__m512i __S, __mmask16 __A, __m512 __B) {
- return _mm512_mask_ipcvts_roundps_epu8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_maskz_ipcvts_roundps_epu8(__mmask16 __A, __m512 __B) {
- return _mm512_maskz_ipcvts_roundps_epu8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_ipcvtts_roundph_epi8(__m512h __A) {
- return _mm512_ipcvtts_roundph_epi8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_mask_ipcvtts_roundph_epi8(__m512i __S, __mmask32 __A, __m512h __B) {
- return _mm512_mask_ipcvtts_roundph_epi8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_maskz_ipcvtts_roundph_epi8(__mmask32 __A, __m512h __B) {
- return _mm512_maskz_ipcvtts_roundph_epi8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_ipcvtts_roundph_epu8(__m512h __A) {
- return _mm512_ipcvtts_roundph_epu8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_mask_ipcvtts_roundph_epu8(__m512i __S, __mmask32 __A, __m512h __B) {
- return _mm512_mask_ipcvtts_roundph_epu8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_maskz_ipcvtts_roundph_epu8(__mmask32 __A, __m512h __B) {
- return _mm512_maskz_ipcvtts_roundph_epu8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_ipcvtts_roundps_epi8(__m512 __A) {
- return _mm512_ipcvtts_roundps_epi8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_mask_ipcvtts_roundps_epi8(__m512i __S, __mmask16 __A, __m512 __B) {
- return _mm512_mask_ipcvtts_roundps_epi8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_maskz_ipcvtts_roundps_epi8(__mmask16 __A, __m512 __B) {
- return _mm512_maskz_ipcvtts_roundps_epi8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_ipcvtts_roundps_epu8(__m512 __A) {
- return _mm512_ipcvtts_roundps_epu8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_mask_ipcvtts_roundps_epu8(__m512i __S, __mmask16 __A, __m512 __B) {
- return _mm512_mask_ipcvtts_roundps_epu8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m512i test_mm512_maskz_ipcvtts_roundps_epu8(__mmask16 __A, __m512 __B) {
- return _mm512_maskz_ipcvtts_roundps_epu8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_ipcvts_roundph_epi8(__m256h __A) {
- return _mm256_ipcvts_roundph_epi8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_mask_ipcvts_roundph_epi8(__m256i __S, __mmask16 __A, __m256h __B) {
- return _mm256_mask_ipcvts_roundph_epi8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_maskz_ipcvts_roundph_epi8(__mmask16 __A, __m256h __B) {
- return _mm256_maskz_ipcvts_roundph_epi8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_ipcvts_roundph_epu8(__m256h __A) {
- return _mm256_ipcvts_roundph_epu8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_mask_ipcvts_roundph_epu8(__m256i __S, __mmask16 __A, __m256h __B) {
- return _mm256_mask_ipcvts_roundph_epu8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_maskz_ipcvts_roundph_epu8(__mmask16 __A, __m256h __B) {
- return _mm256_maskz_ipcvts_roundph_epu8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_ipcvts_roundps_epi8(__m256 __A) {
- return _mm256_ipcvts_roundps_epi8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_mask_ipcvts_roundps_epi8(__m256i __S, __mmask8 __A, __m256 __B) {
- return _mm256_mask_ipcvts_roundps_epi8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_maskz_ipcvts_roundps_epi8(__mmask8 __A, __m256 __B) {
- return _mm256_maskz_ipcvts_roundps_epi8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_ipcvts_roundps_epu8(__m256 __A) {
- return _mm256_ipcvts_roundps_epu8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_mask_ipcvts_roundps_epu8(__m256i __S, __mmask8 __A, __m256 __B) {
- return _mm256_mask_ipcvts_roundps_epu8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_maskz_ipcvts_roundps_epu8(__mmask8 __A, __m256 __B) {
- return _mm256_maskz_ipcvts_roundps_epu8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_ipcvtts_roundph_epi8(__m256h __A) {
- return _mm256_ipcvtts_roundph_epi8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_mask_ipcvtts_roundph_epi8(__m256i __S, __mmask16 __A, __m256h __B) {
- return _mm256_mask_ipcvtts_roundph_epi8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_maskz_ipcvtts_roundph_epi8(__mmask16 __A, __m256h __B) {
- return _mm256_maskz_ipcvtts_roundph_epi8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_ipcvtts_roundph_epu8(__m256h __A) {
- return _mm256_ipcvtts_roundph_epu8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_mask_ipcvtts_roundph_epu8(__m256i __S, __mmask16 __A, __m256h __B) {
- return _mm256_mask_ipcvtts_roundph_epu8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_maskz_ipcvtts_roundph_epu8(__mmask16 __A, __m256h __B) {
- return _mm256_maskz_ipcvtts_roundph_epu8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_ipcvtts_roundps_epi8(__m256 __A) {
- return _mm256_ipcvtts_roundps_epi8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_mask_ipcvtts_roundps_epi8(__m256i __S, __mmask8 __A, __m256 __B) {
- return _mm256_mask_ipcvtts_roundps_epi8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_maskz_ipcvtts_roundps_epi8(__mmask8 __A, __m256 __B) {
- return _mm256_maskz_ipcvtts_roundps_epi8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_ipcvtts_roundps_epu8(__m256 __A) {
- return _mm256_ipcvtts_roundps_epu8(__A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_mask_ipcvtts_roundps_epu8(__m256i __S, __mmask8 __A, __m256 __B) {
- return _mm256_mask_ipcvtts_roundps_epu8(__S, __A, __B, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_maskz_ipcvtts_roundps_epu8(__mmask8 __A, __m256 __B) {
- return _mm256_maskz_ipcvtts_roundps_epu8(__A, __B, 22); // expected-error {{invalid rounding argument}}
-}
diff --git a/clang/test/CodeGen/X86/avx10_2satcvt-builtins.c b/clang/test/CodeGen/X86/avx10_2satcvt-builtins.c
index 8d0e473fed32a..7f30befefffe9 100644
--- a/clang/test/CodeGen/X86/avx10_2satcvt-builtins.c
+++ b/clang/test/CodeGen/X86/avx10_2satcvt-builtins.c
@@ -124,23 +124,6 @@ __m256i test_mm256_maskz_ipcvts_ph_epi8(__mmask16 __A, __m256h __B) {
return _mm256_maskz_ipcvts_ph_epi8(__A, __B);
}
-__m256i test_mm256_ipcvts_roundph_epi8(__m256h __A) {
- // CHECK-LABEL: @test_mm256_ipcvts_roundph_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvtph2ibs256
- return _mm256_ipcvts_roundph_epi8(__A, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_mask_ipcvts_roundph_epi8(__m256i __S, __mmask16 __A, __m256h __B) {
- // CHECK-LABEL: @test_mm256_mask_ipcvts_roundph_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvtph2ibs256
- return _mm256_mask_ipcvts_roundph_epi8(__S, __A, __B, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-__m256i test_mm256_maskz_ipcvts_roundph_epi8(__mmask16 __A, __m256h __B) {
- // CHECK-LABEL: @test_mm256_maskz_ipcvts_roundph_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvtph2ibs256
- return _mm256_maskz_ipcvts_roundph_epi8(__A, __B, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-
__m128i test_mm_ipcvts_ph_epu8(__m128h __A) {
// CHECK-LABEL: @test_mm_ipcvts_ph_epu8(
// CHECK: @llvm.x86.avx10.mask.vcvtph2iubs128
@@ -177,23 +160,6 @@ __m256i test_mm256_maskz_ipcvts_ph_epu8(__mmask16 __A, __m256h __B) {
return _mm256_maskz_ipcvts_ph_epu8(__A, __B);
}
-__m256i test_mm256_ipcvts_roundph_epu8(__m256h __A) {
- // CHECK-LABEL: @test_mm256_ipcvts_roundph_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvtph2iubs256
- return _mm256_ipcvts_roundph_epu8(__A, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_mask_ipcvts_roundph_epu8(__m256i __S, __mmask16 __A, __m256h __B) {
- // CHECK-LABEL: @test_mm256_mask_ipcvts_roundph_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvtph2iubs256
- return _mm256_mask_ipcvts_roundph_epu8(__S, __A, __B, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-__m256i test_mm256_maskz_ipcvts_roundph_epu8(__mmask16 __A, __m256h __B) {
- // CHECK-LABEL: @test_mm256_maskz_ipcvts_roundph_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvtph2iubs256
- return _mm256_maskz_ipcvts_roundph_epu8(__A, __B, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-
__m128i test_mm_ipcvts_ps_epi8(__m128 __A) {
// CHECK-LABEL: @test_mm_ipcvts_ps_epi8(
// CHECK: @llvm.x86.avx10.mask.vcvtps2ibs128
@@ -230,24 +196,6 @@ __m256i test_mm256_maskz_ipcvts_ps_epi8(__mmask8 __A, __m256 __B) {
return _mm256_maskz_ipcvts_ps_epi8(__A, __B);
}
-__m256i test_mm256_ipcvts_roundps_epi8(__m256 __A) {
- // CHECK-LABEL: @test_mm256_ipcvts_roundps_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvtps2ibs256
- return _mm256_ipcvts_roundps_epi8(__A, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_mask_ipcvts_roundps_epi8(__m256i __S, __mmask8 __A, __m256 __B) {
- // CHECK-LABEL: @test_mm256_mask_ipcvts_roundps_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvtps2ibs256
- return _mm256_mask_ipcvts_roundps_epi8(__S, __A, __B, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_maskz_ipcvts_roundps_epi8(__mmask8 __A, __m256 __B) {
- // CHECK-LABEL: @test_mm256_maskz_ipcvts_roundps_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvtps2ibs256
- return _mm256_maskz_ipcvts_roundps_epi8(__A, __B, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-
__m128i test_mm_ipcvts_ps_epu8(__m128 __A) {
// CHECK-LABEL: @test_mm_ipcvts_ps_epu8(
// CHECK: @llvm.x86.avx10.mask.vcvtps2iubs128
@@ -284,24 +232,6 @@ __m256i test_mm256_maskz_ipcvts_ps_epu8(__mmask8 __A, __m256 __B) {
return _mm256_maskz_ipcvts_ps_epu8(__A, __B);
}
-__m256i test_mm256_ipcvts_roundps_epu8(__m256 __A) {
- // CHECK-LABEL: @test_mm256_ipcvts_roundps_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvtps2iubs256
- return _mm256_ipcvts_roundps_epu8(__A, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_mask_ipcvts_roundps_epu8(__m256i __S, __mmask8 __A, __m256 __B) {
- // CHECK-LABEL: @test_mm256_mask_ipcvts_roundps_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvtps2iubs256
- return _mm256_mask_ipcvts_roundps_epu8(__S, __A, __B, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_maskz_ipcvts_roundps_epu8(__mmask8 __A, __m256 __B) {
- // CHECK-LABEL: @test_mm256_maskz_ipcvts_roundps_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvtps2iubs256
- return _mm256_maskz_ipcvts_roundps_epu8(__A, __B, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
-}
-
__m128i test_mm_ipcvtts_bf16_epi8(__m128bh __A) {
// CHECK-LABEL: @test_mm_ipcvtts_bf16_epi8(
// CHECK: @llvm.x86.avx10.vcvttbf162ibs128
@@ -422,24 +352,6 @@ __m256i test_mm256_maskz_ipcvtts_ph_epi8(__mmask16 __A, __m256h __B) {
return _mm256_maskz_ipcvtts_ph_epi8(__A, __B);
}
-__m256i test_mm256_ipcvtts_roundph_epi8(__m256h __A) {
- // CHECK-LABEL: @test_mm256_ipcvtts_roundph_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvttph2ibs256
- return _mm256_ipcvtts_roundph_epi8(__A, _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_mask_ipcvtts_roundph_epi8(__m256i __S, __mmask16 __A, __m256h __B) {
- // CHECK-LABEL: @test_mm256_mask_ipcvtts_roundph_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvttph2ibs256
- return _mm256_mask_ipcvtts_roundph_epi8(__S, __A, __B, _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_maskz_ipcvtts_roundph_epi8(__mmask16 __A, __m256h __B) {
- // CHECK-LABEL: @test_mm256_maskz_ipcvtts_roundph_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvttph2ibs256
- return _mm256_maskz_ipcvtts_roundph_epi8(__A, __B, _MM_FROUND_NO_EXC);
-}
-
__m128i test_mm_ipcvtts_ph_epu8(__m128h __A) {
// CHECK-LABEL: @test_mm_ipcvtts_ph_epu8(
// CHECK: @llvm.x86.avx10.mask.vcvttph2iubs128
@@ -476,24 +388,6 @@ __m256i test_mm256_maskz_ipcvtts_ph_epu8(__mmask16 __A, __m256h __B) {
return _mm256_maskz_ipcvtts_ph_epu8(__A, __B);
}
-__m256i test_mm256_ipcvtts_roundph_epu8(__m256h __A) {
- // CHECK-LABEL: @test_mm256_ipcvtts_roundph_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvttph2iubs256
- return _mm256_ipcvtts_roundph_epu8(__A, _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_mask_ipcvtts_roundph_epu8(__m256i __S, __mmask16 __A, __m256h __B) {
- // CHECK-LABEL: @test_mm256_mask_ipcvtts_roundph_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvttph2iubs256
- return _mm256_mask_ipcvtts_roundph_epu8(__S, __A, __B, _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_maskz_ipcvtts_roundph_epu8(__mmask16 __A, __m256h __B) {
- // CHECK-LABEL: @test_mm256_maskz_ipcvtts_roundph_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvttph2iubs256
- return _mm256_maskz_ipcvtts_roundph_epu8(__A, __B, _MM_FROUND_NO_EXC);
-}
-
__m128i test_mm_ipcvtts_ps_epi8(__m128 __A) {
// CHECK-LABEL: @test_mm_ipcvtts_ps_epi8(
// CHECK: @llvm.x86.avx10.mask.vcvttps2ibs128
@@ -530,24 +424,6 @@ __m256i test_mm256_maskz_ipcvtts_ps_epi8(__mmask8 __A, __m256 __B) {
return _mm256_maskz_ipcvtts_ps_epi8(__A, __B);
}
-__m256i test_mm256_ipcvtts_roundps_epi8(__m256 __A) {
- // CHECK-LABEL: @test_mm256_ipcvtts_roundps_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvttps2ibs256
- return _mm256_ipcvtts_roundps_epi8(__A, _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_mask_ipcvtts_roundps_epi8(__m256i __S, __mmask8 __A, __m256 __B) {
- // CHECK-LABEL: @test_mm256_mask_ipcvtts_roundps_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvttps2ibs256
- return _mm256_mask_ipcvtts_roundps_epi8(__S, __A, __B, _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_maskz_ipcvtts_roundps_epi8(__mmask8 __A, __m256 __B) {
- // CHECK-LABEL: @test_mm256_maskz_ipcvtts_roundps_epi8(
- // CHECK: @llvm.x86.avx10.mask.vcvttps2ibs256
- return _mm256_maskz_ipcvtts_roundps_epi8(__A, __B, _MM_FROUND_NO_EXC);
-}
-
__m128i test_mm_ipcvtts_ps_epu8(__m128 __A) {
// CHECK-LABEL: @test_mm_ipcvtts_ps_epu8(
// CHECK: @llvm.x86.avx10.mask.vcvttps2iubs128
@@ -583,21 +459,3 @@ __m256i test_mm256_maskz_ipcvtts_ps_epu8(__mmask8 __A, __m256 __B) {
// CHECK: @llvm.x86.avx10.mask.vcvttps2iubs256
return _mm256_maskz_ipcvtts_ps_epu8(__A, __B);
}
-
-__m256i test_mm256_ipcvtts_roundps_epu8(__m256 __A) {
- // CHECK-LABEL: @test_mm256_ipcvtts_roundps_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvttps2iubs256
- return _mm256_ipcvtts_roundps_epu8(__A, _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_mask_ipcvtts_roundps_epu8(__m256i __S, __mmask8 __A, __m256 __B) {
- // CHECK-LABEL: @test_mm256_mask_ipcvtts_roundps_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvttps2iubs256
- return _mm256_mask_ipcvtts_roundps_epu8(__S, __A, __B, _MM_FROUND_NO_EXC);
-}
-
-__m256i test_mm256_maskz_ipcvtts_roundps_epu8(__mmask8 __A, __m256 __B) {
- // CHECK-LABEL: @test_mm256_maskz_ipcvtts_roundps_epu8(
- // CHECK: @llvm.x86.avx10.mask.vcvttps2iubs256
- return _mm256_maskz_ipcvtts_roundps_epu8(__A, __B, _MM_FROUND_NO_EXC);
-}
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index 4fcf2ff8f38df..6a152cfa1b155 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -6932,8 +6932,8 @@ def int_x86_avx10_mask_vcvtph2ibs128 : ClangBuiltin<"__builtin_ia32_vcvtph2ibs12
DefaultAttrsIntrinsic<[llvm_v8i16_ty], [llvm_v8f16_ty, llvm_v8i16_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_avx10_mask_vcvtph2ibs256 : ClangBuiltin<"__builtin_ia32_vcvtph2ibs256_mask">,
- DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16f16_ty, llvm_v16i16_ty, llvm_i16_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16f16_ty, llvm_v16i16_ty, llvm_i16_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvtph2ibs512 : ClangBuiltin<"__builtin_ia32_vcvtph2ibs512_mask">,
DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_v32f16_ty, llvm_v32i16_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
@@ -6941,8 +6941,8 @@ def int_x86_avx10_mask_vcvtph2iubs128 : ClangBuiltin<"__builtin_ia32_vcvtph2iubs
DefaultAttrsIntrinsic<[llvm_v8i16_ty], [llvm_v8f16_ty, llvm_v8i16_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_avx10_mask_vcvtph2iubs256 : ClangBuiltin<"__builtin_ia32_vcvtph2iubs256_mask">,
- DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16f16_ty, llvm_v16i16_ty, llvm_i16_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16f16_ty, llvm_v16i16_ty, llvm_i16_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvtph2iubs512 : ClangBuiltin<"__builtin_ia32_vcvtph2iubs512_mask">,
DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_v32f16_ty, llvm_v32i16_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
@@ -6950,8 +6950,8 @@ def int_x86_avx10_mask_vcvtps2ibs128 : ClangBuiltin<"__builtin_ia32_vcvtps2ibs12
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_avx10_mask_vcvtps2ibs256 : ClangBuiltin<"__builtin_ia32_vcvtps2ibs256_mask">,
- DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvtps2ibs512 : ClangBuiltin<"__builtin_ia32_vcvtps2ibs512_mask">,
DefaultAttrsIntrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
@@ -6959,8 +6959,8 @@ def int_x86_avx10_mask_vcvtps2iubs128 : ClangBuiltin<"__builtin_ia32_vcvtps2iubs
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_avx10_mask_vcvtps2iubs256 : ClangBuiltin<"__builtin_ia32_vcvtps2iubs256_mask">,
- DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvtps2iubs512 : ClangBuiltin<"__builtin_ia32_vcvtps2iubs512_mask">,
DefaultAttrsIntrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
@@ -6986,8 +6986,8 @@ def int_x86_avx10_mask_vcvttph2ibs128 : ClangBuiltin<"__builtin_ia32_vcvttph2ibs
DefaultAttrsIntrinsic<[llvm_v8i16_ty], [llvm_v8f16_ty, llvm_v8i16_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_avx10_mask_vcvttph2ibs256 : ClangBuiltin<"__builtin_ia32_vcvttph2ibs256_mask">,
- DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16f16_ty, llvm_v16i16_ty, llvm_i16_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16f16_ty, llvm_v16i16_ty, llvm_i16_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttph2ibs512 : ClangBuiltin<"__builtin_ia32_vcvttph2ibs512_mask">,
DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_v32f16_ty, llvm_v32i16_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
@@ -6995,8 +6995,8 @@ def int_x86_avx10_mask_vcvttph2iubs128 : ClangBuiltin<"__builtin_ia32_vcvttph2iu
DefaultAttrsIntrinsic<[llvm_v8i16_ty], [llvm_v8f16_ty, llvm_v8i16_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_avx10_mask_vcvttph2iubs256 : ClangBuiltin<"__builtin_ia32_vcvttph2iubs256_mask">,
- DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16f16_ty, llvm_v16i16_ty, llvm_i16_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16f16_ty, llvm_v16i16_ty, llvm_i16_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttph2iubs512 : ClangBuiltin<"__builtin_ia32_vcvttph2iubs512_mask">,
DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_v32f16_ty, llvm_v32i16_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
@@ -7004,8 +7004,8 @@ def int_x86_avx10_mask_vcvttps2ibs128 : ClangBuiltin<"__builtin_ia32_vcvttps2ibs
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_avx10_mask_vcvttps2ibs256 : ClangBuiltin<"__builtin_ia32_vcvttps2ibs256_mask">,
- DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttps2ibs512 : ClangBuiltin<"__builtin_ia32_vcvttps2ibs512_mask">,
DefaultAttrsIntrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
@@ -7013,8 +7013,8 @@ def int_x86_avx10_mask_vcvttps2iubs128 : ClangBuiltin<"__builtin_ia32_vcvttps2iu
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_avx10_mask_vcvttps2iubs256 : ClangBuiltin<"__builtin_ia32_vcvttps2iubs256_mask">,
- DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttps2iubs512 : ClangBuiltin<"__builtin_ia32_vcvttps2iubs512_mask">,
DefaultAttrsIntrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
diff --git a/llvm/lib/Target/X86/X86InstrAVX10.td b/llvm/lib/Target/X86/X86InstrAVX10.td
index b368a5299f907..779f7ea03f5d7 100644
--- a/llvm/lib/Target/X86/X86InstrAVX10.td
+++ b/llvm/lib/Target/X86/X86InstrAVX10.td
@@ -219,16 +219,6 @@ multiclass avx10_sat_cvt_rc<bits<8> Opc, string OpStr, X86SchedWriteWidths sched
(MaskNode (SrcInfo.info512.VT SrcInfo.info512.RC:$src),
(i32 timm:$rc)))>,
Sched<[sched.ZMM]>, EVEX, EVEX_RC, EVEX_B;
- let Predicates = [HasAVX10_2], hasEVEX_U = 1 in {
- defm Z256rrb : AVX512_maskable<Opc, MRMSrcReg, DestInfo.info256,
- (outs DestInfo.info256.RC:$dst),
- (ins SrcInfo.info256.RC:$src, AVX512RC:$rc),
- OpStr, "$rc, $src", "$src, $rc",
- (DestInfo.info256.VT
- (MaskNode (SrcInfo.info256.VT SrcInfo.info256.RC:$src),
- (i32 timm:$rc)))>,
- Sched<[sched.YMM]>, EVEX, EVEX_RC, EVEX_B;
- }
}
// Conversion with SAE
@@ -243,15 +233,6 @@ multiclass avx10_sat_cvt_sae<bits<8> Opc, string OpStr, X86SchedWriteWidths sche
(DestInfo.info512.VT
(Node (SrcInfo.info512.VT SrcInfo.info512.RC:$src)))>,
Sched<[sched.ZMM]>, EVEX, EVEX_B;
- let Predicates = [HasAVX10_2], hasEVEX_U = 1 in {
- defm Z256rrb : AVX512_maskable<Opc, MRMSrcReg, DestInfo.info256,
- (outs DestInfo.info256.RC:$dst),
- (ins SrcInfo.info256.RC:$src),
- OpStr, "{sae}, $src", "$src, {sae}",
- (DestInfo.info256.VT
- (Node (SrcInfo.info256.VT SrcInfo.info256.RC:$src)))>,
- Sched<[sched.YMM]>, EVEX, EVEX_B;
- }
}
multiclass avx10_sat_cvt_base<bits<8> Opc, string OpStr, X86SchedWriteWidths sched,
diff --git a/llvm/lib/Target/X86/X86IntrinsicsInfo.h b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
index 31c2bfb8f71c2..a5919f8d2ba75 100644
--- a/llvm/lib/Target/X86/X86IntrinsicsInfo.h
+++ b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
@@ -500,25 +500,25 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(avx10_mask_vcvtph2ibs128, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2IBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtph2ibs256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTP2IBS, X86ISD::CVTP2IBS_RND),
+ X86ISD::CVTP2IBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtph2ibs512, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2IBS, X86ISD::CVTP2IBS_RND),
X86_INTRINSIC_DATA(avx10_mask_vcvtph2iubs128, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2IUBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtph2iubs256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTP2IUBS, X86ISD::CVTP2IUBS_RND),
+ X86ISD::CVTP2IUBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtph2iubs512, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2IUBS, X86ISD::CVTP2IUBS_RND),
X86_INTRINSIC_DATA(avx10_mask_vcvtps2ibs128, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2IBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtps2ibs256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTP2IBS, X86ISD::CVTP2IBS_RND),
+ X86ISD::CVTP2IBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtps2ibs512, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2IBS, X86ISD::CVTP2IBS_RND),
X86_INTRINSIC_DATA(avx10_mask_vcvtps2iubs128, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2IUBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtps2iubs256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTP2IUBS, X86ISD::CVTP2IUBS_RND),
+ X86ISD::CVTP2IUBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvtps2iubs512, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2IUBS, X86ISD::CVTP2IUBS_RND),
X86_INTRINSIC_DATA(avx10_mask_vcvttpd2dqs_128, CVTPD2DQ_MASK,
@@ -547,14 +547,14 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::CVTTP2UIS, X86ISD::CVTTP2UIS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttph2ibs128, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2IBS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttph2ibs256, INTR_TYPE_1OP_MASK_SAE,
- X86ISD::CVTTP2IBS, X86ISD::CVTTP2IBS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttph2ibs256, INTR_TYPE_1OP_MASK,
+ X86ISD::CVTTP2IBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttph2ibs512, INTR_TYPE_1OP_MASK_SAE,
X86ISD::CVTTP2IBS, X86ISD::CVTTP2IBS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttph2iubs128, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2IUBS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttph2iubs256, INTR_TYPE_1OP_MASK_SAE,
- X86ISD::CVTTP2IUBS, X86ISD::CVTTP2IUBS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttph2iubs256, INTR_TYPE_1OP_MASK,
+ X86ISD::CVTTP2IUBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttph2iubs512, INTR_TYPE_1OP_MASK_SAE,
X86ISD::CVTTP2IUBS, X86ISD::CVTTP2IUBS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2dqs_128, INTR_TYPE_1OP_MASK,
@@ -566,13 +566,13 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(avx10_mask_vcvttps2ibs128, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2IBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2ibs256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTTP2IBS, X86ISD::CVTTP2IBS_SAE),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2ibs512, INTR_TYPE_1OP_MASK_SAE,
+ X86ISD::CVTTP2IBS, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2ibs512, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2IBS, X86ISD::CVTTP2IBS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2iubs128, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2IUBS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2iubs256, INTR_TYPE_1OP_MASK_SAE,
- X86ISD::CVTTP2IUBS, X86ISD::CVTTP2IUBS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2iubs256, INTR_TYPE_1OP_MASK,
+ X86ISD::CVTTP2IUBS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2iubs512, INTR_TYPE_1OP_MASK_SAE,
X86ISD::CVTTP2IUBS, X86ISD::CVTTP2IUBS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2qqs_128, INTR_TYPE_1OP_MASK,
diff --git a/llvm/test/CodeGen/X86/avx10_2satcvt-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2satcvt-intrinsics.ll
index bbde50574a8e1..957523f87b7c3 100644
--- a/llvm/test/CodeGen/X86/avx10_2satcvt-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx10_2satcvt-intrinsics.ll
@@ -274,7 +274,7 @@ define dso_local <4 x i64> @test_mm256_ipcvtph_epi8(<16 x half> noundef %__A) lo
; CHECK-NEXT: vcvtph2ibs %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7c,0x28,0x69,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2ibs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1, i32 4)
+ %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2ibs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1)
%1 = bitcast <16 x i16> %0 to <4 x i64>
ret <4 x i64> %1
}
@@ -293,7 +293,7 @@ define dso_local <4 x i64> @test_mm256_mask_ipcvtph_epi8(<4 x i64> noundef %__S,
; X86-NEXT: retl # encoding: [0xc3]
entry:
%0 = bitcast <4 x i64> %__S to <16 x i16>
- %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2ibs256(<16 x half> %__B, <16 x i16> %0, i16 %__A, i32 4)
+ %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2ibs256(<16 x half> %__B, <16 x i16> %0, i16 %__A)
%2 = bitcast <16 x i16> %1 to <4 x i64>
ret <4 x i64> %2
}
@@ -311,60 +311,12 @@ define dso_local <4 x i64> @test_mm256_maskz_ipcvtph_epi8(i16 noundef zeroext %_
; X86-NEXT: vcvtph2ibs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x69,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2ibs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A, i32 4)
+ %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2ibs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A)
%1 = bitcast <16 x i16> %0 to <4 x i64>
ret <4 x i64> %1
}
-define dso_local <4 x i64> @test_mm256_ipcvtph_epi8_round(<16 x half> noundef %__A) {
-; CHECK-LABEL: test_mm256_ipcvtph_epi8_round:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vcvtph2ibs {rz-sae}, %ymm0, %ymm0 # encoding: [0x62,0xf5,0x78,0x78,0x69,0xc0]
-; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2ibs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1, i32 11)
- %1 = bitcast <16 x i16> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_mask_ipcvtph_epi8_round(<4 x i64> noundef %__S, i16 noundef zeroext %__A, <16 x half> noundef %__B) {
-; X64-LABEL: test_mm256_mask_ipcvtph_epi8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvtph2ibs {rz-sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x78,0x79,0x69,0xc1]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_mask_ipcvtph_epi8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvtph2ibs {rz-sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x78,0x79,0x69,0xc1]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = bitcast <4 x i64> %__S to <16 x i16>
- %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2ibs256(<16 x half> %__B, <16 x i16> %0, i16 %__A, i32 11)
- %2 = bitcast <16 x i16> %1 to <4 x i64>
- ret <4 x i64> %2
-}
-
-define dso_local <4 x i64> @test_mm256_maskz_ipcvtph_epi8_round(i16 noundef zeroext %__A, <16 x half> noundef %__B) {
-; X64-LABEL: test_mm256_maskz_ipcvtph_epi8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvtph2ibs {rz-sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x78,0xf9,0x69,0xc0]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_maskz_ipcvtph_epi8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvtph2ibs {rz-sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x78,0xf9,0x69,0xc0]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2ibs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A, i32 11)
- %1 = bitcast <16 x i16> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-declare <16 x i16> @llvm.x86.avx10.mask.vcvtph2ibs256(<16 x half>, <16 x i16>, i16, i32)
+declare <16 x i16> @llvm.x86.avx10.mask.vcvtph2ibs256(<16 x half>, <16 x i16>, i16)
define dso_local <2 x i64> @test_mm_ipcvtph_epu8(<8 x half> noundef %__A) {
; CHECK-LABEL: test_mm_ipcvtph_epu8:
@@ -422,7 +374,7 @@ define dso_local <4 x i64> @test_mm256_ipcvtph_epu8(<16 x half> noundef %__A) lo
; CHECK-NEXT: vcvtph2iubs %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7c,0x28,0x6b,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2iubs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1, i32 4)
+ %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2iubs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1)
%1 = bitcast <16 x i16> %0 to <4 x i64>
ret <4 x i64> %1
}
@@ -441,7 +393,7 @@ define dso_local <4 x i64> @test_mm256_mask_ipcvtph_epu8(<4 x i64> noundef %__S,
; X86-NEXT: retl # encoding: [0xc3]
entry:
%0 = bitcast <4 x i64> %__S to <16 x i16>
- %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2iubs256(<16 x half> %__B, <16 x i16> %0, i16 %__A, i32 4)
+ %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2iubs256(<16 x half> %__B, <16 x i16> %0, i16 %__A)
%2 = bitcast <16 x i16> %1 to <4 x i64>
ret <4 x i64> %2
}
@@ -459,60 +411,12 @@ define dso_local <4 x i64> @test_mm256_maskz_ipcvtph_epu8(i16 noundef zeroext %_
; X86-NEXT: vcvtph2iubs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x6b,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2iubs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A, i32 4)
- %1 = bitcast <16 x i16> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_ipcvtph_epu8_round(<16 x half> noundef %__A) {
-; CHECK-LABEL: test_mm256_ipcvtph_epu8_round:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vcvtph2iubs {rz-sae}, %ymm0, %ymm0 # encoding: [0x62,0xf5,0x78,0x78,0x6b,0xc0]
-; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2iubs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1, i32 11)
- %1 = bitcast <16 x i16> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_mask_ipcvtph_epu8_round(<4 x i64> noundef %__S, i16 noundef zeroext %__A, <16 x half> noundef %__B) {
-; X64-LABEL: test_mm256_mask_ipcvtph_epu8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvtph2iubs {rz-sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x78,0x79,0x6b,0xc1]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_mask_ipcvtph_epu8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvtph2iubs {rz-sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x78,0x79,0x6b,0xc1]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = bitcast <4 x i64> %__S to <16 x i16>
- %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2iubs256(<16 x half> %__B, <16 x i16> %0, i16 %__A, i32 11)
- %2 = bitcast <16 x i16> %1 to <4 x i64>
- ret <4 x i64> %2
-}
-
-define dso_local <4 x i64> @test_mm256_maskz_ipcvtph_epu8_round(i16 noundef zeroext %__A, <16 x half> noundef %__B) {
-; X64-LABEL: test_mm256_maskz_ipcvtph_epu8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvtph2iubs {rz-sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x78,0xf9,0x6b,0xc0]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_maskz_ipcvtph_epu8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvtph2iubs {rz-sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x78,0xf9,0x6b,0xc0]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2iubs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A, i32 11)
+ %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvtph2iubs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A)
%1 = bitcast <16 x i16> %0 to <4 x i64>
ret <4 x i64> %1
}
-declare <16 x i16> @llvm.x86.avx10.mask.vcvtph2iubs256(<16 x half>, <16 x i16>, i16, i32)
+declare <16 x i16> @llvm.x86.avx10.mask.vcvtph2iubs256(<16 x half>, <16 x i16>, i16)
define dso_local <2 x i64> @test_mm_ipcvtps_epi8(<4 x float> noundef %__A) {
; CHECK-LABEL: test_mm_ipcvtps_epi8:
@@ -570,7 +474,7 @@ define dso_local <4 x i64> @test_mm256_ipcvtps_epi8(<8 x float> noundef %__A) lo
; CHECK-NEXT: vcvtps2ibs %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7d,0x28,0x69,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2ibs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1, i32 4)
+ %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2ibs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1)
%1 = bitcast <8 x i32> %0 to <4 x i64>
ret <4 x i64> %1
}
@@ -589,7 +493,7 @@ define dso_local <4 x i64> @test_mm256_mask_ipcvtps_epi8(<4 x i64> noundef %__S,
; X86-NEXT: retl # encoding: [0xc3]
entry:
%0 = bitcast <4 x i64> %__S to <8 x i32>
- %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2ibs256(<8 x float> %__B, <8 x i32> %0, i8 %__A, i32 4)
+ %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2ibs256(<8 x float> %__B, <8 x i32> %0, i8 %__A)
%2 = bitcast <8 x i32> %1 to <4 x i64>
ret <4 x i64> %2
}
@@ -607,60 +511,12 @@ define dso_local <4 x i64> @test_mm256_maskz_ipcvtps_epi8(i8 noundef zeroext %__
; X86-NEXT: vcvtps2ibs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x69,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2ibs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A, i32 4)
+ %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2ibs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A)
%1 = bitcast <8 x i32> %0 to <4 x i64>
ret <4 x i64> %1
}
-define dso_local <4 x i64> @test_mm256_ipcvtps_epi8_round(<8 x float> noundef %__A) {
-; CHECK-LABEL: test_mm256_ipcvtps_epi8_round:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vcvtps2ibs {rz-sae}, %ymm0, %ymm0 # encoding: [0x62,0xf5,0x79,0x78,0x69,0xc0]
-; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2ibs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1, i32 11)
- %1 = bitcast <8 x i32> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_mask_ipcvtps_epi8_round(<4 x i64> noundef %__S, i8 noundef zeroext %__A, <8 x float> noundef %__B) {
-; X64-LABEL: test_mm256_mask_ipcvtps_epi8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvtps2ibs {rz-sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x79,0x79,0x69,0xc1]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_mask_ipcvtps_epi8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvtps2ibs {rz-sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x79,0x79,0x69,0xc1]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = bitcast <4 x i64> %__S to <8 x i32>
- %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2ibs256(<8 x float> %__B, <8 x i32> %0, i8 %__A, i32 11)
- %2 = bitcast <8 x i32> %1 to <4 x i64>
- ret <4 x i64> %2
-}
-
-define dso_local <4 x i64> @test_mm256_maskz_ipcvtps_epi8_round(i8 noundef zeroext %__A, <8 x float> noundef %__B) {
-; X64-LABEL: test_mm256_maskz_ipcvtps_epi8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvtps2ibs {rz-sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x79,0xf9,0x69,0xc0]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_maskz_ipcvtps_epi8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvtps2ibs {rz-sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x79,0xf9,0x69,0xc0]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2ibs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A, i32 11)
- %1 = bitcast <8 x i32> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-declare <8 x i32> @llvm.x86.avx10.mask.vcvtps2ibs256(<8 x float>, <8 x i32>, i8, i32)
+declare <8 x i32> @llvm.x86.avx10.mask.vcvtps2ibs256(<8 x float>, <8 x i32>, i8)
define dso_local <2 x i64> @test_mm_ipcvtps_epu8(<4 x float> noundef %__A) {
; CHECK-LABEL: test_mm_ipcvtps_epu8:
@@ -718,7 +574,7 @@ define dso_local <4 x i64> @test_mm256_ipcvtps_epu8(<8 x float> noundef %__A) lo
; CHECK-NEXT: vcvtps2iubs %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7d,0x28,0x6b,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2iubs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1, i32 4)
+ %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2iubs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1)
%1 = bitcast <8 x i32> %0 to <4 x i64>
ret <4 x i64> %1
}
@@ -737,7 +593,7 @@ define dso_local <4 x i64> @test_mm256_mask_ipcvtps_epu8(<4 x i64> noundef %__S,
; X86-NEXT: retl # encoding: [0xc3]
entry:
%0 = bitcast <4 x i64> %__S to <8 x i32>
- %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2iubs256(<8 x float> %__B, <8 x i32> %0, i8 %__A, i32 4)
+ %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2iubs256(<8 x float> %__B, <8 x i32> %0, i8 %__A)
%2 = bitcast <8 x i32> %1 to <4 x i64>
ret <4 x i64> %2
}
@@ -755,60 +611,12 @@ define dso_local <4 x i64> @test_mm256_maskz_ipcvtps_epu8(i8 noundef zeroext %__
; X86-NEXT: vcvtps2iubs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x6b,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2iubs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A, i32 4)
- %1 = bitcast <8 x i32> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_ipcvtps_epu8_round(<8 x float> noundef %__A) {
-; CHECK-LABEL: test_mm256_ipcvtps_epu8_round:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vcvtps2iubs {rz-sae}, %ymm0, %ymm0 # encoding: [0x62,0xf5,0x79,0x78,0x6b,0xc0]
-; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2iubs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1, i32 11)
- %1 = bitcast <8 x i32> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_mask_ipcvtps_epu8_round(<4 x i64> noundef %__S, i8 noundef zeroext %__A, <8 x float> noundef %__B) {
-; X64-LABEL: test_mm256_mask_ipcvtps_epu8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvtps2iubs {rz-sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x79,0x79,0x6b,0xc1]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_mask_ipcvtps_epu8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvtps2iubs {rz-sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x79,0x79,0x6b,0xc1]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = bitcast <4 x i64> %__S to <8 x i32>
- %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2iubs256(<8 x float> %__B, <8 x i32> %0, i8 %__A, i32 11)
- %2 = bitcast <8 x i32> %1 to <4 x i64>
- ret <4 x i64> %2
-}
-
-define dso_local <4 x i64> @test_mm256_maskz_ipcvtps_epu8_round(i8 noundef zeroext %__A, <8 x float> noundef %__B) {
-; X64-LABEL: test_mm256_maskz_ipcvtps_epu8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvtps2iubs {rz-sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x79,0xf9,0x6b,0xc0]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_maskz_ipcvtps_epu8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvtps2iubs {rz-sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x79,0xf9,0x6b,0xc0]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2iubs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A, i32 11)
+ %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvtps2iubs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A)
%1 = bitcast <8 x i32> %0 to <4 x i64>
ret <4 x i64> %1
}
-declare <8 x i32> @llvm.x86.avx10.mask.vcvtps2iubs256(<8 x float>, <8 x i32>, i8, i32)
+declare <8 x i32> @llvm.x86.avx10.mask.vcvtps2iubs256(<8 x float>, <8 x i32>, i8)
define dso_local <2 x i64> @test_mm_ipcvttbf16_epi8(<8 x bfloat> noundef %__A) {
; CHECK-LABEL: test_mm_ipcvttbf16_epi8:
@@ -1082,7 +890,7 @@ define dso_local <4 x i64> @test_mm256_ipcvttph_epi8(<16 x half> noundef %__A) l
; CHECK-NEXT: vcvttph2ibs %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7c,0x28,0x68,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2ibs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1, i32 4)
+ %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2ibs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1)
%1 = bitcast <16 x i16> %0 to <4 x i64>
ret <4 x i64> %1
}
@@ -1101,7 +909,7 @@ define dso_local <4 x i64> @test_mm256_mask_ipcvttph_epi8(<4 x i64> noundef %__S
; X86-NEXT: retl # encoding: [0xc3]
entry:
%0 = bitcast <4 x i64> %__S to <16 x i16>
- %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2ibs256(<16 x half> %__B, <16 x i16> %0, i16 %__A, i32 4)
+ %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2ibs256(<16 x half> %__B, <16 x i16> %0, i16 %__A)
%2 = bitcast <16 x i16> %1 to <4 x i64>
ret <4 x i64> %2
}
@@ -1119,59 +927,11 @@ define dso_local <4 x i64> @test_mm256_maskz_ipcvttph_epi8(i16 noundef zeroext %
; X86-NEXT: vcvttph2ibs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x68,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2ibs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A, i32 4)
+ %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2ibs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A)
%1 = bitcast <16 x i16> %0 to <4 x i64>
ret <4 x i64> %1
}
-
-define dso_local <4 x i64> @test_mm256_ipcvttph_epi8_round(<16 x half> noundef %__A) {
-; CHECK-LABEL: test_mm256_ipcvttph_epi8_round:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vcvttph2ibs {sae}, %ymm0, %ymm0 # encoding: [0x62,0xf5,0x78,0x18,0x68,0xc0]
-; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2ibs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1, i32 8)
- %1 = bitcast <16 x i16> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_mask_ipcvttph_epi8_round(<4 x i64> noundef %__S, i16 noundef zeroext %__A, <16 x half> noundef %__B) {
-; X64-LABEL: test_mm256_mask_ipcvttph_epi8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvttph2ibs {sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x78,0x19,0x68,0xc1]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_mask_ipcvttph_epi8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvttph2ibs {sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x78,0x19,0x68,0xc1]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = bitcast <4 x i64> %__S to <16 x i16>
- %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2ibs256(<16 x half> %__B, <16 x i16> %0, i16 %__A, i32 8)
- %2 = bitcast <16 x i16> %1 to <4 x i64>
- ret <4 x i64> %2
-}
-
-define dso_local <4 x i64> @test_mm256_maskz_ipcvttph_epi8_round(i16 noundef zeroext %__A, <16 x half> noundef %__B) {
-; X64-LABEL: test_mm256_maskz_ipcvttph_epi8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvttph2ibs {sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x78,0x99,0x68,0xc0]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_maskz_ipcvttph_epi8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvttph2ibs {sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x78,0x99,0x68,0xc0]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2ibs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A, i32 8)
- %1 = bitcast <16 x i16> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-declare <16 x i16> @llvm.x86.avx10.mask.vcvttph2ibs256(<16 x half>, <16 x i16>, i16, i32)
+declare <16 x i16> @llvm.x86.avx10.mask.vcvttph2ibs256(<16 x half>, <16 x i16>, i16)
define dso_local <2 x i64> @test_mm_ipcvttph_epu8(<8 x half> noundef %__A) {
; CHECK-LABEL: test_mm_ipcvttph_epu8:
@@ -1229,7 +989,7 @@ define dso_local <4 x i64> @test_mm256_ipcvttph_epu8(<16 x half> noundef %__A) l
; CHECK-NEXT: vcvttph2iubs %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7c,0x28,0x6a,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2iubs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1, i32 4)
+ %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2iubs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1)
%1 = bitcast <16 x i16> %0 to <4 x i64>
ret <4 x i64> %1
}
@@ -1248,7 +1008,7 @@ define dso_local <4 x i64> @test_mm256_mask_ipcvttph_epu8(<4 x i64> noundef %__S
; X86-NEXT: retl # encoding: [0xc3]
entry:
%0 = bitcast <4 x i64> %__S to <16 x i16>
- %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2iubs256(<16 x half> %__B, <16 x i16> %0, i16 %__A, i32 4)
+ %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2iubs256(<16 x half> %__B, <16 x i16> %0, i16 %__A)
%2 = bitcast <16 x i16> %1 to <4 x i64>
ret <4 x i64> %2
}
@@ -1266,60 +1026,12 @@ define dso_local <4 x i64> @test_mm256_maskz_ipcvttph_epu8(i16 noundef zeroext %
; X86-NEXT: vcvttph2iubs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x6a,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2iubs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A, i32 4)
- %1 = bitcast <16 x i16> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_ipcvttph_epu8_round(<16 x half> noundef %__A) {
-; CHECK-LABEL: test_mm256_ipcvttph_epu8_round:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vcvttph2iubs {sae}, %ymm0, %ymm0 # encoding: [0x62,0xf5,0x78,0x18,0x6a,0xc0]
-; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2iubs256(<16 x half> %__A, <16 x i16> zeroinitializer, i16 -1, i32 8)
- %1 = bitcast <16 x i16> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_mask_ipcvttph_epu8_round(<4 x i64> noundef %__S, i16 noundef zeroext %__A, <16 x half> noundef %__B) {
-; X64-LABEL: test_mm256_mask_ipcvttph_epu8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvttph2iubs {sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x78,0x19,0x6a,0xc1]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_mask_ipcvttph_epu8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvttph2iubs {sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x78,0x19,0x6a,0xc1]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = bitcast <4 x i64> %__S to <16 x i16>
- %1 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2iubs256(<16 x half> %__B, <16 x i16> %0, i16 %__A, i32 8)
- %2 = bitcast <16 x i16> %1 to <4 x i64>
- ret <4 x i64> %2
-}
-
-define dso_local <4 x i64> @test_mm256_maskz_ipcvttph_epu8_round(i16 noundef zeroext %__A, <16 x half> noundef %__B) {
-; X64-LABEL: test_mm256_maskz_ipcvttph_epu8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvttph2iubs {sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x78,0x99,0x6a,0xc0]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_maskz_ipcvttph_epu8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvttph2iubs {sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x78,0x99,0x6a,0xc0]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2iubs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A, i32 8)
+ %0 = tail call <16 x i16> @llvm.x86.avx10.mask.vcvttph2iubs256(<16 x half> %__B, <16 x i16> zeroinitializer, i16 %__A)
%1 = bitcast <16 x i16> %0 to <4 x i64>
ret <4 x i64> %1
}
-declare <16 x i16> @llvm.x86.avx10.mask.vcvttph2iubs256(<16 x half>, <16 x i16>, i16, i32)
+declare <16 x i16> @llvm.x86.avx10.mask.vcvttph2iubs256(<16 x half>, <16 x i16>, i16)
define dso_local <2 x i64> @test_mm_ipcvttps_epi8(<4 x float> noundef %__A) {
; CHECK-LABEL: test_mm_ipcvttps_epi8:
@@ -1377,7 +1089,7 @@ define dso_local <4 x i64> @test_mm256_ipcvttps_epi8(<8 x float> noundef %__A) l
; CHECK-NEXT: vcvttps2ibs %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7d,0x28,0x68,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2ibs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1, i32 4)
+ %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2ibs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1)
%1 = bitcast <8 x i32> %0 to <4 x i64>
ret <4 x i64> %1
}
@@ -1396,7 +1108,7 @@ define dso_local <4 x i64> @test_mm256_mask_ipcvttps_epi8(<4 x i64> noundef %__S
; X86-NEXT: retl # encoding: [0xc3]
entry:
%0 = bitcast <4 x i64> %__S to <8 x i32>
- %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2ibs256(<8 x float> %__B, <8 x i32> %0, i8 %__A, i32 4)
+ %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2ibs256(<8 x float> %__B, <8 x i32> %0, i8 %__A)
%2 = bitcast <8 x i32> %1 to <4 x i64>
ret <4 x i64> %2
}
@@ -1414,60 +1126,12 @@ define dso_local <4 x i64> @test_mm256_maskz_ipcvttps_epi8(i8 noundef zeroext %_
; X86-NEXT: vcvttps2ibs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x68,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2ibs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A, i32 4)
+ %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2ibs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A)
%1 = bitcast <8 x i32> %0 to <4 x i64>
ret <4 x i64> %1
}
-define dso_local <4 x i64> @test_mm256_ipcvttps_epi8_round(<8 x float> noundef %__A) {
-; CHECK-LABEL: test_mm256_ipcvttps_epi8_round:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vcvttps2ibs {sae}, %ymm0, %ymm0 # encoding: [0x62,0xf5,0x79,0x18,0x68,0xc0]
-; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2ibs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1, i32 8)
- %1 = bitcast <8 x i32> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_mask_ipcvttps_epi8_round(<4 x i64> noundef %__S, i8 noundef zeroext %__A, <8 x float> noundef %__B) {
-; X64-LABEL: test_mm256_mask_ipcvttps_epi8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvttps2ibs {sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x79,0x19,0x68,0xc1]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_mask_ipcvttps_epi8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvttps2ibs {sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x79,0x19,0x68,0xc1]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = bitcast <4 x i64> %__S to <8 x i32>
- %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2ibs256(<8 x float> %__B, <8 x i32> %0, i8 %__A, i32 8)
- %2 = bitcast <8 x i32> %1 to <4 x i64>
- ret <4 x i64> %2
-}
-
-define dso_local <4 x i64> @test_mm256_maskz_ipcvttps_epi8_round(i8 noundef zeroext %__A, <8 x float> noundef %__B) {
-; X64-LABEL: test_mm256_maskz_ipcvttps_epi8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvttps2ibs {sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x79,0x99,0x68,0xc0]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_maskz_ipcvttps_epi8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvttps2ibs {sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x79,0x99,0x68,0xc0]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2ibs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A, i32 8)
- %1 = bitcast <8 x i32> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-declare <8 x i32> @llvm.x86.avx10.mask.vcvttps2ibs256(<8 x float>, <8 x i32>, i8, i32)
+declare <8 x i32> @llvm.x86.avx10.mask.vcvttps2ibs256(<8 x float>, <8 x i32>, i8)
define dso_local <2 x i64> @test_mm_ipcvttps_epu8(<4 x float> noundef %__A) {
; CHECK-LABEL: test_mm_ipcvttps_epu8:
@@ -1525,7 +1189,7 @@ define dso_local <4 x i64> @test_mm256_ipcvttps_epu8(<8 x float> noundef %__A) l
; CHECK-NEXT: vcvttps2iubs %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7d,0x28,0x6a,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2iubs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1, i32 4)
+ %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2iubs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1)
%1 = bitcast <8 x i32> %0 to <4 x i64>
ret <4 x i64> %1
}
@@ -1544,7 +1208,7 @@ define dso_local <4 x i64> @test_mm256_mask_ipcvttps_epu8(<4 x i64> noundef %__S
; X86-NEXT: retl # encoding: [0xc3]
entry:
%0 = bitcast <4 x i64> %__S to <8 x i32>
- %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2iubs256(<8 x float> %__B, <8 x i32> %0, i8 %__A, i32 4)
+ %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2iubs256(<8 x float> %__B, <8 x i32> %0, i8 %__A)
%2 = bitcast <8 x i32> %1 to <4 x i64>
ret <4 x i64> %2
}
@@ -1562,57 +1226,9 @@ define dso_local <4 x i64> @test_mm256_maskz_ipcvttps_epu8(i8 noundef zeroext %_
; X86-NEXT: vcvttps2iubs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x6a,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2iubs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A, i32 4)
- %1 = bitcast <8 x i32> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_ipcvttps_epu8_round(<8 x float> noundef %__A) {
-; CHECK-LABEL: test_mm256_ipcvttps_epu8_round:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vcvttps2iubs {sae}, %ymm0, %ymm0 # encoding: [0x62,0xf5,0x79,0x18,0x6a,0xc0]
-; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
-entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2iubs256(<8 x float> %__A, <8 x i32> zeroinitializer, i8 -1, i32 8)
- %1 = bitcast <8 x i32> %0 to <4 x i64>
- ret <4 x i64> %1
-}
-
-define dso_local <4 x i64> @test_mm256_mask_ipcvttps_epu8_round(<4 x i64> noundef %__S, i8 noundef zeroext %__A, <8 x float> noundef %__B) {
-; X64-LABEL: test_mm256_mask_ipcvttps_epu8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvttps2iubs {sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x79,0x19,0x6a,0xc1]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_mask_ipcvttps_epu8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvttps2iubs {sae}, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf5,0x79,0x19,0x6a,0xc1]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = bitcast <4 x i64> %__S to <8 x i32>
- %1 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2iubs256(<8 x float> %__B, <8 x i32> %0, i8 %__A, i32 8)
- %2 = bitcast <8 x i32> %1 to <4 x i64>
- ret <4 x i64> %2
-}
-
-define dso_local <4 x i64> @test_mm256_maskz_ipcvttps_epu8_round(i8 noundef zeroext %__A, <8 x float> noundef %__B) {
-; X64-LABEL: test_mm256_maskz_ipcvttps_epu8_round:
-; X64: # %bb.0: # %entry
-; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
-; X64-NEXT: vcvttps2iubs {sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x79,0x99,0x6a,0xc0]
-; X64-NEXT: retq # encoding: [0xc3]
-;
-; X86-LABEL: test_mm256_maskz_ipcvttps_epu8_round:
-; X86: # %bb.0: # %entry
-; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
-; X86-NEXT: vcvttps2iubs {sae}, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x79,0x99,0x6a,0xc0]
-; X86-NEXT: retl # encoding: [0xc3]
-entry:
- %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2iubs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A, i32 8)
+ %0 = tail call <8 x i32> @llvm.x86.avx10.mask.vcvttps2iubs256(<8 x float> %__B, <8 x i32> zeroinitializer, i8 %__A)
%1 = bitcast <8 x i32> %0 to <4 x i64>
ret <4 x i64> %1
}
-declare <8 x i32> @llvm.x86.avx10.mask.vcvttps2iubs256(<8 x float>, <8 x i32>, i8, i32)
+declare <8 x i32> @llvm.x86.avx10.mask.vcvttps2iubs256(<8 x float>, <8 x i32>, i8)
diff --git a/llvm/test/MC/Disassembler/X86/avx10.2-satcvt-32.txt b/llvm/test/MC/Disassembler/X86/avx10.2-satcvt-32.txt
index 9e8477aa7f387..b690b012bee4d 100644
--- a/llvm/test/MC/Disassembler/X86/avx10.2-satcvt-32.txt
+++ b/llvm/test/MC/Disassembler/X86/avx10.2-satcvt-32.txt
@@ -249,18 +249,10 @@
# INTEL: vcvtph2ibs ymm2, ymm3
0x62,0xf5,0x7c,0x28,0x69,0xd3
-# ATT: vcvtph2ibs {rn-sae}, %ymm3, %ymm2
-# INTEL: vcvtph2ibs ymm2, ymm3, {rn-sae}
-0x62,0xf5,0x78,0x18,0x69,0xd3
-
# ATT: vcvtph2ibs %ymm3, %ymm2 {%k7}
# INTEL: vcvtph2ibs ymm2 {k7}, ymm3
0x62,0xf5,0x7c,0x2f,0x69,0xd3
-# ATT: vcvtph2ibs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvtph2ibs ymm2 {k7} {z}, ymm3, {rz-sae}
-0x62,0xf5,0x78,0xff,0x69,0xd3
-
# ATT: vcvtph2ibs 268435456(%esp,%esi,8), %xmm2
# INTEL: vcvtph2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
0x62,0xf5,0x7c,0x08,0x69,0x94,0xf4,0x00,0x00,0x00,0x10
@@ -365,18 +357,10 @@
# INTEL: vcvtph2iubs ymm2, ymm3
0x62,0xf5,0x7c,0x28,0x6b,0xd3
-# ATT: vcvtph2iubs {rn-sae}, %ymm3, %ymm2
-# INTEL: vcvtph2iubs ymm2, ymm3, {rn-sae}
-0x62,0xf5,0x78,0x18,0x6b,0xd3
-
# ATT: vcvtph2iubs %ymm3, %ymm2 {%k7}
# INTEL: vcvtph2iubs ymm2 {k7}, ymm3
0x62,0xf5,0x7c,0x2f,0x6b,0xd3
-# ATT: vcvtph2iubs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvtph2iubs ymm2 {k7} {z}, ymm3, {rz-sae}
-0x62,0xf5,0x78,0xff,0x6b,0xd3
-
# ATT: vcvtph2iubs 268435456(%esp,%esi,8), %xmm2
# INTEL: vcvtph2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
0x62,0xf5,0x7c,0x08,0x6b,0x94,0xf4,0x00,0x00,0x00,0x10
@@ -481,18 +465,10 @@
# INTEL: vcvtps2ibs ymm2, ymm3
0x62,0xf5,0x7d,0x28,0x69,0xd3
-# ATT: vcvtps2ibs {rn-sae}, %ymm3, %ymm2
-# INTEL: vcvtps2ibs ymm2, ymm3, {rn-sae}
-0x62,0xf5,0x79,0x18,0x69,0xd3
-
# ATT: vcvtps2ibs %ymm3, %ymm2 {%k7}
# INTEL: vcvtps2ibs ymm2 {k7}, ymm3
0x62,0xf5,0x7d,0x2f,0x69,0xd3
-# ATT: vcvtps2ibs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvtps2ibs ymm2 {k7} {z}, ymm3, {rz-sae}
-0x62,0xf5,0x79,0xff,0x69,0xd3
-
# ATT: vcvtps2ibs 268435456(%esp,%esi,8), %xmm2
# INTEL: vcvtps2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
0x62,0xf5,0x7d,0x08,0x69,0x94,0xf4,0x00,0x00,0x00,0x10
@@ -597,18 +573,10 @@
# INTEL: vcvtps2iubs ymm2, ymm3
0x62,0xf5,0x7d,0x28,0x6b,0xd3
-# ATT: vcvtps2iubs {rn-sae}, %ymm3, %ymm2
-# INTEL: vcvtps2iubs ymm2, ymm3, {rn-sae}
-0x62,0xf5,0x79,0x18,0x6b,0xd3
-
# ATT: vcvtps2iubs %ymm3, %ymm2 {%k7}
# INTEL: vcvtps2iubs ymm2 {k7}, ymm3
0x62,0xf5,0x7d,0x2f,0x6b,0xd3
-# ATT: vcvtps2iubs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvtps2iubs ymm2 {k7} {z}, ymm3, {rz-sae}
-0x62,0xf5,0x79,0xff,0x6b,0xd3
-
# ATT: vcvtps2iubs 268435456(%esp,%esi,8), %xmm2
# INTEL: vcvtps2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
0x62,0xf5,0x7d,0x08,0x6b,0x94,0xf4,0x00,0x00,0x00,0x10
@@ -929,18 +897,10 @@
# INTEL: vcvttph2ibs ymm2, ymm3
0x62,0xf5,0x7c,0x28,0x68,0xd3
-# ATT: vcvttph2ibs {sae}, %ymm3, %ymm2
-# INTEL: vcvttph2ibs ymm2, ymm3, {sae}
-0x62,0xf5,0x78,0x18,0x68,0xd3
-
# ATT: vcvttph2ibs %ymm3, %ymm2 {%k7}
# INTEL: vcvttph2ibs ymm2 {k7}, ymm3
0x62,0xf5,0x7c,0x2f,0x68,0xd3
-# ATT: vcvttph2ibs {sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvttph2ibs ymm2 {k7} {z}, ymm3, {sae}
-0x62,0xf5,0x78,0x9f,0x68,0xd3
-
# ATT: vcvttph2ibs 268435456(%esp,%esi,8), %xmm2
# INTEL: vcvttph2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
0x62,0xf5,0x7c,0x08,0x68,0x94,0xf4,0x00,0x00,0x00,0x10
@@ -1045,18 +1005,10 @@
# INTEL: vcvttph2iubs ymm2, ymm3
0x62,0xf5,0x7c,0x28,0x6a,0xd3
-# ATT: vcvttph2iubs {sae}, %ymm3, %ymm2
-# INTEL: vcvttph2iubs ymm2, ymm3, {sae}
-0x62,0xf5,0x78,0x18,0x6a,0xd3
-
# ATT: vcvttph2iubs %ymm3, %ymm2 {%k7}
# INTEL: vcvttph2iubs ymm2 {k7}, ymm3
0x62,0xf5,0x7c,0x2f,0x6a,0xd3
-# ATT: vcvttph2iubs {sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvttph2iubs ymm2 {k7} {z}, ymm3, {sae}
-0x62,0xf5,0x78,0x9f,0x6a,0xd3
-
# ATT: vcvttph2iubs 268435456(%esp,%esi,8), %xmm2
# INTEL: vcvttph2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
0x62,0xf5,0x7c,0x08,0x6a,0x94,0xf4,0x00,0x00,0x00,0x10
@@ -1161,18 +1113,10 @@
# INTEL: vcvttps2ibs ymm2, ymm3
0x62,0xf5,0x7d,0x28,0x68,0xd3
-# ATT: vcvttps2ibs {sae}, %ymm3, %ymm2
-# INTEL: vcvttps2ibs ymm2, ymm3, {sae}
-0x62,0xf5,0x79,0x18,0x68,0xd3
-
# ATT: vcvttps2ibs %ymm3, %ymm2 {%k7}
# INTEL: vcvttps2ibs ymm2 {k7}, ymm3
0x62,0xf5,0x7d,0x2f,0x68,0xd3
-# ATT: vcvttps2ibs {sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvttps2ibs ymm2 {k7} {z}, ymm3, {sae}
-0x62,0xf5,0x79,0x9f,0x68,0xd3
-
# ATT: vcvttps2ibs 268435456(%esp,%esi,8), %xmm2
# INTEL: vcvttps2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
0x62,0xf5,0x7d,0x08,0x68,0x94,0xf4,0x00,0x00,0x00,0x10
@@ -1277,18 +1221,10 @@
# INTEL: vcvttps2iubs ymm2, ymm3
0x62,0xf5,0x7d,0x28,0x6a,0xd3
-# ATT: vcvttps2iubs {sae}, %ymm3, %ymm2
-# INTEL: vcvttps2iubs ymm2, ymm3, {sae}
-0x62,0xf5,0x79,0x18,0x6a,0xd3
-
# ATT: vcvttps2iubs %ymm3, %ymm2 {%k7}
# INTEL: vcvttps2iubs ymm2 {k7}, ymm3
0x62,0xf5,0x7d,0x2f,0x6a,0xd3
-# ATT: vcvttps2iubs {sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvttps2iubs ymm2 {k7} {z}, ymm3, {sae}
-0x62,0xf5,0x79,0x9f,0x6a,0xd3
-
# ATT: vcvttps2iubs 268435456(%esp,%esi,8), %xmm2
# INTEL: vcvttps2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
0x62,0xf5,0x7d,0x08,0x6a,0x94,0xf4,0x00,0x00,0x00,0x10
diff --git a/llvm/test/MC/Disassembler/X86/avx10.2-satcvt-64.txt b/llvm/test/MC/Disassembler/X86/avx10.2-satcvt-64.txt
index a7b811f9ae3ec..2b1703202a95c 100644
--- a/llvm/test/MC/Disassembler/X86/avx10.2-satcvt-64.txt
+++ b/llvm/test/MC/Disassembler/X86/avx10.2-satcvt-64.txt
@@ -249,18 +249,10 @@
# INTEL: vcvtph2ibs ymm22, ymm23
0x62,0xa5,0x7c,0x28,0x69,0xf7
-# ATT: vcvtph2ibs {rn-sae}, %ymm23, %ymm22
-# INTEL: vcvtph2ibs ymm22, ymm23, {rn-sae}
-0x62,0xa5,0x78,0x18,0x69,0xf7
-
# ATT: vcvtph2ibs %ymm23, %ymm22 {%k7}
# INTEL: vcvtph2ibs ymm22 {k7}, ymm23
0x62,0xa5,0x7c,0x2f,0x69,0xf7
-# ATT: vcvtph2ibs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvtph2ibs ymm22 {k7} {z}, ymm23, {rz-sae}
-0x62,0xa5,0x78,0xff,0x69,0xf7
-
# ATT: vcvtph2ibs 268435456(%rbp,%r14,8), %xmm22
# INTEL: vcvtph2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa5,0x7c,0x08,0x69,0xb4,0xf5,0x00,0x00,0x00,0x10
@@ -365,18 +357,10 @@
# INTEL: vcvtph2iubs ymm22, ymm23
0x62,0xa5,0x7c,0x28,0x6b,0xf7
-# ATT: vcvtph2iubs {rn-sae}, %ymm23, %ymm22
-# INTEL: vcvtph2iubs ymm22, ymm23, {rn-sae}
-0x62,0xa5,0x78,0x18,0x6b,0xf7
-
# ATT: vcvtph2iubs %ymm23, %ymm22 {%k7}
# INTEL: vcvtph2iubs ymm22 {k7}, ymm23
0x62,0xa5,0x7c,0x2f,0x6b,0xf7
-# ATT: vcvtph2iubs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvtph2iubs ymm22 {k7} {z}, ymm23, {rz-sae}
-0x62,0xa5,0x78,0xff,0x6b,0xf7
-
# ATT: vcvtph2iubs 268435456(%rbp,%r14,8), %xmm22
# INTEL: vcvtph2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa5,0x7c,0x08,0x6b,0xb4,0xf5,0x00,0x00,0x00,0x10
@@ -481,18 +465,10 @@
# INTEL: vcvtps2ibs ymm22, ymm23
0x62,0xa5,0x7d,0x28,0x69,0xf7
-# ATT: vcvtps2ibs {rn-sae}, %ymm23, %ymm22
-# INTEL: vcvtps2ibs ymm22, ymm23, {rn-sae}
-0x62,0xa5,0x79,0x18,0x69,0xf7
-
# ATT: vcvtps2ibs %ymm23, %ymm22 {%k7}
# INTEL: vcvtps2ibs ymm22 {k7}, ymm23
0x62,0xa5,0x7d,0x2f,0x69,0xf7
-# ATT: vcvtps2ibs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvtps2ibs ymm22 {k7} {z}, ymm23, {rz-sae}
-0x62,0xa5,0x79,0xff,0x69,0xf7
-
# ATT: vcvtps2ibs 268435456(%rbp,%r14,8), %xmm22
# INTEL: vcvtps2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa5,0x7d,0x08,0x69,0xb4,0xf5,0x00,0x00,0x00,0x10
@@ -597,18 +573,10 @@
# INTEL: vcvtps2iubs ymm22, ymm23
0x62,0xa5,0x7d,0x28,0x6b,0xf7
-# ATT: vcvtps2iubs {rn-sae}, %ymm23, %ymm22
-# INTEL: vcvtps2iubs ymm22, ymm23, {rn-sae}
-0x62,0xa5,0x79,0x18,0x6b,0xf7
-
# ATT: vcvtps2iubs %ymm23, %ymm22 {%k7}
# INTEL: vcvtps2iubs ymm22 {k7}, ymm23
0x62,0xa5,0x7d,0x2f,0x6b,0xf7
-# ATT: vcvtps2iubs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvtps2iubs ymm22 {k7} {z}, ymm23, {rz-sae}
-0x62,0xa5,0x79,0xff,0x6b,0xf7
-
# ATT: vcvtps2iubs 268435456(%rbp,%r14,8), %xmm22
# INTEL: vcvtps2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa5,0x7d,0x08,0x6b,0xb4,0xf5,0x00,0x00,0x00,0x10
@@ -929,18 +897,10 @@
# INTEL: vcvttph2ibs ymm22, ymm23
0x62,0xa5,0x7c,0x28,0x68,0xf7
-# ATT: vcvttph2ibs {sae}, %ymm23, %ymm22
-# INTEL: vcvttph2ibs ymm22, ymm23, {sae}
-0x62,0xa5,0x78,0x18,0x68,0xf7
-
# ATT: vcvttph2ibs %ymm23, %ymm22 {%k7}
# INTEL: vcvttph2ibs ymm22 {k7}, ymm23
0x62,0xa5,0x7c,0x2f,0x68,0xf7
-# ATT: vcvttph2ibs {sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvttph2ibs ymm22 {k7} {z}, ymm23, {sae}
-0x62,0xa5,0x78,0x9f,0x68,0xf7
-
# ATT: vcvttph2ibs 268435456(%rbp,%r14,8), %xmm22
# INTEL: vcvttph2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa5,0x7c,0x08,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10
@@ -1045,18 +1005,10 @@
# INTEL: vcvttph2iubs ymm22, ymm23
0x62,0xa5,0x7c,0x28,0x6a,0xf7
-# ATT: vcvttph2iubs {sae}, %ymm23, %ymm22
-# INTEL: vcvttph2iubs ymm22, ymm23, {sae}
-0x62,0xa5,0x78,0x18,0x6a,0xf7
-
# ATT: vcvttph2iubs %ymm23, %ymm22 {%k7}
# INTEL: vcvttph2iubs ymm22 {k7}, ymm23
0x62,0xa5,0x7c,0x2f,0x6a,0xf7
-# ATT: vcvttph2iubs {sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvttph2iubs ymm22 {k7} {z}, ymm23, {sae}
-0x62,0xa5,0x78,0x9f,0x6a,0xf7
-
# ATT: vcvttph2iubs 268435456(%rbp,%r14,8), %xmm22
# INTEL: vcvttph2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa5,0x7c,0x08,0x6a,0xb4,0xf5,0x00,0x00,0x00,0x10
@@ -1161,18 +1113,10 @@
# INTEL: vcvttps2ibs ymm22, ymm23
0x62,0xa5,0x7d,0x28,0x68,0xf7
-# ATT: vcvttps2ibs {sae}, %ymm23, %ymm22
-# INTEL: vcvttps2ibs ymm22, ymm23, {sae}
-0x62,0xa5,0x79,0x18,0x68,0xf7
-
# ATT: vcvttps2ibs %ymm23, %ymm22 {%k7}
# INTEL: vcvttps2ibs ymm22 {k7}, ymm23
0x62,0xa5,0x7d,0x2f,0x68,0xf7
-# ATT: vcvttps2ibs {sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvttps2ibs ymm22 {k7} {z}, ymm23, {sae}
-0x62,0xa5,0x79,0x9f,0x68,0xf7
-
# ATT: vcvttps2ibs 268435456(%rbp,%r14,8), %xmm22
# INTEL: vcvttps2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa5,0x7d,0x08,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10
@@ -1277,18 +1221,10 @@
# INTEL: vcvttps2iubs ymm22, ymm23
0x62,0xa5,0x7d,0x28,0x6a,0xf7
-# ATT: vcvttps2iubs {sae}, %ymm23, %ymm22
-# INTEL: vcvttps2iubs ymm22, ymm23, {sae}
-0x62,0xa5,0x79,0x18,0x6a,0xf7
-
# ATT: vcvttps2iubs %ymm23, %ymm22 {%k7}
# INTEL: vcvttps2iubs ymm22 {k7}, ymm23
0x62,0xa5,0x7d,0x2f,0x6a,0xf7
-# ATT: vcvttps2iubs {sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvttps2iubs ymm22 {k7} {z}, ymm23, {sae}
-0x62,0xa5,0x79,0x9f,0x6a,0xf7
-
# ATT: vcvttps2iubs 268435456(%rbp,%r14,8), %xmm22
# INTEL: vcvttps2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa5,0x7d,0x08,0x6a,0xb4,0xf5,0x00,0x00,0x00,0x10
diff --git a/llvm/test/MC/X86/avx10.2satcvt-32-att.s b/llvm/test/MC/X86/avx10.2satcvt-32-att.s
index aa5519c14e59a..992527e885f35 100644
--- a/llvm/test/MC/X86/avx10.2satcvt-32-att.s
+++ b/llvm/test/MC/X86/avx10.2satcvt-32-att.s
@@ -248,18 +248,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x69,0xd3]
vcvtph2ibs %ymm3, %ymm2
-// CHECK: vcvtph2ibs {rn-sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x69,0xd3]
- vcvtph2ibs {rn-sae}, %ymm3, %ymm2
-
// CHECK: vcvtph2ibs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x69,0xd3]
vcvtph2ibs %ymm3, %ymm2 {%k7}
-// CHECK: vcvtph2ibs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0x78,0xff,0x69,0xd3]
- vcvtph2ibs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvtph2ibs 268435456(%esp,%esi,8), %xmm2
// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x69,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvtph2ibs 268435456(%esp,%esi,8), %xmm2
@@ -364,18 +356,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x6b,0xd3]
vcvtph2iubs %ymm3, %ymm2
-// CHECK: vcvtph2iubs {rn-sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x6b,0xd3]
- vcvtph2iubs {rn-sae}, %ymm3, %ymm2
-
// CHECK: vcvtph2iubs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x6b,0xd3]
vcvtph2iubs %ymm3, %ymm2 {%k7}
-// CHECK: vcvtph2iubs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0x78,0xff,0x6b,0xd3]
- vcvtph2iubs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvtph2iubs 268435456(%esp,%esi,8), %xmm2
// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x6b,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvtph2iubs 268435456(%esp,%esi,8), %xmm2
@@ -480,18 +464,10 @@
// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x69,0xd3]
vcvtps2ibs %ymm3, %ymm2
-// CHECK: vcvtps2ibs {rn-sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0x79,0x18,0x69,0xd3]
- vcvtps2ibs {rn-sae}, %ymm3, %ymm2
-
// CHECK: vcvtps2ibs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0x7d,0x2f,0x69,0xd3]
vcvtps2ibs %ymm3, %ymm2 {%k7}
-// CHECK: vcvtps2ibs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0x79,0xff,0x69,0xd3]
- vcvtps2ibs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvtps2ibs 268435456(%esp,%esi,8), %xmm2
// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x69,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvtps2ibs 268435456(%esp,%esi,8), %xmm2
@@ -596,18 +572,10 @@
// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x6b,0xd3]
vcvtps2iubs %ymm3, %ymm2
-// CHECK: vcvtps2iubs {rn-sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0x79,0x18,0x6b,0xd3]
- vcvtps2iubs {rn-sae}, %ymm3, %ymm2
-
// CHECK: vcvtps2iubs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0x7d,0x2f,0x6b,0xd3]
vcvtps2iubs %ymm3, %ymm2 {%k7}
-// CHECK: vcvtps2iubs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0x79,0xff,0x6b,0xd3]
- vcvtps2iubs {rz-sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvtps2iubs 268435456(%esp,%esi,8), %xmm2
// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x6b,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvtps2iubs 268435456(%esp,%esi,8), %xmm2
@@ -928,18 +896,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x68,0xd3]
vcvttph2ibs %ymm3, %ymm2
-// CHECK: vcvttph2ibs {sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x68,0xd3]
- vcvttph2ibs {sae}, %ymm3, %ymm2
-
// CHECK: vcvttph2ibs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x68,0xd3]
vcvttph2ibs %ymm3, %ymm2 {%k7}
-// CHECK: vcvttph2ibs {sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0x78,0x9f,0x68,0xd3]
- vcvttph2ibs {sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvttph2ibs 268435456(%esp,%esi,8), %xmm2
// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x68,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvttph2ibs 268435456(%esp,%esi,8), %xmm2
@@ -1044,18 +1004,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x6a,0xd3]
vcvttph2iubs %ymm3, %ymm2
-// CHECK: vcvttph2iubs {sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x6a,0xd3]
- vcvttph2iubs {sae}, %ymm3, %ymm2
-
// CHECK: vcvttph2iubs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x6a,0xd3]
vcvttph2iubs %ymm3, %ymm2 {%k7}
-// CHECK: vcvttph2iubs {sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0x78,0x9f,0x6a,0xd3]
- vcvttph2iubs {sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvttph2iubs 268435456(%esp,%esi,8), %xmm2
// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x6a,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvttph2iubs 268435456(%esp,%esi,8), %xmm2
@@ -1160,18 +1112,10 @@
// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x68,0xd3]
vcvttps2ibs %ymm3, %ymm2
-// CHECK: vcvttps2ibs {sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0x79,0x18,0x68,0xd3]
- vcvttps2ibs {sae}, %ymm3, %ymm2
-
// CHECK: vcvttps2ibs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0x7d,0x2f,0x68,0xd3]
vcvttps2ibs %ymm3, %ymm2 {%k7}
-// CHECK: vcvttps2ibs {sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0x79,0x9f,0x68,0xd3]
- vcvttps2ibs {sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvttps2ibs 268435456(%esp,%esi,8), %xmm2
// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x68,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvttps2ibs 268435456(%esp,%esi,8), %xmm2
@@ -1276,18 +1220,10 @@
// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x6a,0xd3]
vcvttps2iubs %ymm3, %ymm2
-// CHECK: vcvttps2iubs {sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0x79,0x18,0x6a,0xd3]
- vcvttps2iubs {sae}, %ymm3, %ymm2
-
// CHECK: vcvttps2iubs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0x7d,0x2f,0x6a,0xd3]
vcvttps2iubs %ymm3, %ymm2 {%k7}
-// CHECK: vcvttps2iubs {sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0x79,0x9f,0x6a,0xd3]
- vcvttps2iubs {sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvttps2iubs 268435456(%esp,%esi,8), %xmm2
// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x6a,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvttps2iubs 268435456(%esp,%esi,8), %xmm2
diff --git a/llvm/test/MC/X86/avx10.2satcvt-32-intel.s b/llvm/test/MC/X86/avx10.2satcvt-32-intel.s
index d0b87054a2a86..8c1c36787385a 100644
--- a/llvm/test/MC/X86/avx10.2satcvt-32-intel.s
+++ b/llvm/test/MC/X86/avx10.2satcvt-32-intel.s
@@ -248,18 +248,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x69,0xd3]
vcvtph2ibs ymm2, ymm3
-// CHECK: vcvtph2ibs ymm2, ymm3, {rn-sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x69,0xd3]
- vcvtph2ibs ymm2, ymm3, {rn-sae}
-
// CHECK: vcvtph2ibs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x69,0xd3]
vcvtph2ibs ymm2 {k7}, ymm3
-// CHECK: vcvtph2ibs ymm2 {k7} {z}, ymm3, {rz-sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0xff,0x69,0xd3]
- vcvtph2ibs ymm2 {k7} {z}, ymm3, {rz-sae}
-
// CHECK: vcvtph2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x69,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvtph2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
@@ -364,18 +356,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x6b,0xd3]
vcvtph2iubs ymm2, ymm3
-// CHECK: vcvtph2iubs ymm2, ymm3, {rn-sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x6b,0xd3]
- vcvtph2iubs ymm2, ymm3, {rn-sae}
-
// CHECK: vcvtph2iubs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x6b,0xd3]
vcvtph2iubs ymm2 {k7}, ymm3
-// CHECK: vcvtph2iubs ymm2 {k7} {z}, ymm3, {rz-sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0xff,0x6b,0xd3]
- vcvtph2iubs ymm2 {k7} {z}, ymm3, {rz-sae}
-
// CHECK: vcvtph2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x6b,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvtph2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
@@ -480,18 +464,10 @@
// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x69,0xd3]
vcvtps2ibs ymm2, ymm3
-// CHECK: vcvtps2ibs ymm2, ymm3, {rn-sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0x18,0x69,0xd3]
- vcvtps2ibs ymm2, ymm3, {rn-sae}
-
// CHECK: vcvtps2ibs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0x7d,0x2f,0x69,0xd3]
vcvtps2ibs ymm2 {k7}, ymm3
-// CHECK: vcvtps2ibs ymm2 {k7} {z}, ymm3, {rz-sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0xff,0x69,0xd3]
- vcvtps2ibs ymm2 {k7} {z}, ymm3, {rz-sae}
-
// CHECK: vcvtps2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x69,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvtps2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
@@ -596,18 +572,10 @@
// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x6b,0xd3]
vcvtps2iubs ymm2, ymm3
-// CHECK: vcvtps2iubs ymm2, ymm3, {rn-sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0x18,0x6b,0xd3]
- vcvtps2iubs ymm2, ymm3, {rn-sae}
-
// CHECK: vcvtps2iubs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0x7d,0x2f,0x6b,0xd3]
vcvtps2iubs ymm2 {k7}, ymm3
-// CHECK: vcvtps2iubs ymm2 {k7} {z}, ymm3, {rz-sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0xff,0x6b,0xd3]
- vcvtps2iubs ymm2 {k7} {z}, ymm3, {rz-sae}
-
// CHECK: vcvtps2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x6b,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvtps2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
@@ -928,18 +896,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x68,0xd3]
vcvttph2ibs ymm2, ymm3
-// CHECK: vcvttph2ibs ymm2, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x68,0xd3]
- vcvttph2ibs ymm2, ymm3, {sae}
-
// CHECK: vcvttph2ibs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x68,0xd3]
vcvttph2ibs ymm2 {k7}, ymm3
-// CHECK: vcvttph2ibs ymm2 {k7} {z}, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0x9f,0x68,0xd3]
- vcvttph2ibs ymm2 {k7} {z}, ymm3, {sae}
-
// CHECK: vcvttph2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x68,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvttph2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
@@ -1044,18 +1004,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x6a,0xd3]
vcvttph2iubs ymm2, ymm3
-// CHECK: vcvttph2iubs ymm2, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x6a,0xd3]
- vcvttph2iubs ymm2, ymm3, {sae}
-
// CHECK: vcvttph2iubs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x6a,0xd3]
vcvttph2iubs ymm2 {k7}, ymm3
-// CHECK: vcvttph2iubs ymm2 {k7} {z}, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0x9f,0x6a,0xd3]
- vcvttph2iubs ymm2 {k7} {z}, ymm3, {sae}
-
// CHECK: vcvttph2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
// CHECK: encoding: [0x62,0xf5,0x7c,0x08,0x6a,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvttph2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
@@ -1160,18 +1112,10 @@
// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x68,0xd3]
vcvttps2ibs ymm2, ymm3
-// CHECK: vcvttps2ibs ymm2, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0x18,0x68,0xd3]
- vcvttps2ibs ymm2, ymm3, {sae}
-
// CHECK: vcvttps2ibs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0x7d,0x2f,0x68,0xd3]
vcvttps2ibs ymm2 {k7}, ymm3
-// CHECK: vcvttps2ibs ymm2 {k7} {z}, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0x9f,0x68,0xd3]
- vcvttps2ibs ymm2 {k7} {z}, ymm3, {sae}
-
// CHECK: vcvttps2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x68,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvttps2ibs xmm2, xmmword ptr [esp + 8*esi + 268435456]
@@ -1276,18 +1220,10 @@
// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x6a,0xd3]
vcvttps2iubs ymm2, ymm3
-// CHECK: vcvttps2iubs ymm2, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0x18,0x6a,0xd3]
- vcvttps2iubs ymm2, ymm3, {sae}
-
// CHECK: vcvttps2iubs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0x7d,0x2f,0x6a,0xd3]
vcvttps2iubs ymm2 {k7}, ymm3
-// CHECK: vcvttps2iubs ymm2 {k7} {z}, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0x9f,0x6a,0xd3]
- vcvttps2iubs ymm2 {k7} {z}, ymm3, {sae}
-
// CHECK: vcvttps2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
// CHECK: encoding: [0x62,0xf5,0x7d,0x08,0x6a,0x94,0xf4,0x00,0x00,0x00,0x10]
vcvttps2iubs xmm2, xmmword ptr [esp + 8*esi + 268435456]
diff --git a/llvm/test/MC/X86/avx10.2satcvt-64-att.s b/llvm/test/MC/X86/avx10.2satcvt-64-att.s
index a5f9a62a1f835..248b74c2005b0 100644
--- a/llvm/test/MC/X86/avx10.2satcvt-64-att.s
+++ b/llvm/test/MC/X86/avx10.2satcvt-64-att.s
@@ -248,18 +248,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x69,0xf7]
vcvtph2ibs %ymm23, %ymm22
-// CHECK: vcvtph2ibs {rn-sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x69,0xf7]
- vcvtph2ibs {rn-sae}, %ymm23, %ymm22
-
// CHECK: vcvtph2ibs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x69,0xf7]
vcvtph2ibs %ymm23, %ymm22 {%k7}
-// CHECK: vcvtph2ibs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0x78,0xff,0x69,0xf7]
- vcvtph2ibs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvtph2ibs 268435456(%rbp,%r14,8), %xmm22
// CHECK: encoding: [0x62,0xa5,0x7c,0x08,0x69,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvtph2ibs 268435456(%rbp,%r14,8), %xmm22
@@ -364,18 +356,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x6b,0xf7]
vcvtph2iubs %ymm23, %ymm22
-// CHECK: vcvtph2iubs {rn-sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x6b,0xf7]
- vcvtph2iubs {rn-sae}, %ymm23, %ymm22
-
// CHECK: vcvtph2iubs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x6b,0xf7]
vcvtph2iubs %ymm23, %ymm22 {%k7}
-// CHECK: vcvtph2iubs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0x78,0xff,0x6b,0xf7]
- vcvtph2iubs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvtph2iubs 268435456(%rbp,%r14,8), %xmm22
// CHECK: encoding: [0x62,0xa5,0x7c,0x08,0x6b,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvtph2iubs 268435456(%rbp,%r14,8), %xmm22
@@ -480,18 +464,10 @@
// CHECK: encoding: [0x62,0xa5,0x7d,0x28,0x69,0xf7]
vcvtps2ibs %ymm23, %ymm22
-// CHECK: vcvtps2ibs {rn-sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0x79,0x18,0x69,0xf7]
- vcvtps2ibs {rn-sae}, %ymm23, %ymm22
-
// CHECK: vcvtps2ibs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0x7d,0x2f,0x69,0xf7]
vcvtps2ibs %ymm23, %ymm22 {%k7}
-// CHECK: vcvtps2ibs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0x79,0xff,0x69,0xf7]
- vcvtps2ibs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvtps2ibs 268435456(%rbp,%r14,8), %xmm22
// CHECK: encoding: [0x62,0xa5,0x7d,0x08,0x69,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvtps2ibs 268435456(%rbp,%r14,8), %xmm22
@@ -596,18 +572,10 @@
// CHECK: encoding: [0x62,0xa5,0x7d,0x28,0x6b,0xf7]
vcvtps2iubs %ymm23, %ymm22
-// CHECK: vcvtps2iubs {rn-sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0x79,0x18,0x6b,0xf7]
- vcvtps2iubs {rn-sae}, %ymm23, %ymm22
-
// CHECK: vcvtps2iubs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0x7d,0x2f,0x6b,0xf7]
vcvtps2iubs %ymm23, %ymm22 {%k7}
-// CHECK: vcvtps2iubs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0x79,0xff,0x6b,0xf7]
- vcvtps2iubs {rz-sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvtps2iubs 268435456(%rbp,%r14,8), %xmm22
// CHECK: encoding: [0x62,0xa5,0x7d,0x08,0x6b,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvtps2iubs 268435456(%rbp,%r14,8), %xmm22
@@ -928,18 +896,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x68,0xf7]
vcvttph2ibs %ymm23, %ymm22
-// CHECK: vcvttph2ibs {sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x68,0xf7]
- vcvttph2ibs {sae}, %ymm23, %ymm22
-
// CHECK: vcvttph2ibs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x68,0xf7]
vcvttph2ibs %ymm23, %ymm22 {%k7}
-// CHECK: vcvttph2ibs {sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0x78,0x9f,0x68,0xf7]
- vcvttph2ibs {sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvttph2ibs 268435456(%rbp,%r14,8), %xmm22
// CHECK: encoding: [0x62,0xa5,0x7c,0x08,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvttph2ibs 268435456(%rbp,%r14,8), %xmm22
@@ -1044,18 +1004,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x6a,0xf7]
vcvttph2iubs %ymm23, %ymm22
-// CHECK: vcvttph2iubs {sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x6a,0xf7]
- vcvttph2iubs {sae}, %ymm23, %ymm22
-
// CHECK: vcvttph2iubs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x6a,0xf7]
vcvttph2iubs %ymm23, %ymm22 {%k7}
-// CHECK: vcvttph2iubs {sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0x78,0x9f,0x6a,0xf7]
- vcvttph2iubs {sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvttph2iubs 268435456(%rbp,%r14,8), %xmm22
// CHECK: encoding: [0x62,0xa5,0x7c,0x08,0x6a,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvttph2iubs 268435456(%rbp,%r14,8), %xmm22
@@ -1160,18 +1112,10 @@
// CHECK: encoding: [0x62,0xa5,0x7d,0x28,0x68,0xf7]
vcvttps2ibs %ymm23, %ymm22
-// CHECK: vcvttps2ibs {sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0x79,0x18,0x68,0xf7]
- vcvttps2ibs {sae}, %ymm23, %ymm22
-
// CHECK: vcvttps2ibs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0x7d,0x2f,0x68,0xf7]
vcvttps2ibs %ymm23, %ymm22 {%k7}
-// CHECK: vcvttps2ibs {sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0x79,0x9f,0x68,0xf7]
- vcvttps2ibs {sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvttps2ibs 268435456(%rbp,%r14,8), %xmm22
// CHECK: encoding: [0x62,0xa5,0x7d,0x08,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvttps2ibs 268435456(%rbp,%r14,8), %xmm22
@@ -1276,18 +1220,10 @@
// CHECK: encoding: [0x62,0xa5,0x7d,0x28,0x6a,0xf7]
vcvttps2iubs %ymm23, %ymm22
-// CHECK: vcvttps2iubs {sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0x79,0x18,0x6a,0xf7]
- vcvttps2iubs {sae}, %ymm23, %ymm22
-
// CHECK: vcvttps2iubs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0x7d,0x2f,0x6a,0xf7]
vcvttps2iubs %ymm23, %ymm22 {%k7}
-// CHECK: vcvttps2iubs {sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0x79,0x9f,0x6a,0xf7]
- vcvttps2iubs {sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvttps2iubs 268435456(%rbp,%r14,8), %xmm22
// CHECK: encoding: [0x62,0xa5,0x7d,0x08,0x6a,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvttps2iubs 268435456(%rbp,%r14,8), %xmm22
diff --git a/llvm/test/MC/X86/avx10.2satcvt-64-intel.s b/llvm/test/MC/X86/avx10.2satcvt-64-intel.s
index e633842abf43d..6afc4fca3e680 100644
--- a/llvm/test/MC/X86/avx10.2satcvt-64-intel.s
+++ b/llvm/test/MC/X86/avx10.2satcvt-64-intel.s
@@ -248,18 +248,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x69,0xf7]
vcvtph2ibs ymm22, ymm23
-// CHECK: vcvtph2ibs ymm22, ymm23, {rn-sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x69,0xf7]
- vcvtph2ibs ymm22, ymm23, {rn-sae}
-
// CHECK: vcvtph2ibs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x69,0xf7]
vcvtph2ibs ymm22 {k7}, ymm23
-// CHECK: vcvtph2ibs ymm22 {k7} {z}, ymm23, {rz-sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0xff,0x69,0xf7]
- vcvtph2ibs ymm22 {k7} {z}, ymm23, {rz-sae}
-
// CHECK: vcvtph2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0x62,0xa5,0x7c,0x08,0x69,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvtph2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
@@ -364,18 +356,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x6b,0xf7]
vcvtph2iubs ymm22, ymm23
-// CHECK: vcvtph2iubs ymm22, ymm23, {rn-sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x6b,0xf7]
- vcvtph2iubs ymm22, ymm23, {rn-sae}
-
// CHECK: vcvtph2iubs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x6b,0xf7]
vcvtph2iubs ymm22 {k7}, ymm23
-// CHECK: vcvtph2iubs ymm22 {k7} {z}, ymm23, {rz-sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0xff,0x6b,0xf7]
- vcvtph2iubs ymm22 {k7} {z}, ymm23, {rz-sae}
-
// CHECK: vcvtph2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0x62,0xa5,0x7c,0x08,0x6b,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvtph2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
@@ -480,18 +464,10 @@
// CHECK: encoding: [0x62,0xa5,0x7d,0x28,0x69,0xf7]
vcvtps2ibs ymm22, ymm23
-// CHECK: vcvtps2ibs ymm22, ymm23, {rn-sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0x18,0x69,0xf7]
- vcvtps2ibs ymm22, ymm23, {rn-sae}
-
// CHECK: vcvtps2ibs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0x7d,0x2f,0x69,0xf7]
vcvtps2ibs ymm22 {k7}, ymm23
-// CHECK: vcvtps2ibs ymm22 {k7} {z}, ymm23, {rz-sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0xff,0x69,0xf7]
- vcvtps2ibs ymm22 {k7} {z}, ymm23, {rz-sae}
-
// CHECK: vcvtps2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0x62,0xa5,0x7d,0x08,0x69,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvtps2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
@@ -596,18 +572,10 @@
// CHECK: encoding: [0x62,0xa5,0x7d,0x28,0x6b,0xf7]
vcvtps2iubs ymm22, ymm23
-// CHECK: vcvtps2iubs ymm22, ymm23, {rn-sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0x18,0x6b,0xf7]
- vcvtps2iubs ymm22, ymm23, {rn-sae}
-
// CHECK: vcvtps2iubs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0x7d,0x2f,0x6b,0xf7]
vcvtps2iubs ymm22 {k7}, ymm23
-// CHECK: vcvtps2iubs ymm22 {k7} {z}, ymm23, {rz-sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0xff,0x6b,0xf7]
- vcvtps2iubs ymm22 {k7} {z}, ymm23, {rz-sae}
-
// CHECK: vcvtps2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0x62,0xa5,0x7d,0x08,0x6b,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvtps2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
@@ -928,18 +896,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x68,0xf7]
vcvttph2ibs ymm22, ymm23
-// CHECK: vcvttph2ibs ymm22, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x68,0xf7]
- vcvttph2ibs ymm22, ymm23, {sae}
-
// CHECK: vcvttph2ibs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x68,0xf7]
vcvttph2ibs ymm22 {k7}, ymm23
-// CHECK: vcvttph2ibs ymm22 {k7} {z}, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0x9f,0x68,0xf7]
- vcvttph2ibs ymm22 {k7} {z}, ymm23, {sae}
-
// CHECK: vcvttph2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0x62,0xa5,0x7c,0x08,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvttph2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
@@ -1044,18 +1004,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x6a,0xf7]
vcvttph2iubs ymm22, ymm23
-// CHECK: vcvttph2iubs ymm22, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x6a,0xf7]
- vcvttph2iubs ymm22, ymm23, {sae}
-
// CHECK: vcvttph2iubs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x6a,0xf7]
vcvttph2iubs ymm22 {k7}, ymm23
-// CHECK: vcvttph2iubs ymm22 {k7} {z}, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0x9f,0x6a,0xf7]
- vcvttph2iubs ymm22 {k7} {z}, ymm23, {sae}
-
// CHECK: vcvttph2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0x62,0xa5,0x7c,0x08,0x6a,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvttph2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
@@ -1160,18 +1112,10 @@
// CHECK: encoding: [0x62,0xa5,0x7d,0x28,0x68,0xf7]
vcvttps2ibs ymm22, ymm23
-// CHECK: vcvttps2ibs ymm22, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0x18,0x68,0xf7]
- vcvttps2ibs ymm22, ymm23, {sae}
-
// CHECK: vcvttps2ibs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0x7d,0x2f,0x68,0xf7]
vcvttps2ibs ymm22 {k7}, ymm23
-// CHECK: vcvttps2ibs ymm22 {k7} {z}, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0x9f,0x68,0xf7]
- vcvttps2ibs ymm22 {k7} {z}, ymm23, {sae}
-
// CHECK: vcvttps2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0x62,0xa5,0x7d,0x08,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvttps2ibs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
@@ -1276,18 +1220,10 @@
// CHECK: encoding: [0x62,0xa5,0x7d,0x28,0x6a,0xf7]
vcvttps2iubs ymm22, ymm23
-// CHECK: vcvttps2iubs ymm22, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0x18,0x6a,0xf7]
- vcvttps2iubs ymm22, ymm23, {sae}
-
// CHECK: vcvttps2iubs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0x7d,0x2f,0x6a,0xf7]
vcvttps2iubs ymm22 {k7}, ymm23
-// CHECK: vcvttps2iubs ymm22 {k7} {z}, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0x9f,0x6a,0xf7]
- vcvttps2iubs ymm22 {k7} {z}, ymm23, {sae}
-
// CHECK: vcvttps2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0x62,0xa5,0x7d,0x08,0x6a,0xb4,0xf5,0x00,0x00,0x00,0x10]
vcvttps2iubs xmm22, xmmword ptr [rbp + 8*r14 + 268435456]
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