[llvm] [SPIRV] Support for SPV_INTEL_cluster_attributes extension (PR #131593)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 17 03:04:50 PDT 2025
https://github.com/EbinJose2002 created https://github.com/llvm/llvm-project/pull/131593
- Support for SPV_INTEL_cluster_attributes extension
- Added decorations for StallEnableINTEL and StallFreeINTEL
>From 7b218f58ebbeb5b7a694b481e9a646b85b1785d9 Mon Sep 17 00:00:00 2001
From: EbinJose2002 <ebin.jose at multicorewareinc.com>
Date: Mon, 17 Mar 2025 13:16:01 +0530
Subject: [PATCH] - Support for SPV_INTEL_cluster_attributes extension - Added
decorations for StallEnableINTEL and StallFreeINTEL
---
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 4 +-
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 70 +++++++++++++++++++
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 4 ++
.../cluster_attributes.ll | 22 ++++++
4 files changed, 99 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cluster_attributes/cluster_attributes.ll
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 37119bf01545c..5406869249590 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -92,7 +92,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
{"SPV_INTEL_long_composites",
SPIRV::Extension::Extension::SPV_INTEL_long_composites},
{"SPV_INTEL_fp_max_error",
- SPIRV::Extension::Extension::SPV_INTEL_fp_max_error}};
+ SPIRV::Extension::Extension::SPV_INTEL_fp_max_error},
+ {"SPV_INTEL_fpga_cluster_attributes",
+ SPIRV::Extension::Extension::SPV_INTEL_fpga_cluster_attributes}};
bool SPIRVExtensionsParser::parse(cl::Option &O, llvm::StringRef ArgName,
llvm::StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index 63894acacbc73..0a32cf138004c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -891,6 +891,10 @@ static void addOpDecorateReqs(const MachineInstr &MI, unsigned DecIndex,
} else if (Dec == SPIRV::Decoration::FPMaxErrorDecorationINTEL) {
Reqs.addRequirements(SPIRV::Capability::FPMaxErrorINTEL);
Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fp_max_error);
+ } else if (Dec == SPIRV::Decoration::StallEnableINTEL) {
+ Reqs.addRequirements(SPIRV::Capability::FPGAClusterAttributesINTEL);
+ } else if (Dec == SPIRV::Decoration::StallFreeINTEL) {
+ Reqs.addRequirements(SPIRV::Capability::FPGAClusterAttributesV2INTEL);
}
}
@@ -1922,7 +1926,70 @@ static void handleMIFlagDecoration(MachineInstr &I, const SPIRVSubtarget &ST,
buildOpDecorate(DstReg, I, TII, SPIRV::Decoration::FPFastMathMode, {FMFlags});
}
+static std::vector<uint32_t>
+getMetaDataValues(std::vector<llvm::MDNode *> &MetaDataList) {
+ std::vector<uint32_t> res;
+ for (auto metaDataNode : MetaDataList) {
+ if (metaDataNode->getNumOperands() > 0) {
+ if (auto *CMD = llvm::dyn_cast<llvm::ConstantAsMetadata>(
+ metaDataNode->getOperand(0))) {
+ if (auto *CI = llvm::dyn_cast<llvm::ConstantInt>(CMD->getValue())) {
+ APInt val = CI->getValue();
+ int64_t decVal = val.getZExtValue();
+ res.push_back(decVal);
+ }
+ }
+ }
+ }
+ return res;
+}
+
+static void handleFunctionDecoration(llvm::Module::const_iterator F,
+ const SPIRVInstrInfo &TII,
+ MachineModuleInfo *MMI,
+ const SPIRVSubtarget &ST) {
+ MachineFunction *MF = MMI->getMachineFunction(*F);
+ Register FuncReg;
+ MachineInstr *FirstInstr = nullptr;
+ std::vector<llvm::MDNode *> MetaDataList;
+ // Find function register and first instruction
+ for (auto &MBB : *MF) {
+ for (auto &MI : MBB) {
+ if (MI.getOpcode() == SPIRV::OpFunction) {
+ FirstInstr = &MI;
+ FuncReg = MI.getOperand(0).getReg();
+ break;
+ }
+ }
+ if (FuncReg.isValid() && FirstInstr)
+ break;
+ }
+
+ // Add function-level decorations based on metadata
+ if (MDNode *Node = F->getMetadata("stall_enable")) {
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_fpga_cluster_attributes)) {
+ MetaDataList.push_back(Node);
+ std::vector<uint32_t> params = getMetaDataValues(MetaDataList);
+ if (params.at(0) == 1) {
+ buildOpDecorate(FuncReg, *FirstInstr, TII,
+ SPIRV::Decoration::StallEnableINTEL, {});
+ }
+ }
+ } else if (MDNode *Node = F->getMetadata("stall_free")) {
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_fpga_cluster_attributes)) {
+ MetaDataList.push_back(Node);
+ std::vector<uint32_t> params = getMetaDataValues(MetaDataList);
+ if (params.at(0) == 1) {
+ buildOpDecorate(FuncReg, *FirstInstr, TII,
+ SPIRV::Decoration::StallFreeINTEL, {});
+ }
+ }
+ }
+}
// Walk all functions and add decorations related to MI flags.
+
static void addDecorations(const Module &M, const SPIRVInstrInfo &TII,
MachineModuleInfo *MMI, const SPIRVSubtarget &ST,
SPIRV::ModuleAnalysisInfo &MAI) {
@@ -1930,9 +1997,12 @@ static void addDecorations(const Module &M, const SPIRVInstrInfo &TII,
MachineFunction *MF = MMI->getMachineFunction(*F);
if (!MF)
continue;
+
for (auto &MBB : *MF)
for (auto &MI : MBB)
handleMIFlagDecoration(MI, ST, TII, MAI.Reqs);
+
+ handleFunctionDecoration(F, TII, MMI, ST);
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index caee778eddbc4..dcfbcf282ee77 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -513,6 +513,8 @@ defm LongCompositesINTEL : CapabilityOperand<6089, 0, 0, [SPV_INTEL_long_composi
defm BindlessImagesINTEL : CapabilityOperand<6528, 0, 0, [SPV_INTEL_bindless_images], []>;
defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory_access_aliasing], []>;
defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], []>;
+defm FPGAClusterAttributesINTEL : CapabilityOperand<5904, 0, 0, [SPV_INTEL_fpga_cluster_attributes], []>;
+defm FPGAClusterAttributesV2INTEL : CapabilityOperand<6150, 0, 0, [SPV_INTEL_fpga_cluster_attributes], []>;
//===----------------------------------------------------------------------===//
// Multiclass used to define SourceLanguage enum values and at the same time
@@ -1264,6 +1266,8 @@ defm FunctionFloatingPointModeINTEL : DecorationOperand<6080, 0, 0, [], [Functio
defm AliasScopeINTEL : DecorationOperand<5914, 0, 0, [], [MemoryAccessAliasingINTEL]>;
defm NoAliasINTEL : DecorationOperand<5915, 0, 0, [], [MemoryAccessAliasingINTEL]>;
defm FPMaxErrorDecorationINTEL : DecorationOperand<6170, 0, 0, [], [FPMaxErrorINTEL]>;
+defm StallEnableINTEL : DecorationOperand<5905, 0, 0, [SPV_INTEL_fpga_cluster_attributes], [FPGAClusterAttributesINTEL]>;
+defm StallFreeINTEL : DecorationOperand<6151, 0, 0, [SPV_INTEL_fpga_cluster_attributes], [FPGAClusterAttributesV2INTEL]>;
//===----------------------------------------------------------------------===//
// Multiclass used to define BuiltIn enum values and at the same time
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cluster_attributes/cluster_attributes.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cluster_attributes/cluster_attributes.ll
new file mode 100644
index 0000000000000..bbc1949766118
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cluster_attributes/cluster_attributes.ll
@@ -0,0 +1,22 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_fpga_cluster_attributes %s -o - | FileCheck %s
+
+; CHECK-DAG: OpCapability FPGAClusterAttributesINTEL
+; CHECK-DAG: OpCapability FPGAClusterAttributesV2INTEL
+; CHECK-DAG: OpExtension "SPV_INTEL_fpga_cluster_attributes"
+; CHECK-DAG: OpDecorate %[[#STALLENABLE_DEC:]] StallEnableINTEL
+; CHECK-DAG: OpDecorate %[[#STALLFREE_DEC:]] StallFreeINTEL
+; CHECK: %[[#STALLENABLE_DEC]] = OpFunction %[[#]] None %[[#]]
+; CHECK: %[[#STALLFREE_DEC]] = OpFunction %[[#]] None %[[#]]
+
+define spir_func void @test_fpga_stallenable_attr() !stall_enable !0 {
+ entry:
+ ret void
+}
+
+define spir_func void @test_fpga_stallfree_attr() !stall_free !1 {
+ entry:
+ ret void
+}
+
+!0 = !{ i32 1 }
+!1 = !{ i32 1 }
\ No newline at end of file
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