[llvm] [X86] Prevent APX NDD compression when it creates a partial write (PR #132051)

[Daniel Zabawa via llvm-commits]

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@@ -6793,19 +6793,42 @@ static bool hasPartialRegUpdate(unsigned Opcode, const X86Subtarget &Subtarget,
 unsigned X86InstrInfo::getPartialRegUpdateClearance(
     const MachineInstr &MI, unsigned OpNum,
     const TargetRegisterInfo *TRI) const {
-  if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
+
+  // With the NDD/ZU features, ISel may generate NDD/ZU ops which
+  // appear to perform partial writes. We detect these based on flags
+  // and register class.
+  bool HasNDDPartialWrite = false;
+  if (OpNum == 0 && (Subtarget.hasNDD() || Subtarget.hasZU()) &&
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daniel-zabawa wrote:

The idea was to prevent checking individual instructions if the feature is disabled. This code previously only considered select instructions covered by hasPartialRegUpdate, so I was concerned about compile time impact now that a much wider set of opcodes are considered.

https://github.com/llvm/llvm-project/pull/132051