[llvm] [NVPTX] Improve 64bit FSH/ROT lowering when shift amount is constant (PR #131371)

Alex MacLean via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 17 13:34:51 PDT 2025


================
@@ -2758,6 +2764,53 @@ static SDValue lowerCTLZCTPOP(SDValue Op, SelectionDAG &DAG) {
   return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, CT, SDNodeFlags::NonNeg);
 }
 
+static SDValue expandFSH64(SDValue A, SDValue B, SDValue AmtVal, SDLoc DL,
----------------
AlexMaclean wrote:

Done

https://github.com/llvm/llvm-project/pull/131371


More information about the llvm-commits mailing list