[llvm] [AMDGPU][True16][CodeGen] fix moveToVALU with proper subreg access in true16 (PR #131859)

[Matt Arsenault via llvm-commits]

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@@ -6297,6 +6297,12 @@ void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
       continue;
     }
 
+    // True16 Operands cannot contain VGPR_32 (typically occurs during
+    // SIFixSGPRCopies). True16 instructions are always selected as VOP3
+    if (ST.useRealTrue16Insts() && AMDGPU::isTrue16Inst(Opc) && MO.isReg() &&
+        MRI.getRegClass(MO.getReg()) == &AMDGPU::VGPR_32RegClass)
+      legalizeOpWithMove(MI, Idx);
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arsenm wrote:

This shouldn't really happen in the first place. legalizeOperands is mostly a hack because the DAG doesn't really know if an operand is going to be SGPR or VGPR and we need to enforce the constant bus restriction. Getting the correct 32 or 16-bit register class doesn't fit the pattern; you should be able to get this correct from the start 

https://github.com/llvm/llvm-project/pull/131859