[llvm] 97213b3 - [MC] Return MCRegister from MCRegisterClass::getRegister. NFC (#132126)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 20 07:24:57 PDT 2025
Author: Craig Topper
Date: 2025-03-20T07:24:53-07:00
New Revision: 97213b39edea06f78b76d4baf299c0ffa323a9d6
URL: https://github.com/llvm/llvm-project/commit/97213b39edea06f78b76d4baf299c0ffa323a9d6
DIFF: https://github.com/llvm/llvm-project/commit/97213b39edea06f78b76d4baf299c0ffa323a9d6.diff
LOG: [MC] Return MCRegister from MCRegisterClass::getRegister. NFC (#132126)
Replace unsigned with MCRegister at some of the call sites.
Added:
Modified:
llvm/include/llvm/MC/MCRegisterInfo.h
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index 1579ecb035c21..f780bdb97d4fd 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -63,7 +63,7 @@ class MCRegisterClass {
/// getRegister - Return the specified register in the class.
///
- unsigned getRegister(unsigned i) const {
+ MCRegister getRegister(unsigned i) const {
assert(i < getNumRegs() && "Register number out of range!");
return RegsBegin[i];
}
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 47c0a1fab08f7..79b190388eb75 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -1141,7 +1141,7 @@ bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
assert(MO.isReg() && "Should only get here with a register!");
const TargetRegisterInfo *RI = STI->getRegisterInfo();
Register Reg = MO.getReg();
- unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
+ MCRegister RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
if (!RI->regsOverlap(RegToPrint, Reg))
return true;
O << AArch64InstPrinter::getRegisterName(RegToPrint, AltName);
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index ab9b31ccbe288..d678dd88e05da 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1794,8 +1794,8 @@ class AArch64Operand : public MCParsedAsmOperand {
AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(getReg()));
const MCRegisterInfo *RI = Ctx.getRegisterInfo();
- uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister(
- RI->getEncodingValue(getReg()));
+ MCRegister Reg = RI->getRegClass(AArch64::GPR32RegClassID)
+ .getRegister(RI->getEncodingValue(getReg()));
Inst.addOperand(MCOperand::createReg(Reg));
}
@@ -1806,8 +1806,8 @@ class AArch64Operand : public MCParsedAsmOperand {
AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(getReg()));
const MCRegisterInfo *RI = Ctx.getRegisterInfo();
- uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID).getRegister(
- RI->getEncodingValue(getReg()));
+ MCRegister Reg = RI->getRegClass(AArch64::GPR64RegClassID)
+ .getRegister(RI->getEncodingValue(getReg()));
Inst.addOperand(MCOperand::createReg(Reg));
}
@@ -2227,8 +2227,8 @@ class AArch64Operand : public MCParsedAsmOperand {
return;
const MCRegisterInfo *RI = Ctx.getRegisterInfo();
- uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID)
- .getRegister(RI->getEncodingValue(getReg()));
+ MCRegister Reg = RI->getRegClass(AArch64::GPR64RegClassID)
+ .getRegister(RI->getEncodingValue(getReg()));
if (Reg != AArch64::XZR)
llvm_unreachable("wrong register");
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index f78e6926f2c7d..bab0cbe7788e9 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -341,7 +341,7 @@ static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
if (RegNo > NumRegsInClass - 1)
return Fail;
- unsigned Register =
+ MCRegister Register =
AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
@@ -355,7 +355,7 @@ DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
if (RegNo & 1)
return Fail;
- unsigned Register =
+ MCRegister Register =
AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
RegNo >> 1);
Inst.addOperand(MCOperand::createReg(Register));
@@ -369,7 +369,7 @@ static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
unsigned Reg = (RegNo * 2) + Min;
if (Reg < Min || Reg > Max || (Reg & 1))
return Fail;
- unsigned Register =
+ MCRegister Register =
AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
@@ -383,7 +383,7 @@ static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
if (Reg < Min || Reg > Max || (Reg & 1))
return Fail;
- unsigned Register =
+ MCRegister Register =
AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(Reg);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
@@ -394,7 +394,7 @@ static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
if (RegNo > 7)
return Fail;
- unsigned Register =
+ MCRegister Register =
AArch64MCRegisterClasses[AArch64::ZPR_KRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
@@ -405,7 +405,7 @@ static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
const void *Decoder) {
if (RegNo * 4 > 28)
return Fail;
- unsigned Register =
+ MCRegister Register =
AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
@@ -449,7 +449,7 @@ static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
const void *Decoder) {
if ((RegNo * 2) > 14)
return Fail;
- unsigned Register =
+ MCRegister Register =
AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
@@ -1655,7 +1655,7 @@ DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
if (RegNo & 0x1)
return Fail;
- unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
+ MCRegister Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
Inst.addOperand(MCOperand::createReg(Reg));
return Success;
}
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index fb586fa090321..8d27153fcfcde 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -1062,7 +1062,8 @@ void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
- unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
+ MCRegister Reg =
+ R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
TRI.reserveRegisterTuples(Reserved, Reg);
}
}
@@ -1084,7 +1085,7 @@ MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
unsigned ValueReg, unsigned Address,
unsigned OffsetReg,
unsigned AddrChan) const {
- unsigned AddrReg;
+ MCRegister AddrReg;
switch (AddrChan) {
default: llvm_unreachable("Invalid Channel");
case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
@@ -1116,7 +1117,7 @@ MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
unsigned ValueReg, unsigned Address,
unsigned OffsetReg,
unsigned AddrChan) const {
- unsigned AddrReg;
+ MCRegister AddrReg;
switch (AddrChan) {
default: llvm_unreachable("Invalid Channel");
case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index d6a586e1f247b..3f0711910ca44 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -6983,7 +6983,7 @@ void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
}
if (Op2.getReg() == ARM::PC)
return;
- unsigned PairedReg = GPR.getRegister(RtEncoding + 1);
+ MCRegister PairedReg = GPR.getRegister(RtEncoding + 1);
if (!PairedReg || PairedReg == ARM::PC ||
(PairedReg == ARM::SP && !hasV8Ops()))
return;
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 2a2ebd63d6b47..568f020d9d2fe 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -856,7 +856,7 @@ class MipsOperand : public MCParsedAsmOperand {
public:
/// Coerce the register to GPR32 and return the real register for the current
/// target.
- unsigned getGPR32Reg() const {
+ MCRegister getGPR32Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
unsigned ClassID = Mips::GPR32RegClassID;
@@ -865,7 +865,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to GPR32 and return the real register for the current
/// target.
- unsigned getGPRMM16Reg() const {
+ MCRegister getGPRMM16Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
unsigned ClassID = Mips::GPR32RegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -873,7 +873,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to GPR64 and return the real register for the current
/// target.
- unsigned getGPR64Reg() const {
+ MCRegister getGPR64Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
unsigned ClassID = Mips::GPR64RegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -882,7 +882,7 @@ class MipsOperand : public MCParsedAsmOperand {
private:
/// Coerce the register to AFGR64 and return the real register for the current
/// target.
- unsigned getAFGR64Reg() const {
+ MCRegister getAFGR64Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
if (RegIdx.Index % 2 != 0)
AsmParser.Warning(StartLoc, "Float register should be even.");
@@ -892,7 +892,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to FGR64 and return the real register for the current
/// target.
- unsigned getFGR64Reg() const {
+ MCRegister getFGR64Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
.getRegister(RegIdx.Index);
@@ -900,7 +900,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to FGR32 and return the real register for the current
/// target.
- unsigned getFGR32Reg() const {
+ MCRegister getFGR32Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
.getRegister(RegIdx.Index);
@@ -908,7 +908,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to FCC and return the real register for the current
/// target.
- unsigned getFCCReg() const {
+ MCRegister getFCCReg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
.getRegister(RegIdx.Index);
@@ -916,7 +916,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to MSA128 and return the real register for the current
/// target.
- unsigned getMSA128Reg() const {
+ MCRegister getMSA128Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
// It doesn't matter which of the MSA128[BHWD] classes we use. They are all
// identical
@@ -926,7 +926,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to MSACtrl and return the real register for the
/// current target.
- unsigned getMSACtrlReg() const {
+ MCRegister getMSACtrlReg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
unsigned ClassID = Mips::MSACtrlRegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -934,7 +934,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to COP0 and return the real register for the
/// current target.
- unsigned getCOP0Reg() const {
+ MCRegister getCOP0Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!");
unsigned ClassID = Mips::COP0RegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -942,7 +942,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to COP2 and return the real register for the
/// current target.
- unsigned getCOP2Reg() const {
+ MCRegister getCOP2Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
unsigned ClassID = Mips::COP2RegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -950,7 +950,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to COP3 and return the real register for the
/// current target.
- unsigned getCOP3Reg() const {
+ MCRegister getCOP3Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");
unsigned ClassID = Mips::COP3RegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -958,7 +958,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to ACC64DSP and return the real register for the
/// current target.
- unsigned getACC64DSPReg() const {
+ MCRegister getACC64DSPReg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
unsigned ClassID = Mips::ACC64DSPRegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -966,7 +966,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to HI32DSP and return the real register for the
/// current target.
- unsigned getHI32DSPReg() const {
+ MCRegister getHI32DSPReg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
unsigned ClassID = Mips::HI32DSPRegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -974,7 +974,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to LO32DSP and return the real register for the
/// current target.
- unsigned getLO32DSPReg() const {
+ MCRegister getLO32DSPReg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
unsigned ClassID = Mips::LO32DSPRegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -982,7 +982,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to CCR and return the real register for the
/// current target.
- unsigned getCCRReg() const {
+ MCRegister getCCRReg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
unsigned ClassID = Mips::CCRRegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -990,7 +990,7 @@ class MipsOperand : public MCParsedAsmOperand {
/// Coerce the register to HWRegs and return the real register for the
/// current target.
- unsigned getHWRegsReg() const {
+ MCRegister getHWRegsReg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
unsigned ClassID = Mips::HWRegsRegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
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