The Week Of Monday 24 February 2025 Archives by date

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Starting: Mon Feb 24 00:02:18 PST 2025
Ending: Sun Mar 2 23:48:18 PST 2025
Messages: 4921

• [llvm] [WIP][AMDGPU] combine uniform AMDGPU lane Intrinsics (PR #116953)   Pankaj Dwivedi via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   Akshat Oke via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] [CodeGen][NPM] Parse MachineFunctions in NPM driver (PR #128467)   Akshat Oke via llvm-commits
• [llvm] [cpack][NSIS Installer] Make installer DPI-Aware (PR #128470)   via llvm-commits
• [llvm] [Attributor] Do not optimize away externally_initialized loads. (PR #128170)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Djordje Todorovic via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Djordje Todorovic via llvm-commits
• [llvm] [RISCV] Remove unnecessary entries from RISCVVInversePseudosTable. NFC (PR #128376)   Pengcheng Wang via llvm-commits
• [llvm] MachineFunction: Remove null check on TargetRegisterInfo (PR #128480)   Matt Arsenault via llvm-commits
• [llvm] MachineFunction: Remove null check on TargetRegisterInfo (PR #128480)   Matt Arsenault via llvm-commits
• [llvm] MachineFunction: Remove null check on TargetRegisterInfo (PR #128480)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Craig Topper via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Craig Topper via llvm-commits
• [llvm] 5c6453d - [AArch64] Add BF16 REV costs.   David Green via llvm-commits
• [llvm] [RISCV] Remove virtual from getOutliningTypeImpl override. NFC (PR #128482)   Sudharsan Veeravalli via llvm-commits
• [llvm] [RISCV] Remove virtual from getOutliningTypeImpl override. NFC (PR #128482)   via llvm-commits
• [llvm] [ValueTracking] ComputeNumSignBitsImpl - add basic handling of BITCAST nodes (PR #127218)   via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (PR #124706)   via llvm-commits
• [llvm] [ValueTracking] ComputeNumSignBitsImpl - add basic handling of BITCAST nodes (PR #127218)   via llvm-commits
• [llvm] [InstCombine] Fold `X!=Y ? ctz(X^Y, true) : BW -> ctz(X^Y, false)` (PR #128483)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Fold `X!=Y ? ctz(X^Y, true) : BW -> ctz(X^Y, false)` (PR #128483)   via llvm-commits
• [llvm] [DebugInfo] Avoid repeated hash lookups (NFC) (PR #128459)   Nikita Popov via llvm-commits
• [llvm] [X86] Avoid repeated hash lookups (NFC) (PR #128464)   Nikita Popov via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Pengcheng Wang via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   Nikita Popov via llvm-commits
• [llvm] [RISCV] Remove virtual from getOutliningTypeImpl override. NFC (PR #128482)   Pengcheng Wang via llvm-commits
• [llvm] 6ad55f1 - [DebugInfo] Avoid repeated hash lookups (NFC) (#128459)   via llvm-commits
• [llvm] [DebugInfo] Avoid repeated hash lookups (NFC) (PR #128459)   Kazu Hirata via llvm-commits
• [llvm] 47656dc - [X86] Avoid repeated hash lookups (NFC) (#128464)   via llvm-commits
• [llvm] [X86] Avoid repeated hash lookups (NFC) (PR #128464)   Kazu Hirata via llvm-commits
• [llvm] [InstCombine] Simplify nonnull phi nodes (PR #128466)   Nikita Popov via llvm-commits
• [llvm] 229dcf9 - [CodeGen][NPM] Port MachineLateInstrsCleanup to NPM (#128160)   via llvm-commits
• [llvm] [CodeGen][NPM] Port MachineLateInstrsCleanup to NPM (PR #128160)   Akshat Oke via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (PR #124706)   via llvm-commits
• [llvm] [InstCombine] Fold `X!=Y ? ctz(X^Y, true) : BW -> ctz(X^Y, false)` (PR #128483)   Nikita Popov via llvm-commits
• [llvm] [InstCombine] Fold `X!=Y ? ctz(X^Y, true) : BW -> ctz(X^Y, false)` (PR #128483)   Nikita Popov via llvm-commits
• [lld] 301fe47 - [AArch64][ELF] Section alignment of 4 for AArch64 instruction (#114031)   via llvm-commits
• [lld] [llvm] [AArch64][ELF] Section alignment of 4 for AArch64 instruction (PR #114031)   Jack Styles via llvm-commits
• [lld] [llvm] [AArch64][ELF] Section alignment of 4 for AArch64 instruction (PR #114031)   Jack Styles via llvm-commits
• [lld] [llvm] [AArch64][ELF] Section alignment of 4 for AArch64 instruction (PR #114031)   via llvm-commits
• [llvm] On Windows, remove the UCRT libraries from the release script (PR #128378)   Hans Wennborg via llvm-commits
• [llvm] [MachineBasicBlock][NFC] Decouple SplitCriticalEdges from pass manager (PR #128151)   Akshat Oke via llvm-commits
• [llvm] [InstCombine] Fold `X!=Y ? ctz(X^Y, true) : BW -> ctz(X^Y, false)` (PR #128483)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Fold `X!=Y ? ctz(X^Y, true) : BW -> ctz(X^Y, false)` (PR #128483)   Nikita Popov via llvm-commits
• [llvm] 7a9f53c - [X86] combineBROADCAST_LOAD - merge across chains (REAPPLIED) (#128209)   Simon Pilgrim via llvm-commits
• [llvm] Introduce CovMap in ObjectYAML (PR #127432)   James Henderson via llvm-commits
• [llvm] Introduce CovMap in ObjectYAML (PR #127432)   James Henderson via llvm-commits
• [llvm] Introduce CovMap in ObjectYAML (PR #127432)   James Henderson via llvm-commits
• [llvm] Introduce CovMap in ObjectYAML (PR #127432)   James Henderson via llvm-commits
• [llvm] Introduce CovMap in ObjectYAML (PR #127432)   James Henderson via llvm-commits
• [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)   Akshat Oke via llvm-commits
• [llvm] [InstCombine] Fold `X!=Y ? ctz(X^Y, true) : BW -> ctz(X^Y, false)` (PR #128483)   Nikita Popov via llvm-commits
• [llvm] [MachineBasicBlock][NFC] Decouple SplitCriticalEdges from pass manager (PR #128151)   Akshat Oke via llvm-commits
• [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)   Akshat Oke via llvm-commits
• [llvm] c5f40bf - [InstCombine] Fold `X!=Y ? ctz(X^Y, true) : BW -> ctz(X^Y, false)` (#128483)   via llvm-commits
• [llvm] [InstCombine] Fold `X!=Y ? ctz(X^Y, true) : BW -> ctz(X^Y, false)` (PR #128483)   Yingwei Zheng via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   David Sherwood via llvm-commits
• [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)   Matt Arsenault via llvm-commits
• [llvm] [LV] Restrict widest induction type to be IntegerType (NFC) (PR #128173)   David Sherwood via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [SPIRV] Stop including SPIRVInstrInfo.h in MCTargetDesc. NFC (PR #128443)   Nathan Gauër via llvm-commits
• [llvm] [llvm][ELF]Add Shdr check for getBuildID (PR #126537)   James Henderson via llvm-commits
• [llvm] [llvm][ELF]Add Shdr check for getBuildID (PR #126537)   James Henderson via llvm-commits
• [llvm] [llvm][ELF]Add Shdr check for getBuildID (PR #126537)   James Henderson via llvm-commits
• [llvm] [SPIRV] Stop including SPIRVInstrInfo.h in MCTargetDesc. NFC (PR #128443)   Vyacheslav Levytskyy via llvm-commits
• [llvm] [Loads] Support dereferenceable assumption with variable size. (PR #128436)   David Sherwood via llvm-commits
• [llvm] [Loads] Support dereferenceable assumption with variable size. (PR #128436)   Nikita Popov via llvm-commits
• [llvm] [llvm-objcopy] Let --change-section-lma change segments wth filesz=0,… (PR #127724)   James Henderson via llvm-commits
• [llvm] [llvm-objcopy] Let --change-section-lma change segments wth filesz=0,… (PR #127724)   James Henderson via llvm-commits
• [llvm] [llvm-objcopy] Let --change-section-lma change segments wth filesz=0,… (PR #127724)   James Henderson via llvm-commits
• [llvm] [llvm-objcopy] Let --change-section-lma change segments wth filesz=0,… (PR #127724)   James Henderson via llvm-commits
• [llvm] [RISCV] Remove virtual from getOutliningTypeImpl override. NFC (PR #128482)   Sudharsan Veeravalli via llvm-commits
• [llvm] 35c90bf - [RISCV] Remove virtual from getOutliningTypeImpl override. NFC (#128482)   via llvm-commits
• [llvm] [RISCV] Remove virtual from getOutliningTypeImpl override. NFC (PR #128482)   Sudharsan Veeravalli via llvm-commits
• [llvm] Handle Call Operand vxi1 in Hexagon Backend (PR #128027)   via llvm-commits
• [llvm] Correct .dynstr finding of getDynamicStrTab() (PR #127975)   James Henderson via llvm-commits
• [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)   Akshat Oke via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Ramkumar Ramachandra via llvm-commits
• [llvm] Weak linkage emulation (PR #128486)   Lang Hames via llvm-commits
• [llvm] [DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (PR #128167)   Simon Pilgrim via llvm-commits
• [llvm] 3532651 - RegAllocGreedy: Add braces   Matt Arsenault via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Florian Hahn via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Florian Hahn via llvm-commits
• [llvm] [Attributor] Do not optimize away externally_initialized loads. (PR #128170)   Nikita Popov via llvm-commits
• [llvm] [DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (PR #128167)   Simon Pilgrim via llvm-commits
• [llvm] Correct .dynstr finding of getDynamicStrTab() (PR #127975)   Ruoyu Qiu via llvm-commits
• [llvm] [AArch64][Build Attributes] Improve Parsing and Formatting (PR #126530)   via llvm-commits
• [llvm] [llvm-objdump]Correct .dynstr finding of getDynamicStrTab() (PR #127975)   Ruoyu Qiu via llvm-commits
• [llvm] [llvm-objdump]Correct .dynstr finding of getDynamicStrTab() (PR #127975)   Ruoyu Qiu via llvm-commits
• [llvm] [BOLT][binary-analysis] Add initial pac-ret gadget scanner (PR #122304)   Kristof Beyls via llvm-commits
• [llvm] [llvm][ELF]Add Shdr check for getBuildID (PR #126537)   Ruoyu Qiu via llvm-commits
• [llvm] RegAllocGreedy: Remove unnecessary null register class check (PR #128487)   Matt Arsenault via llvm-commits
• [llvm] RegAllocGreedy: Remove unnecessary null register class check (PR #128487)   Matt Arsenault via llvm-commits
• [llvm] RegAllocGreedy: Remove unnecessary null register class check (PR #128487)   via llvm-commits
• [llvm] RegAllocGreedy: Remove unnecessary null register class check (PR #128487)   Matt Arsenault via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Marina Taylor via llvm-commits
• [llvm] MachineFunction: Remove null check on TargetRegisterInfo (PR #128480)   Simon Pilgrim via llvm-commits
• [llvm] DeveloperPolicy: Update commit access requirements (PR #127006)   Jay Foad via llvm-commits
• [llvm] fixed #95641 pointless string copy (PR #127325)   Simon Pilgrim via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Ramkumar Ramachandra via llvm-commits
• [llvm] [SPIR-V] Fix generation of gMIR vs. SPIR-V code from utility methods (PR #128159)   Vyacheslav Levytskyy via llvm-commits
• [llvm] DONT_MERGE: FIXME: Revert "Revert "[X86] combineBROADCAST_LOAD - merge across chains"" (PR #128381)   Simon Pilgrim via llvm-commits
• [llvm] [llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (PR #128367)   Jay Foad via llvm-commits
• [llvm] [WIP][AMDGPU] combine uniform AMDGPU lane Intrinsics (PR #116953)   Pankaj Dwivedi via llvm-commits
• [llvm] 5a2bee0 - [llvm-objdump]Correct .dynstr finding of getDynamicStrTab() (#127975)   via llvm-commits
• [llvm] [llvm-objdump]Correct .dynstr finding of getDynamicStrTab() (PR #127975)   James Henderson via llvm-commits
• [llvm] [llvm-objdump]Correct .dynstr finding of getDynamicStrTab() (PR #127975)   James Henderson via llvm-commits
• [llvm] MachineFunction: Remove null check on TargetRegisterInfo (PR #128480)   Matt Arsenault via llvm-commits
• [llvm] [llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (PR #128367)   Matt Arsenault via llvm-commits
• [llvm] [DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (PR #128167)   Matt Arsenault via llvm-commits
• [llvm] fixed #95641 pointless string copy (PR #127325)   via llvm-commits
• [llvm] [LoopVectorize] Perform loop versioning for some early exit loops (PR #120603)   David Sherwood via llvm-commits
• [llvm] [Attributor] Do not optimize away externally_initialized loads. (PR #128170)   Pierre van Houtryve via llvm-commits
• [llvm] [LoopInterchange] Enable it by default (WIP) (PR #124911)   Sjoerd Meijer via llvm-commits
• [llvm] [LoopVectorize] Perform loop versioning for some early exit loops (PR #120603)   via llvm-commits
• [llvm] [X86] Fold AND(Y, XOR(X, SUB(0, X))) to ANDN(Y, BLSMSK(X)) (PR #128348)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Fold AND(Y, XOR(X, SUB(0, X))) to ANDN(Y, BLSMSK(X)) (PR #128348)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Fold AND(Y, XOR(X, SUB(0, X))) to ANDN(Y, BLSMSK(X)) (PR #128348)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Fold AND(Y, XOR(X, SUB(0, X))) to ANDN(Y, BLSMSK(X)) (PR #128348)   Simon Pilgrim via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Florian Hahn via llvm-commits
• [llvm] [WIP][AMDGPU] combine uniform AMDGPU lane Intrinsics (PR #116953)   Pankaj Dwivedi via llvm-commits
• [llvm] [LoopVectorize] Perform loop versioning for some early exit loops (PR #120603)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Perform loop versioning for some early exit loops (PR #120603)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Perform loop versioning for some early exit loops (PR #120603)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Perform loop versioning for some early exit loops (PR #120603)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Perform loop versioning for some early exit loops (PR #120603)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Perform loop versioning for some early exit loops (PR #120603)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Perform loop versioning for some early exit loops (PR #120603)   David Sherwood via llvm-commits
• [llvm] [AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (PR #126696)   Jay Foad via llvm-commits
• [llvm] [AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (PR #126696)   Jay Foad via llvm-commits
• [llvm] [AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (PR #126696)   Jay Foad via llvm-commits
• [llvm] [AMDGPU] combine uniform AMDGPU lane Intrinsics (PR #116953)   Pankaj Dwivedi via llvm-commits
• [llvm] [AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (PR #126696)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)   Matt Arsenault via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Simon Pilgrim via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Ash Dobrescu via llvm-commits
• [llvm] 9cbdcfc - [CaptureTracking] Remove StoreCaptures parameter (NFC)   Nikita Popov via llvm-commits
• [llvm] [LoopVectorize] Perform loop versioning for some early exit loops (PR #120603)   David Sherwood via llvm-commits
• [llvm] [VectorCombine] Handle shuffle of selects (PR #128032)   Simon Pilgrim via llvm-commits
• [llvm] [VectorCombine] Handle shuffle of selects (PR #128032)   Simon Pilgrim via llvm-commits
• [compiler-rt] [TySan] Fix false positives with derived classes (PR #126260)   via llvm-commits
• [llvm] [LV] Restrict widest induction type to be IntegerType (NFC) (PR #128173)   Ramkumar Ramachandra via llvm-commits
• [llvm] [DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (PR #128167)   Simon Pilgrim via llvm-commits
• [llvm] [DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (PR #128167)   Simon Pilgrim via llvm-commits
• [llvm] InstCombine: Remove a check for pointer bitcasts (PR #128491)   Matt Arsenault via llvm-commits
• [llvm] InstCombine: Remove a check for pointer bitcasts (PR #128491)   Matt Arsenault via llvm-commits
• [llvm] [DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (PR #128167)   Simon Pilgrim via llvm-commits
• [llvm] InstCombine: Remove a check for pointer bitcasts (PR #128491)   Matt Arsenault via llvm-commits
• [llvm] 7de6492 - [DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (#128167)   via llvm-commits
• [llvm] InstCombine: Remove a check for pointer bitcasts (PR #128491)   via llvm-commits
• [llvm] [DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (PR #128167)   Simon Pilgrim via llvm-commits
• [llvm] TargetTransformInfo: Add missing consts to a couple of methods (PR #128492)   Matt Arsenault via llvm-commits
• [llvm] TargetTransformInfo: Add missing consts to a couple of methods (PR #128492)   Matt Arsenault via llvm-commits
• [llvm] TargetTransformInfo: Add missing consts to a couple of methods (PR #128492)   Matt Arsenault via llvm-commits
• [llvm] TargetTransformInfo: Add missing consts to a couple of methods (PR #128492)   via llvm-commits
• [llvm] TargetTransformInfo: Add missing consts to a couple of methods (PR #128492)   via llvm-commits
• [llvm] MachineFunction: Remove null check on TargetRegisterInfo (PR #128480)   Simon Pilgrim via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   Jose E. Marchesi via llvm-commits
• [llvm] [Support] report_fatal_error: Do not generate crash backtrace by default (PR #128495)   Akshat Oke via llvm-commits
• [llvm] [Support] report_fatal_error: Do not generate crash backtrace by default (PR #128495)   via llvm-commits
• [llvm] [Support] report_fatal_error: Do not generate crash backtrace by default (PR #128495)   via llvm-commits
• [llvm] [Support] report_fatal_error: Do not generate crash backtrace by default (PR #128495)   via llvm-commits
• [llvm] [VPlan] Thread plan to VPBuilder (NFC) (PR #125364)   Ramkumar Ramachandra via llvm-commits
• [llvm] [Support] report_fatal_error: Do not generate crash backtrace by default (PR #128495)   Matt Arsenault via llvm-commits
• [llvm] [Support] report_fatal_error: Do not generate crash backtrace by default (PR #128495)   Matt Arsenault via llvm-commits
• [llvm] db40592 - MachineFunction: Remove null check on TargetRegisterInfo (#128480)   via llvm-commits
• [llvm] MachineFunction: Remove null check on TargetRegisterInfo (PR #128480)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] combine uniform AMDGPU lane Intrinsics (PR #116953)   Pankaj Dwivedi via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Ivan Kosarev via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Ivan Kosarev via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Ivan Kosarev via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Ivan Kosarev via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Ivan Kosarev via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Ivan Kosarev via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Ivan Kosarev via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Ivan Kosarev via llvm-commits
• [llvm] [Loads] Support dereferenceable assumption with variable size. (PR #128436)   Florian Hahn via llvm-commits
• [llvm] [Loads] Support dereferenceable assumption with variable size. (PR #128436)   Florian Hahn via llvm-commits
• [llvm] [Loads] Support dereferenceable assumption with variable size. (PR #128436)   Florian Hahn via llvm-commits
• [llvm] [SPIR-V] Stop generating StorageImageReadWithoutFormat and StorageImageWriteWithoutFormat for the Unknown image format in the OpenCL environment (PR #128497)   Vyacheslav Levytskyy via llvm-commits
• [llvm] [SPIR-V] Stop generating StorageImageReadWithoutFormat and StorageImageWriteWithoutFormat for the Unknown image format in the OpenCL environment (PR #128497)   via llvm-commits
• [llvm] [AArch64] Add cost model for REV shuffles. (PR #128498)   David Green via llvm-commits
• [llvm] [AArch64] Add cost model for REV shuffles. (PR #128498)   via llvm-commits
• [llvm] [AArch64] Add cost model for REV shuffles. (PR #128498)   via llvm-commits
• [llvm] [Loads] Support dereferenceable assumption with variable size. (PR #128436)   David Sherwood via llvm-commits
• [llvm] AMDGPU: Add amdgpu-num-agpr attribute to control AGPR allocation (PR #128034)   Matt Arsenault via llvm-commits
• [llvm] [Support] report_fatal_error: Do not generate crash backtrace by default (PR #128495)   Akshat Oke via llvm-commits
• [llvm] PeepholeOpt: Immediately check if a reg_sequence compose supports a subregister (PR #128279)   Matt Arsenault via llvm-commits
• [llvm] [Support] report_fatal_error: Do not generate crash backtrace by default (PR #128495)   Sergei Barannikov via llvm-commits
• [llvm] [Support] report_fatal_error: Do not generate crash backtrace by default (PR #128495)   James Henderson via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Frederik Harwath via llvm-commits
• [llvm] AMDGPU: Fix creating illegally typed readfirstlane in atomic optimizer (PR #128388)   Matt Arsenault via llvm-commits
• [llvm] 6aea630 - AMDGPU: Fix creating illegally typed readfirstlane in atomic optimizer (#128388)   via llvm-commits
• [llvm] AMDGPU: Fix creating illegally typed readfirstlane in atomic optimizer (PR #128388)   Matt Arsenault via llvm-commits
• [llvm] [Support] report_fatal_error: Do not generate crash backtrace by default (PR #128495)   Akshat Oke via llvm-commits
• [llvm] AMDGPU: More consistently use the fold list instead of direct mutation (PR #127612)   Matt Arsenault via llvm-commits
• [llvm] InstCombine: Remove a check for pointer bitcasts (PR #128491)   Nikita Popov via llvm-commits
• [llvm] InstCombine: Remove a check for pointer bitcasts (PR #128491)   Nikita Popov via llvm-commits
• [llvm] InstCombine: Remove a check for pointer bitcasts (PR #128491)   Nikita Popov via llvm-commits
• [llvm] InstCombine: Remove a check for pointer bitcasts (PR #128491)   Matt Arsenault via llvm-commits
• [llvm] [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (PR #128190)   Viktoria Maximova via llvm-commits
• [llvm] InstCombine: Remove a check for pointer bitcasts (PR #128491)   Matt Arsenault via llvm-commits
• [llvm] [InstCombine] Simplify nonnull phi nodes (PR #128466)   Yingwei Zheng via llvm-commits
• [llvm] [VectorCombine] Handle shuffle of selects (PR #128032)   via llvm-commits
• [llvm] [VPlan] Thread plan to VPBuilder (NFC) (PR #125364)   Ramkumar Ramachandra via llvm-commits
• [llvm] [InstrRef] Preserve debug instr num in aarch64-expand-pseudo LOADgot expansion (PR #128081)   Jeremy Morse via llvm-commits
• [llvm] [Dexter] Remove clang-opt-bisect analyzer tool (PR #128165)   Jeremy Morse via llvm-commits
• [llvm] [Support] report_fatal_error: Do not generate crash backtrace by default (PR #128495)   Akshat Oke via llvm-commits
• [llvm] TargetTransformInfo: Add missing consts to a couple of methods (PR #128492)   Sam Parker via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Marina Taylor via llvm-commits
• [llvm] [VPlan] Thread plan to VPBuilder (NFC) (PR #125364)   Ramkumar Ramachandra via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] TargetTransformInfo: Add missing consts to a couple of methods (PR #128492)   Matt Arsenault via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] 971fc42 - TargetTransformInfo: Add missing consts to a couple of methods (#128492)   via llvm-commits
• [llvm] TargetTransformInfo: Add missing consts to a couple of methods (PR #128492)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Matt Arsenault via llvm-commits
• [llvm] [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (PR #128190)   Vyacheslav Levytskyy via llvm-commits
• [llvm] [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (PR #128190)   Vyacheslav Levytskyy via llvm-commits
• [llvm] [VPlan] Introduce explicit broadcasts for live-ins. (PR #124644)   Florian Hahn via llvm-commits
• [llvm] Add support for the intrinsic @llvm.fptosi.sat.* and @llvm.fptoui.sat.* lowering (PR #126214)   Vishakh Prakash via llvm-commits
• [llvm] llvm.sadd.with.overflow intrinsic lowering to SPIRV (PR #126463)   Ebin Jose via llvm-commits
• [llvm] Added legalizer and instruction selector for @llvm.lround.* and @llvm.llround.* intrinsic (PR #126473)   Aadesh P S via llvm-commits
• [llvm] fixed #95641 pointless string copy (PR #127325)   via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Florian Hahn via llvm-commits
• [llvm] [RISCV] Correct RISCVTTIImpl::getIntImmCostInst for Zba (PR #128174)   Gergely Futo via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Pierre van Houtryve via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Pierre van Houtryve via llvm-commits
• [llvm] [DebugInfo] Merge partially matching chains of textual inclusions (PR #125780)   Vladislav Dzhidzhoev via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Matt Arsenault via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Marina Taylor via llvm-commits
• [llvm] [LV] Restrict widest induction type to be IntegerType (NFC) (PR #128173)   Florian Hahn via llvm-commits
• [llvm] [LV] Restrict widest induction type to be IntegerType (NFC) (PR #128173)   Florian Hahn via llvm-commits
• [llvm] [LV] Restrict widest induction type to be IntegerType (NFC) (PR #128173)   Florian Hahn via llvm-commits
• [llvm] Reland "[LV]: Teach LV to recursively (de)interleave." (PR #125094)   Hassnaa Hamdi via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Marina Taylor via llvm-commits
• [llvm] LiveIntervals: Use BumpPtrAllocator (PR #127057)   Matt Arsenault via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (PR #124706)   Sudharsan Veeravalli via llvm-commits
• [llvm] [DeadArgElim] fix verifier failure when changing musttail's function signature (PR #127366)   via llvm-commits
• [llvm] 0f34b65 - InstCombine: Remove a check for pointer bitcasts (#128491)   via llvm-commits
• [llvm] InstCombine: Remove a check for pointer bitcasts (PR #128491)   Matt Arsenault via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   Jonathan Thackray via llvm-commits
• [llvm] 72768d9 - [ConstraintElim] Teach checkAndReplaceCondition about samesign (#128168)   via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Florian Hahn via llvm-commits
• [llvm] [VectorCombine] Handle shuffle of selects (PR #128032)   Simon Pilgrim via llvm-commits
• [llvm] [llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (PR #128367)   Alex Voicu via llvm-commits
• [llvm] [llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (PR #128367)   Alex Voicu via llvm-commits
• [llvm] Add DISubrangeType (PR #126772)   Tom Tromey via llvm-commits
• [llvm] [ValueTracking] ComputeNumSignBitsImpl - add basic handling of BITCAST nodes (PR #127218)   Simon Pilgrim via llvm-commits
• [llvm] [CFIInstrInserter] A test showing the need to handle `cfi_escape`. (PR #128211)   Mikhail Gudim via llvm-commits
• [clang] [llvm] [AARCH64][Neon] switch to using bitcasts in arm_neon.h where appropriate (PR #127043)   Jonathan Thackray via llvm-commits
• [llvm] [SPIR-V] Stop generating StorageImageReadWithoutFormat and StorageImageWriteWithoutFormat for the Unknown image format in the OpenCL environment (PR #128497)   Vyacheslav Levytskyy via llvm-commits
• [llvm] [CFIInstrInserter] A test showing the need to handle `cfi_escape`. (PR #128211)   Mikhail Gudim via llvm-commits
• [llvm] [CFIInstrInserter] A test showing the need to handle `cfi_escape`. (PR #128211)   Mikhail Gudim via llvm-commits
• [llvm] [CFIInstrInserter] A test showing the need to handle `cfi_escape`. (PR #128211)   Mikhail Gudim via llvm-commits
• [llvm] [AMDGPU] Fix edge case of buffer OOB handling (PR #115479)   Piotr Sobczak via llvm-commits
• [llvm] [AMDGPU] Fix edge case of buffer OOB handling (PR #115479)   Piotr Sobczak via llvm-commits
• [llvm] [X86] Fix arithmetic error in extractVector (PR #128052)   Simon Pilgrim via llvm-commits
• [llvm] [mlir] [OpenMPIRBuilder] Add support for distribute constructs (PR #127816)   Sergio Afonso via llvm-commits
• [llvm] d5148f0 - [X86] Fix arithmetic error in extractVector (#128052)   via llvm-commits
• [llvm] [X86] Fix arithmetic error in extractVector (PR #128052)   Phoebe Wang via llvm-commits
• [llvm] [OpenMPIRBuilder] Add support for distribute constructs (PR #127816)   Sergio Afonso via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   Virginia Cangelosi via llvm-commits
• [llvm] Handle Call Operand vxi1 in Hexagon Backend (PR #128027)   Brian Cain via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Nikita Popov via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Hans Wennborg via llvm-commits
• [llvm] [LV] Optimize VPWidenIntOrFpInductionRecipe for known TC (PR #118828)   Hari Limaye via llvm-commits
• [llvm] [InstCombine] Simplify nonnull phi nodes (PR #128466)   Nikita Popov via llvm-commits
• [llvm] 4ba3ebe - On Windows, remove the UCRT libraries from the release script (#128378)   via llvm-commits
• [llvm] On Windows, remove the UCRT libraries from the release script (PR #128378)   Alexandre Ganea via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Hans Wennborg via llvm-commits
• [llvm] Handle Call Operand vxi1 in Hexagon Backend (PR #128027)   Alex Rønne Petersen via llvm-commits
• [llvm] DeveloperPolicy: Reword paragraph about contributing without commit access (PR #128244)   Louis Dionne via llvm-commits
• [llvm] [X86] Added support for 8 and 16bit LEA instructions (PR #122102)   Phoebe Wang via llvm-commits
• [llvm] [X86] Added support for 8 and 16bit LEA instructions (PR #122102)   Phoebe Wang via llvm-commits
• [llvm] [ConstraintElim] Teach checkAndReplaceCondition about samesign (PR #128168)   Marina Taylor via llvm-commits
• [lld] [LLD][ELF][RISCV] Handle .note.gnu.property sections for Zicfilp/Zicfiss features (PR #127193)   Kito Cheng via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Benjamin Maxwell via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   via llvm-commits
• [llvm] AMDGPU: Enable RELA for PAL target (PR #128516)   via llvm-commits
• [llvm] AMDGPU: Enable RELA for PAL target (PR #128516)   via llvm-commits
• [llvm] AMDGPU: Enable RELA for PAL target (PR #128516)   via llvm-commits
• [llvm] fixed #95641 pointless string copy (PR #127325)   via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [lld] [llvm] [LTO] Override TargetABI from module flags if present when creating T… (PR #126497)   Kito Cheng via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Matt Arsenault via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Matt Arsenault via llvm-commits
• [llvm] aa77085 - [MergeFunc] Add tests for (merging weak|linkonce)_odr functions.   Florian Hahn via llvm-commits
• [clang] [llvm] AMDGPU: Move enqueued block handling into clang (PR #128519)   Matt Arsenault via llvm-commits
• [clang] [llvm] AMDGPU: Move enqueued block handling into clang (PR #128519)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Enable RELA for PAL target (PR #128516)   Matt Arsenault via llvm-commits
• [clang] [llvm] AMDGPU: Move enqueued block handling into clang (PR #128519)   via llvm-commits
• [clang] [llvm] AMDGPU: Move enqueued block handling into clang (PR #128519)   Matt Arsenault via llvm-commits
• [llvm] [LV][EVL] Support fixed-order recurrence idiom with EVL tail folding. (PR #124093)   Alexey Bataev via llvm-commits
• [llvm] [SLP][REVEC] Fix scalar mask is passed to getScalarizationOverhead but the type is vector. (PR #128476)   Alexey Bataev via llvm-commits
• [llvm] [AArch64] Improve codegen for some fixed-width partial reductions (PR #126529)   David Green via llvm-commits
• [llvm] [SLP][REVEC] Fix scalar mask is passed to getScalarizationOverhead but the type is vector. (PR #128476)   Han-Kuan Chen via llvm-commits
• [llvm] [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (PR #128190)   Viktoria Maximova via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Alexey Bataev via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Alexey Bataev via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Alexey Bataev via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Alexey Bataev via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Alexey Bataev via llvm-commits
• [llvm] [SLP][REVEC] Fix scalar mask is passed to getScalarizationOverhead but the type is vector. (PR #128476)   Alexey Bataev via llvm-commits
• [llvm] AMDGPU: Enable RELA for PAL target (PR #128516)   Jay Foad via llvm-commits
• [llvm] AMDGPU: Enable RELA for PAL target (PR #128516)   Jay Foad via llvm-commits
• [llvm] [OpenMPIRBuilder] Add support for distribute constructs (PR #127816)   Sergio Afonso via llvm-commits
• [llvm] eb14d2a - [SLP]Fix check for matched gather node, if it is a subvector node   Alexey Bataev via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Pravin Jagtap via llvm-commits
• [llvm] [flang] Set compile definitions for flang-rt build on AIX (PR #127919)   Kelvin Li via llvm-commits
• [llvm] [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (PR #128190)   Viktoria Maximova via llvm-commits
• [llvm] [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (PR #128190)   via llvm-commits
• [llvm] [flang] Set compile definitions for flang-rt build on AIX (PR #127919)   Kelvin Li via llvm-commits
• [llvm] AMDGPU: Expand remaining system atomic operations (PR #122137)   Matt Arsenault via llvm-commits
• [llvm] [flang] Set compile definitions for flang-rt build on AIX (PR #127919)   Kelvin Li via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Alexey Bataev via llvm-commits
• [clang] [llvm] AMDGPU: Move enqueued block handling into clang (PR #128519)   Matt Arsenault via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [llvm] [VectorCombine] Handle shuffle of selects (PR #128032)   via llvm-commits
• [llvm] [VectorCombine] Handle shuffle of selects (PR #128032)   via llvm-commits
• [llvm] [SPIR-V] Stop generating StorageImageReadWithoutFormat and StorageImageWriteWithoutFormat for the Unknown image format in the OpenCL environment (PR #128497)   Steven Perron via llvm-commits
• [llvm] [AMDGPU] Update PromoteAlloca to handle GEPs with variable offset. (PR #122342)   Sumanth Gundapaneni via llvm-commits
• [llvm] Jitlink xcoff graphbuilder (PR #128524)   Henry Jiang via llvm-commits
• [llvm] Jitlink xcoff graphbuilder (PR #128524)   Henry Jiang via llvm-commits
• [llvm] [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (PR #128190)   Viktoria Maximova via llvm-commits
• [llvm] [AMDGPU] Update PromoteAlloca to handle GEPs with variable offset. (PR #122342)   via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   Teresa Johnson via llvm-commits
• [llvm] Jitlink xcoff graphbuilder (PR #128524)   via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Alexey Bataev via llvm-commits
• [llvm] RegAllocGreedy: Remove unnecessary null register class check (PR #128487)   Christudasan Devadasan via llvm-commits
• [llvm] [PPC][MC] Restore support for case-insensitive register names (PR #128525)   Nikita Popov via llvm-commits
• [llvm] DeveloperPolicy: Update commit access requirements (PR #127006)   Tom Stellard via llvm-commits
• [llvm] [PPC][MC] Restore support for case-insensitive register names (PR #128525)   via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Benjamin Maxwell via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Ana Mihajlovic via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Ana Mihajlovic via llvm-commits
• [llvm] [LV]Split store-load forward distance analysis from other checks (PR #121156)   Alexey Bataev via llvm-commits
• [llvm] [LV]Split store-load forward distance analysis from other checks (PR #121156)   Alexey Bataev via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Ana Mihajlovic via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Ana Mihajlovic via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Ana Mihajlovic via llvm-commits
• [llvm] 3a6108b - [SLP][REVEC] Fix scalar mask is passed to getScalarizationOverhead but the type is vector. (#128476)   via llvm-commits
• [llvm] [SLP][REVEC] Fix scalar mask is passed to getScalarizationOverhead but the type is vector. (PR #128476)   Han-Kuan Chen via llvm-commits
• [llvm] clang-format aliasing analysis files (PR #128526)   via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Jay Foad via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Jay Foad via llvm-commits
• [llvm] [MCA] New option to report scheduling information: -scheduling-info (PR #126703)   Julien Villette via llvm-commits
• [llvm] clang-format aliasing analysis files (PR #128526)   via llvm-commits
• [llvm] clang-format aliasing analysis files (PR #128526)   via llvm-commits
• [llvm] [ARM] Emit a warning when the hard-float ABI is enabled but can't be used. (PR #111334)   Peter Smith via llvm-commits
• [llvm] [ARM] Emit a warning when the hard-float ABI is enabled but can't be used. (PR #111334)   Peter Smith via llvm-commits
• [llvm] [ARM] Emit a warning when the hard-float ABI is enabled but can't be used. (PR #111334)   Peter Smith via llvm-commits
• [llvm] [NFC][Offload] Fix typo to output architecture (PR #128527)   Jan Patrick Lehr via llvm-commits
• [llvm] [AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (PR #126696)   Christudasan Devadasan via llvm-commits
• [llvm] [NFC][Offload] Fix typo to output architecture (PR #128527)   via llvm-commits
• [llvm] [NFC][Offload] Fix typo to output architecture (PR #128527)   Joseph Huber via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Matt Arsenault via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Matt Arsenault via llvm-commits
• [llvm] 16f9c5d - [SPIR-V] Stop generating StorageImageReadWithoutFormat and StorageImageWriteWithoutFormat for the Unknown image format in the OpenCL environment (#128497)   via llvm-commits
• [llvm] [SPIR-V] Stop generating StorageImageReadWithoutFormat and StorageImageWriteWithoutFormat for the Unknown image format in the OpenCL environment (PR #128497)   Vyacheslav Levytskyy via llvm-commits
• [llvm] 529b3d1 - [RISCV][TTI] Remove SK_Select from manual splitting in getShuffleCost   Philip Reames via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Jay Foad via llvm-commits
• [llvm] [NFC][Offload] Fix typo to output architecture (PR #128527)   Jan Patrick Lehr via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Matt Arsenault via llvm-commits
• [llvm] [MergeFuncs] Don't introduce calls to {linkonce,weak}_odr functions. (PR #125050)   Florian Hahn via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Matt Arsenault via llvm-commits
• [llvm] [MergeFuncs] Don't introduce calls to (linkonce,weak)_odr functions. (PR #125050)   Florian Hahn via llvm-commits
• [llvm] b66ec64 - RegAllocGreedy: Remove unnecessary null register class check (#128487)   via llvm-commits
• [llvm] [llvm] DLLExport public methods from SmallVector (PR #127850)   Andrew Rogers via llvm-commits
• [llvm] RegAllocGreedy: Remove unnecessary null register class check (PR #128487)   Matt Arsenault via llvm-commits
• [llvm] [MergeFuncs] Don't introduce calls to (linkonce,weak)_odr functions. (PR #125050)   Florian Hahn via llvm-commits
• [llvm] [MergeFuncs] Don't introduce calls to (linkonce,weak)_odr functions. (PR #125050)   Florian Hahn via llvm-commits
• [llvm] [CFIInstrInserter] A test showing the need to handle `cfi_escape`. (PR #128211)   Michael Maitland via llvm-commits
• [llvm] [MachineSink] Lower SplitEdgeProbabilityThreshold (PR #127666)   Guy David via llvm-commits
• [llvm] [AArch64][MC] Improve `isSImm` Diagnostic Fidelity (PR #127255)   Sam Elliott via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Benjamin Maxwell via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Pravin Jagtap via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Pravin Jagtap via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Pravin Jagtap via llvm-commits
• [llvm] 538b898 - [RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)   via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (PR #124706)   Sam Elliott via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Matt Arsenault via llvm-commits
• [clang] [llvm] [CMake][Release] Enable bolt optimization for clang on Linux (PR #128090)   Tobias Hieta via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Benjamin Maxwell via llvm-commits
• [llvm] [AMDGPU] Update PromoteAlloca to handle GEPs with variable offset. (PR #122342)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Update PromoteAlloca to handle GEPs with variable offset. (PR #122342)   Matt Arsenault via llvm-commits
• [llvm] fixed #95641 pointless string copy (PR #127325)   via llvm-commits
• [clang] [llvm] AMDGPU: Move enqueued block handling into clang (PR #128519)   Matt Arsenault via llvm-commits
• [llvm] [AArch64][MC] Improve `isSImm` Diagnostic Fidelity (PR #127255)   Oliver Stannard via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Benjamin Maxwell via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Benjamin Maxwell via llvm-commits
• [llvm] [CFIInstrInserter] A test showing the need to handle `cfi_escape`. (PR #128211)   Mikhail Gudim via llvm-commits
• [llvm] [SLP][REVEC] Add getScalarizationOverhead helper function to reduce error when REVEC is enabled. (PR #128530)   Han-Kuan Chen via llvm-commits
• [llvm] [SLP][REVEC] Add getScalarizationOverhead helper function to reduce error when REVEC is enabled. (PR #128530)   via llvm-commits
• [llvm] [SLP][REVEC] Add getScalarizationOverhead helper function to reduce error when REVEC is enabled. (PR #128530)   via llvm-commits
• [llvm] [CFIInstrInserter] A test showing the need to handle `cfi_escape`. (PR #128211)   Mikhail Gudim via llvm-commits
• [llvm] [OpenMPIRBuilder] Add support for distribute constructs (PR #127816)   Sergio Afonso via llvm-commits
• [llvm] InstSimplify: teach simplifyICmpWithConstant about samesign (PR #125899)   Ramkumar Ramachandra via llvm-commits
• [llvm] [InstSimplify] Teach simplifyICmpWithConstant about samesign (PR #125899)   Ramkumar Ramachandra via llvm-commits
• [llvm] cebb8f7 - [OpenMPIRBuilder] Add support for distribute constructs (#127816)   via llvm-commits
• [llvm] [OpenMPIRBuilder] Add support for distribute constructs (PR #127816)   Sergio Afonso via llvm-commits
• [llvm] [mlir] [MLIR][OpenMP] Host lowering of standalone distribute (PR #127817)   Sergio Afonso via llvm-commits
• [llvm] [LV] Restrict widest induction type to be IntegerType (NFC) (PR #128173)   Ramkumar Ramachandra via llvm-commits
• [llvm] [AArch64] Improve codegen for some fixed-width partial reductions (PR #126529)   Sander de Smalen via llvm-commits
• [llvm] [CodingStandard] Rework anonymous namespace section to cover visibility more broadly (PR #126775)   Rahul Joshi via llvm-commits
• [llvm] 5bddadf - [CodingStandard] Rework anonymous namespace section to cover visibility more broadly (#126775)   via llvm-commits
• [llvm] [CodingStandard] Rework anonymous namespace section to cover visibility more broadly (PR #126775)   Rahul Joshi via llvm-commits
• [llvm] [ARM] Emit a warning when the hard-float ABI is enabled but can't be used. (PR #111334)   Oliver Stannard via llvm-commits
• [llvm] [ARM] Emit a warning when the hard-float ABI is enabled but can't be used. (PR #111334)   Oliver Stannard via llvm-commits
• [llvm] [ARM] Emit a warning when the hard-float ABI is enabled but can't be used. (PR #111334)   Oliver Stannard via llvm-commits
• [llvm] [X86] Added support for 8 and 16bit LEA instructions (PR #122102)   via llvm-commits
• [llvm] [X86] Added support for 8 and 16bit LEA instructions (PR #122102)   via llvm-commits
• [llvm] [X86] Added support for 8 and 16bit LEA instructions (PR #122102)   via llvm-commits
• [llvm] [BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Matt Arsenault via llvm-commits
• [llvm] [CFIInstrInserter] A test showing the need to handle `cfi_escape`. (PR #128211)   Mikhail Gudim via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   David Blaikie via llvm-commits
• [lldb] [llvm] [llvm][telemetr]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   Vitaly Buka via llvm-commits
• [llvm] aab07d8 - fixed #95641 pointless string copy (#127325)   via llvm-commits
• [llvm] fixed #95641 pointless string copy (PR #127325)   Simon Pilgrim via llvm-commits
• [llvm] fixed #95641 pointless string copy (PR #127325)   via llvm-commits
• [llvm] Add DISubrangeType (PR #126772)   David Blaikie via llvm-commits
• [llvm] DONT_MERGE: FIXME: Revert "Revert "[X86] combineBROADCAST_LOAD - merge across chains"" (PR #128381)   Vitaly Buka via llvm-commits
• [llvm] [PPC][MC] Restore support for case-insensitive register names (PR #128525)   Lei Huang via llvm-commits
• [llvm] [CFIInstrInserter] Tests for scenarios not currently handled by `CFIInstrInserter`. (PR #128211)   Mikhail Gudim via llvm-commits
• [llvm] [LangRef] Clarify that the pointer after an object must be valid. (PR #127892)   Florian Hahn via llvm-commits
• [llvm] [BOLT] Flow conservation scores (PR #127954)   via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   via llvm-commits
• [llvm] [BOLT] Flow conservation scores (PR #127954)   via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   via llvm-commits
• [llvm] [AArch64][Build Attributes] Improve Parsing and Formatting (PR #126530)   Oliver Stannard via llvm-commits
• [llvm] [SLP][REVEC] Add getScalarizationOverhead helper function to reduce error when REVEC is enabled. (PR #128530)   Han-Kuan Chen via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [llvm] [BOLT] Flow conservation scores (PR #127954)   via llvm-commits
• [clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)   Deric Cheung via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Ana Mihajlovic via llvm-commits
• [llvm] [LangRef] Clarify that the pointer after an object must be valid. (PR #127892)   Florian Hahn via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   Florian Mayer via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Benjamin Maxwell via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Benjamin Maxwell via llvm-commits
• [llvm] [BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [clang] [llvm] [MTE] generalize overalignment / size of MTE globals (PR #121957)   Florian Mayer via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Benjamin Maxwell via llvm-commits
• [llvm] [BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [llvm] 20fd7f0 - Remove floating-point working group meeting (#128258)   via llvm-commits
• [llvm] Remove floating-point working group meeting (PR #128258)   Andy Kaylor via llvm-commits
• [llvm] [ARM] Emit a warning when the hard-float ABI is enabled but can't be used. (PR #111334)   Ralf Jung via llvm-commits
• [llvm] f1252f5 - [PPC][MC] Restore support for case-insensitive register names (#128525)   via llvm-commits
• [llvm] [PPC][MC] Restore support for case-insensitive register names (PR #128525)   Nikita Popov via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [LangRef] Clarify that the pointer after an object must be valid. (PR #127892)   Florian Hahn via llvm-commits
• [llvm] [LangRef] Clarify that the pointer after an object must be valid. (PR #127892)   Florian Hahn via llvm-commits
• [llvm] [LangRef] Clarify that the pointer after an object must be valid. (PR #127892)   Florian Hahn via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [llvm] [object][webassembly] Add support for RUNTIME_PATH to yaml2obj and obj2yaml (PR #126080)   Sam Clegg via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [llvm] cc7f22e - [object][WebAssembly] Add support for RUNTIME_PATH to yaml2obj and obj2yaml (#126080)   via llvm-commits
• [llvm] [object][webassembly] Add support for RUNTIME_PATH to yaml2obj and obj2yaml (PR #126080)   Sam Clegg via llvm-commits
• [llvm] [object][WebAssembly] Add support for RUNTIME_PATH to yaml2obj and obj2yaml (PR #126080)   Sam Clegg via llvm-commits
• [llvm] [object][WebAssembly] Add support for RUNTIME_PATH to yaml2obj and obj2yaml (PR #126080)   via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Antonio Frighetto via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Antonio Frighetto via llvm-commits
• [llvm] AMDGPU/GlobalISel: Disable LCSSA pass (PR #124297)   Petar Avramovic via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Antonio Frighetto via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   via llvm-commits
• [llvm] [SelectionDAG] Remove UnsafeFPMath check in `visitFADDForFMACombine` (PR #127770)   Andy Kaylor via llvm-commits
• [llvm] AMDGPU/GlobalISel: Disable LCSSA pass (PR #124297)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU/GlobalISel: Disable LCSSA pass (PR #124297)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU/GlobalISel: Disable LCSSA pass (PR #124297)   Matt Arsenault via llvm-commits
• [llvm] 7f6f186 - [SPIRV] Stop including SPIRVInstrInfo.h in MCTargetDesc. NFC (#128443)   via llvm-commits
• [llvm] [SPIRV] Stop including SPIRVInstrInfo.h in MCTargetDesc. NFC (PR #128443)   Craig Topper via llvm-commits
• [llvm] [RISCV] Remove unnecessary entries from RISCVVInversePseudosTable. NFC (PR #128376)   Craig Topper via llvm-commits
• [llvm] a0be17d - [RISCV] Remove unnecessary entries from RISCVVInversePseudosTable. NFC (#128376)   via llvm-commits
• [llvm] [RISCV] Remove unnecessary entries from RISCVVInversePseudosTable. NFC (PR #128376)   Craig Topper via llvm-commits
• [llvm] [ARM] Emit a warning when the hard-float ABI is enabled but can't be used. (PR #111334)   Oliver Stannard via llvm-commits
• [llvm] [BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   Benjamin Maxwell via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Farzon Lotfi via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [Asan] Provide TTI hook to provide memory reference infromation of ta… (PR #127753)   Min-Yih Hsu via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Ali Raeisdanaei via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Farzon Lotfi via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [RISCV] Correct RISCVTTIImpl::getIntImmCostInst for Zba (PR #128174)   Craig Topper via llvm-commits
• [llvm] [Asan] Provide TTI hook to provide memory reference infromation of ta… (PR #127753)   Matt Arsenault via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   Thurston Dang via llvm-commits
• [llvm] 571b787 - [CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)   via llvm-commits
• [llvm] [CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (PR #128473)   Craig Topper via llvm-commits
• [llvm] [CFIInstrInserter] Tests for scenarios not currently handled by `CFIInstrInserter`. (PR #128211)   Michael Maitland via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Ali Raeisdanaei via llvm-commits
• [clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)   Deric Cheung via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Ali Raeisdanaei via llvm-commits
• [llvm] [AArch64][Build Attributes] Improve Parsing and Formatting (PR #126530)   via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Craig Topper via llvm-commits
• [llvm] [AArch64][MC] Improve `isSImm` Diagnostic Fidelity (PR #127255)   Sam Elliott via llvm-commits
• [llvm] [AArch64][MC] Improve `isSImm` Diagnostic Fidelity (PR #127255)   Sam Elliott via llvm-commits
• [llvm] [AArch64][Build Attributes] Improve Parsing and Formatting (PR #126530)   via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] [AArch64] Add cost model for REV shuffles. (PR #128498)   Benjamin Maxwell via llvm-commits
• [llvm] [AArch64] Improve urem by constant costs (PR #122236)   David Green via llvm-commits
• [llvm] [AArch64] Improve urem by constant costs (PR #122236)   David Green via llvm-commits
• [llvm] [SLP][REVEC] Add getScalarizationOverhead helper function to reduce error when REVEC is enabled. (PR #128530)   Alexey Bataev via llvm-commits
• [llvm] Add DISubrangeType (PR #126772)   Tom Tromey via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] e298fc2 - Add DISubrangeType (#126772)   via llvm-commits
• [llvm] Obviously Redundant Assert In AsmWriter (PR #128543)   JP Hafer via llvm-commits
• [llvm] d9d1f24 - [gn build] Port d0e37d972331 (llvm-dap tweaks)   Nico Weber via llvm-commits
• [llvm] Obviously Redundant Assert In AsmWriter (PR #128543)   via llvm-commits
• [llvm] 9638d08 - [NVPTX] Support for memory orderings for cmpxchg (#126159)   via llvm-commits
• [llvm] [NVPTX] Support for memory orderings for cmpxchg (PR #126159)   Akshay Deodhar via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] Obviously Redundant Assert In AsmWriter (PR #128543)   via llvm-commits
• [llvm] [AArch64][Build Attributes] Improve Parsing and Formatting (PR #126530)   via llvm-commits
• [llvm] [Dexter] Normalise the "tools directory" into a list of tools (PR #128544)   Jeremy Morse via llvm-commits
• [llvm] [OpenMP] Replace most GPU helpers with ones from <gpuintrin.h> (PR #125771)   Jon Chesterfield via llvm-commits
• [llvm] [OpenMP] Replace most GPU helpers with ones from <gpuintrin.h> (PR #125771)   Jon Chesterfield via llvm-commits
• [llvm] [OpenMP] Replace most GPU helpers with ones from <gpuintrin.h> (PR #125771)   Jon Chesterfield via llvm-commits
• [llvm] [OpenMP] Replace most GPU helpers with ones from <gpuintrin.h> (PR #125771)   Jon Chesterfield via llvm-commits
• [llvm] [Dexter] Normalise the "tools directory" into a list of tools (PR #128544)   via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   via llvm-commits
• [clang] [llvm] workflows/release-binaries: Enable Windows x86 builds (PR #128274)   Tom Stellard via llvm-commits
• [llvm] [NVPTX] Switch to imm offset variants for LDG and LDU (PR #128270)   Artem Belevich via llvm-commits
• [llvm] [NVPTX] Switch to imm offset variants for LDG and LDU (PR #128270)   Artem Belevich via llvm-commits
• [llvm] [NVPTX] Switch to imm offset variants for LDG and LDU (PR #128270)   Artem Belevich via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Mircea Trofin via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Ali Raeisdanaei via llvm-commits
• [llvm] d9b0571 - [gn build] Port 363bfd6090b0   LLVM GN Syncbot via llvm-commits
• [llvm] 41cd6d2 - [gn build] Port 850b49297615   LLVM GN Syncbot via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Mircea Trofin via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Ali Raeisdanaei via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Ali Raeisdanaei via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [clang] [llvm] workflows/release-binaries: Enable Windows x86 builds (PR #128274)   Tom Stellard via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Artem Belevich via llvm-commits
• [llvm] [Asan] Provide TTI hook to provide memory reference infromation of ta… (PR #127753)   Craig Topper via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Mircea Trofin via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Mircea Trofin via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Ali Raeisdanaei via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Ali Raeisdanaei via llvm-commits
• [clang] [llvm] [LLVM][Triple][NFCI] Add function to test for offloading triples (PR #126956)   Nick Sarnie via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Eli Friedman via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Mircea Trofin via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Farzon Lotfi via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Pengcheng Wang via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Deric Cheung via llvm-commits
• [llvm] [BOLT] Enable hugify for AArch64 (PR #117158)   Pavel Iliin via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] 4ac43b5 - [LV] Restrict widest induction type to be IntegerType (NFC) (#128173)   via llvm-commits
• [llvm] [LV] Restrict widest induction type to be IntegerType (NFC) (PR #128173)   Ramkumar Ramachandra via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Reid Kleckner via llvm-commits
• [llvm] [SystemZ] Drop regstate of SELRMux operand in selectSLRMux(). (PR #128555)   Jonas Paulsson via llvm-commits
• [llvm] [SystemZ] Drop regstate of SELRMux operand in selectSLRMux(). (PR #128555)   via llvm-commits
• [llvm] [DirectX] Fix build breaks (PR #128556)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] Fix build breaks (PR #128556)   via llvm-commits
• [llvm] [DirectX] Fix build breaks (PR #128556)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] Fix build breaks (PR #128556)   via llvm-commits
• [llvm] [DirectX] Fix build breaks (PR #128556)   Damyan Pepper via llvm-commits
• [llvm] [DirectX] Fix build breaks (PR #128556)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] Fix build breaks (PR #128556)   Farzon Lotfi via llvm-commits
• [llvm] [BOLT][binary-analysis] Add initial pac-ret gadget scanner (PR #122304)   Alan Zhao via llvm-commits
• [llvm] [DirectX] Fix build breaks (PR #128556)   Damyan Pepper via llvm-commits
• [llvm] [BOLT][binary-analysis] Add initial pac-ret gadget scanner (PR #122304)   LLVM Continuous Integration via llvm-commits
• [llvm] Handle Call Operand vxi1 in Hexagon Backend (PR #128027)   Brian Cain via llvm-commits
• [llvm] Handle Call Operand vxi1 in Hexagon Backend (PR #128027)   Brian Cain via llvm-commits
• [llvm] [DirectX] Fix build breaks (PR #128556)   Justin Bogner via llvm-commits
• [llvm] [DirectX] Fix build breaks (PR #128556)   Farzon Lotfi via llvm-commits
• [llvm] 4c9e14b - [AMDGPU] Update PromoteAlloca to handle GEPs with variable offset. (#122342)   via llvm-commits
• [llvm] [AMDGPU] Update PromoteAlloca to handle GEPs with variable offset. (PR #122342)   Sumanth Gundapaneni via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Aiden Grossman via llvm-commits
• [llvm] Refactored verbosity flag in mlgo-utils to common location #107898 (PR #128541)   Aiden Grossman via llvm-commits
• [llvm] [llvm-ifs] Handle more e_machine values for --target (PR #128559)   Roland McGrath via llvm-commits
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• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Durgadoss R via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Alexey Bataev via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Alexey Bataev via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Alexey Bataev via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Alexey Bataev via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Alexey Bataev via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Alexey Bataev via llvm-commits
• [llvm] [flang-rt] Make `FLANG_RT_INSTALL_RESOURCE_PATH` configurable (PR #128561)   Michał Górny via llvm-commits
• [llvm] Handle Call Operand vxi1 in Hexagon Backend (PR #128027)   Ikhlas Ajbar via llvm-commits
• [llvm] [BOLT][binary-analysis] Add initial pac-ret gadget scanner (PR #122304)   Kristof Beyls via llvm-commits
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• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
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• [llvm] e55f1a7 - [SLP] Add test for getSpillCost fix   Mikhail R. Gadelha via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Durgadoss R via llvm-commits
• [compiler-rt] [ASan][Windows] Honor asan config flags on windows when set through the user function (PR #122990)   David Justo via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
• [llvm] [BOLT][binary-analysis] Add initial pac-ret gadget scanner (PR #122304)   LLVM Continuous Integration via llvm-commits
• [llvm] [BOLT][binary-analysis] Add initial pac-ret gadget scanner (PR #122304)   LLVM Continuous Integration via llvm-commits
• [llvm] [AMDGPU] Restrict promote alloca on pointers across address spaces (PR #119762)   Sumanth Gundapaneni via llvm-commits
• [llvm] [BOLT][binary-analysis] Add initial pac-ret gadget scanner (PR #122304)   LLVM Continuous Integration via llvm-commits
• [llvm] [BOLT] pacret-scanner: fix regression tests... (PR #128565)   Kristof Beyls via llvm-commits
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• [llvm] [WebAssembly] Make llvm.wasm.throw invokable (PR #128104)   Derek Schuff via llvm-commits
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• [llvm] [BOLT] pacret-scanner: fix regression tests... (PR #128565)   Kristof Beyls via llvm-commits
• [llvm] [BOLT] pacret-scanner: fix regression tests... (PR #128565)   Kristof Beyls via llvm-commits
• [llvm] [BOLT][binary-analysis] Add initial pac-ret gadget scanner (PR #122304)   Kristof Beyls via llvm-commits
• [llvm] [CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (PR #126807)   Eli Friedman via llvm-commits
• [flang] [llvm] [FLANG][OpenMP]Add frontend support for ASSUME and ASSUMES (PR #120770)   Krzysztof Parzyszek via llvm-commits
• [llvm] b335d5a - [gn build] Port 988480323d5e   LLVM GN Syncbot via llvm-commits
• [lld] [lld][WebAssembly] Allow linker-synthetic symbols to be undefined when building shared libraries (PR #128223)   Derek Schuff via llvm-commits
• [lld] [lld][WebAssembly] Allow linker-synthetic symbols to be undefined when building shared libraries (PR #128223)   Derek Schuff via llvm-commits
• [llvm] [LangRef] Document accessing memory outside of object is UB. (PR #128429)   Eli Friedman via llvm-commits
• [llvm] spill 16 with scratch load/store (PR #128060)   Brox Chen via llvm-commits
• [flang] [llvm] [FLANG][OpenMP]Add frontend support for ASSUME and ASSUMES (PR #120770)   Krzysztof Parzyszek via llvm-commits
• [llvm] [llvm-ifs] Handle more e_machine values for --target (PR #128559)   Saleem Abdulrasool via llvm-commits
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• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Brox Chen via llvm-commits
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• [llvm] [BPF] Report Unreachable Behavior from IR (PR #126858)   Eli Friedman via llvm-commits
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• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   Vitaly Buka via llvm-commits
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• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   Vitaly Buka via llvm-commits
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• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   LLVM Continuous Integration via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   LLVM Continuous Integration via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   LLVM Continuous Integration via llvm-commits
• [llvm] TRY:Reapply "[llvm-mt] Use XmlDeleter to free xmlFreeDoc" (PR #128575)   Vitaly Buka via llvm-commits
• [llvm] [llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (PR #128367)   Alex Voicu via llvm-commits
• [llvm] TRY:Reapply "[llvm-mt] Use XmlDeleter to free xmlFreeDoc" (PR #128575)   Vitaly Buka via llvm-commits
• [llvm] TRY Revert "[llvm-mt] Use XmlDeleter to free xmlFreeDoc" (PR #128563)   Vitaly Buka via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   LLVM Continuous Integration via llvm-commits
• [llvm] TRY:Reapply "[llvm-mt] Use XmlDeleter to free xmlFreeDoc" (PR #128575)   Vitaly Buka via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   LLVM Continuous Integration via llvm-commits
• [llvm] 23aca2f - Revert "Symbolize line zero as if no source info is available (#124846)"   Zequan Wu via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   LLVM Continuous Integration via llvm-commits
• [llvm] [BOLT] pacret-scanner: fix regression test failure (PR #128576)   Kristof Beyls via llvm-commits
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• [llvm] Revert "[llvm-mt] Use XmlDeleter to free xmlFreeDoc" (PR #128578)   Vitaly Buka via llvm-commits
• [llvm] e063365 - Revert "[llvm-mt] Use XmlDeleter to free xmlFreeDoc" (#128578)   via llvm-commits
• [llvm] Revert "[llvm-mt] Use XmlDeleter to free xmlFreeDoc" (PR #128578)   Vitaly Buka via llvm-commits
• [llvm] [BOLT] pacret-scanner: fix regression tests... (PR #128565)   Kristof Beyls via llvm-commits
• [llvm] Revert "Revert "[llvm-mt] Use XmlDeleter to free xmlFreeDoc"" (PR #128579)   Vitaly Buka via llvm-commits
• [llvm] [BOLT] pacret-scanner: fix regression test failure (PR #128576)   Kristof Beyls via llvm-commits
• [llvm] [BOLT] pacret-scanner: fix regression test failure (PR #128576)   Alan Zhao via llvm-commits
• [llvm] [Hexagon] Add a case to BitTracker for new register class (PR #128580)   Ikhlas Ajbar via llvm-commits
• [llvm] [Hexagon] Add a case to BitTracker for new register class (PR #128580)   via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
• [llvm] [Hexagon] Add a case to BitTracker for new register class (PR #128580)   Ikhlas Ajbar via llvm-commits
• [libc] [llvm] [libc] Remove special full build handling for GPU (PR #128572)   Jon Chesterfield via llvm-commits
• [llvm] [Hexagon] Add a case to BitTracker for new register class (PR #128580)   via llvm-commits
• [llvm] [Hexagon] Add a case to BitTracker for new register class (PR #128580)   Brian Cain via llvm-commits
• [libc] [llvm] [libc] Remove special full build handling for GPU (PR #128572)   via llvm-commits
• [libc] [llvm] [libc] Remove special full build handling for GPU (PR #128572)   Joseph Huber via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] 47822c8 - [LangRef] Clarify that the pointer after an object must be valid. (#127892)   via llvm-commits
• [llvm] [LangRef] Clarify that the pointer after an object must be valid. (PR #127892)   Florian Hahn via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [Loads] Support dereferenceable assumption with variable size. (PR #128436)   Florian Hahn via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Brox Chen via llvm-commits
• [llvm] Revert "Revert "[llvm-mt] Use XmlDeleter to free xmlFreeDoc"" (PR #128579)   Vitaly Buka via llvm-commits
• [llvm] Reland "[llvm-mt] Use XmlDeleter to free xmlFreeDoc"" (PR #128579)   Vitaly Buka via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Brox Chen via llvm-commits
• [llvm] [RISCV] Merge Xqci Decoder Tables (PR #128140)   Sam Elliott via llvm-commits
• [libc] [llvm] [libc] Remove special full build handling for GPU (PR #128572)   via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   Vitaly Buka via llvm-commits
• [libc] [llvm] [libc] Remove special full build handling for GPU (PR #128572)   Joseph Huber via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   Sander de Smalen via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   Sander de Smalen via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   Sander de Smalen via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   Sander de Smalen via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   Sander de Smalen via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   Sander de Smalen via llvm-commits
• [libc] [llvm] [libc] Remove special full build handling for GPU (PR #128572)   via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   via llvm-commits
• [llvm] [llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (PR #128367)   Alex Voicu via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [libc] [llvm] [libc] Remove special full build handling for GPU (PR #128572)   Joseph Huber via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] a018788 - [gn build] Port d36231940444   LLVM GN Syncbot via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   Paul T Robinson via llvm-commits
• [llvm] df14dbd - [DirectX] Fix build breaks (#128556)   via llvm-commits
• [llvm] [DirectX] Fix build breaks (PR #128556)   Farzon Lotfi via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   via llvm-commits
• [libc] [llvm] [libc] Remove special full build handling for GPU (PR #128572)   Joseph Huber via llvm-commits
• [llvm] baa77e3 - [LV] Remove some redundant casts (NFC).   Florian Hahn via llvm-commits
• [libc] [llvm] [libc] Remove special full build handling for GPU (PR #128572)   via llvm-commits
• [libc] [llvm] [libc] Remove special full build handling for GPU (PR #128572)   via llvm-commits
• [llvm] [Loads] Support dereferenceable assumption with variable size. (PR #128436)   Florian Hahn via llvm-commits
• [llvm] eabe2eb - [libc] Remove special full build handling for GPU (#128572)   via llvm-commits
• [libc] [llvm] [libc] Remove special full build handling for GPU (PR #128572)   Joseph Huber via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   Maksim Panchenko via llvm-commits
• [llvm] [RFC][BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [RISCV] Correctly Decode Unsigned Immediates with Ranges (PR #128584)   Sam Elliott via llvm-commits
• [llvm] [Aarch64] [ISel] Don't save vaargs registers if vaargs are unused (PR #126780)   Eli Friedman via llvm-commits
• [llvm] [RISCV] Correctly Decode Unsigned Immediates with Ranges (PR #128584)   via llvm-commits
• [llvm] [RISCV] Correctly Decode Unsigned Immediates with Ranges (PR #128584)   via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [clang] [libc] [lld] [llvm] Ugly example of building libc to spirv (PR #128585)   Jon Chesterfield via llvm-commits
• [llvm] [RFC][BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [clang] [libc] [lld] [llvm] Ugly example of building libc to spirv (PR #128585)   via llvm-commits
• [clang] [libc] [lld] [llvm] Ugly example of building libc to spirv (PR #128585)   via llvm-commits
• [clang] [libc] [lld] [llvm] Ugly example of building libc to spirv (PR #128585)   via llvm-commits
• [clang] [libc] [lld] [llvm] Ugly example of building libc to spirv (PR #128585)   via llvm-commits
• [llvm] b248817 - [gn build] Port 38d7cf1a8143   LLVM GN Syncbot via llvm-commits
• [lld] [llvm] [CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (PR #126880)   Eli Friedman via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   Paul T Robinson via llvm-commits
• [clang] [libc] [lld] [llvm] Ugly example of building libc to spirv (PR #128585)   via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   Paul T Robinson via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   Maksim Panchenko via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [PPC] Implement `areInlineCompatible` (PR #126562)   Henry Jiang via llvm-commits
• [llvm] [PPC] Implement `areInlineCompatible` (PR #126562)   Henry Jiang via llvm-commits
• [llvm] [RISCV] Correctly Decode Unsigned Immediates with Ranges (PR #128584)   Craig Topper via llvm-commits
• [llvm] [RFC][BPF] Report Unreachable Behavior from IR (PR #126858)   Eli Friedman via llvm-commits
• [llvm] 6b44427 - Reland "[llvm-mt] Use XmlDeleter to free xmlFreeDoc"" (#128579)   via llvm-commits
• [llvm] Reland "[llvm-mt] Use XmlDeleter to free xmlFreeDoc"" (PR #128579)   Vitaly Buka via llvm-commits
• [llvm] TRY Revert "[llvm-mt] Use XmlDeleter to free xmlFreeDoc" (PR #128563)   Vitaly Buka via llvm-commits
• [llvm] TRY:Reapply "[llvm-mt] Use XmlDeleter to free xmlFreeDoc" (PR #128575)   Vitaly Buka via llvm-commits
• [llvm] [LoongArch] Add machine function pass to merge base + offset (PR #101139)   LLVM Continuous Integration via llvm-commits
• [clang] [llvm] Reapply "Reland "[HLSL] Implement the `reflect` HLSL function"" (#124046) (PR #128386)   Vitaly Buka via llvm-commits
• [llvm] [ConstraintElim] Preserve analyses when IR is unchanged. (PR #128588)   Andreas Jonson via llvm-commits
• [llvm] [VPlan] Use VPlan predecessors in VPWidenPHIRecipe (NFC). (PR #126388)   Florian Hahn via llvm-commits
• [llvm] [ConstraintElim] Preserve analyses when IR is unchanged. (PR #128588)   via llvm-commits
• [llvm] [VPlan] Use VPlan predecessors in VPWidenPHIRecipe (NFC). (PR #126388)   Florian Hahn via llvm-commits
• [clang] [llvm] [Hexagon] Set the default compilation target to V68 (PR #125239)   Ikhlas Ajbar via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   Greg Clayton via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   Jose E. Marchesi via llvm-commits
• [llvm] [ConstraintElim] Preserve analyses when IR is unchanged. (PR #128588)   Florian Hahn via llvm-commits
• [llvm] [PPC] Implement `areInlineCompatible` (PR #126562)   Hubert Tong via llvm-commits
• [clang] [clang-tools-extra] [llvm] [clangd][WIP] Add doxygen parsing using standalone doxygen parser (PR #128591)   via llvm-commits
• [clang] [clang-tools-extra] [llvm] [clangd][WIP] Add doxygen parsing using standalone doxygen parser (PR #128591)   via llvm-commits
• [clang-tools-extra] [llvm] [clangd][WIP] Add doxygen parsing for Hover (PR #127451)   via llvm-commits
• [clang-tools-extra] [llvm] [clangd][WIP] Add doxygen parsing for Hover (PR #127451)   via llvm-commits
• [llvm] 6d0cfbc - [PPC] Implement `areInlineCompatible` (#126562)   via llvm-commits
• [llvm] [PPC] Implement `areInlineCompatible` (PR #126562)   Henry Jiang via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Craig Topper via llvm-commits
• [llvm] [JumpThreading] Remove deleted BB from Unreachable (PR #126984)   via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   LLVM Continuous Integration via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   Brox Chen via llvm-commits
• [llvm] 305d273 - Reland "[HLSL] Implement the reflect HLSL function" (#125599)   via llvm-commits
• [clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)   Deric Cheung via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   Ali Raeisdanaei via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   via llvm-commits
• [llvm] [SandboxVec][Scheduler] Enforce scheduling SchedBundle instrs back-to-back (PR #128092)   via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   Ali Raeisdanaei via llvm-commits
• [llvm] [SandboxVec][Scheduler] Enforce scheduling SchedBundle instrs back-to-back (PR #128092)   via llvm-commits
• [clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)   LLVM Continuous Integration via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   Ali Raeisdanaei via llvm-commits
• [llvm] [SLP][REVEC] Add getScalarizationOverhead helper function to reduce error when REVEC is enabled. (PR #128530)   Han-Kuan Chen via llvm-commits
• [llvm] [llvm-dwarfdump] Make --verify for .debug_names multithreaded. (PR #127281)   Alexander Yermolovich via llvm-commits
• [llvm] [llvm-dwarfdump] Make --verify for .debug_names multithreaded. (PR #127281)   Alexander Yermolovich via llvm-commits
• [llvm] [llvm-dwarfdump] Make --verify for .debug_names multithreaded. (PR #127281)   Alexander Yermolovich via llvm-commits
• [llvm] [llvm-dwarfdump] Make --verify for .debug_names multithreaded. (PR #127281)   Alexander Yermolovich via llvm-commits
• [llvm] [llvm-dwarfdump] Make --verify for .debug_names multithreaded. (PR #127281)   Alexander Yermolovich via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   via llvm-commits
• [llvm] [X86] Added support for 8 and 16bit LEA instructions (PR #122102)   Phoebe Wang via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] [FlattenCFG] Fix an Imprecise Usage of AA (PR #128117)   via llvm-commits
• [llvm] [FlattenCFG] Fix an Imprecise Usage of AA (PR #128117)   via llvm-commits
• [llvm] [FlattenCFG] Fix an Imprecise Usage of AA (PR #128117)   via llvm-commits
• [llvm] [llvm-mt] Use XmlDeleter to free xmlFreeDoc (PR #128472)   LLVM Continuous Integration via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [X86][NFC] Added/Updated Trigonometric functions testcases (PR #127094)   Evgenii Kudriashov via llvm-commits
• [llvm] [NVPTX] Switch to imm offset variants for LDG and LDU (PR #128270)   Alex MacLean via llvm-commits
• [llvm] [AA] Move Target Specific AA before BasicAA (PR #125965)   via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   Ellis Hoag via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   Ellis Hoag via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   via llvm-commits
• [llvm] [AA] Move Target Specific AA before BasicAA (PR #125965)   via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] [SelectionDAG] Remove UnsafeFPMath check in `visitFADDForFMACombine` (PR #127770)   via llvm-commits
• [llvm] Update GettingStarted.rst (PR #128616)   via llvm-commits
• [llvm] Update GettingStarted.rst (PR #128616)   via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] [NVPTX] Switch to imm offset variants for LDG and LDU (PR #128270)   Artem Belevich via llvm-commits
• [llvm] Introduce CovMap in ObjectYAML (PR #127432)   Jessica Paquette via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Matt Arsenault via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] [WebAssembly] Use the same lowerings for f16x8 as other float vectors. (PR #127897)   Brendan Dahl via llvm-commits
• [llvm] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (PR #128618)   Yingwei Zheng via llvm-commits
• [llvm] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (PR #128618)   via llvm-commits
• [clang] [libc] [lld] [llvm] Ugly example of building libc to spirv (PR #128585)   Farzon Lotfi via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   Zequan Wu via llvm-commits
• [llvm] Weak linkage emulation (PR #128486)   Lang Hames via llvm-commits
• [llvm] 6880644 - [ORC] Remove unused header. NFC.   Lang Hames via llvm-commits
• [llvm] 253e116 - [ORC][llvm-jitlink] Add support for emulating ld64 -weak-lx / -weak_library.   Lang Hames via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   Zequan Wu via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] [RISCV][NFC] Merge Xqci Decoder Tables (PR #128140)   Sam Elliott via llvm-commits
• [clang] [libc] [lld] [llvm] Ugly example of building libc to spirv (PR #128585)   Joseph Huber via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Mikhail R. Gadelha via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Mikhail R. Gadelha via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] [Hexagon] Add a case to BitTracker for new register class (PR #128580)   Ikhlas Ajbar via llvm-commits
• [llvm] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (PR #128618)   Yingwei Zheng via llvm-commits
• [llvm] [VP][RISCV][WIP] Add a vp.load.ff intrinsic for fault only first load. (PR #128593)   Pengcheng Wang via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] [RISCV] Correctly Decode Unsigned Immediates with Ranges (PR #128584)   Sam Elliott via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   Ali Raeisdanaei via llvm-commits
• [llvm] [RISCV] Correctly Decode Unsigned Immediates with Ranges (PR #128584)   Sam Elliott via llvm-commits
• [llvm] [MachinePipeliner] Fix loop-carried dependencies analysis (PR #121907)   Ikhlas Ajbar via llvm-commits
• [llvm] [ORC] Add LoadRelocatableObject: universal binary support, clearer er… (PR #104406)   LLVM Continuous Integration via llvm-commits
• [llvm] [RISCV] Correctly Decode Unsigned Immediates with Ranges (PR #128584)   Craig Topper via llvm-commits
• [llvm] [RISCV] Correctly Decode Unsigned Immediates with Ranges (PR #128584)   Craig Topper via llvm-commits
• [llvm] Add DISubrangeType (PR #126772)   LLVM Continuous Integration via llvm-commits
• [llvm] [JITLink][XCOFF] Setup initial build support for XCOFF (PR #127266)   Henry Jiang via llvm-commits
• [llvm] [JITLink][XCOFF] Setup initial build support for XCOFF (PR #127266)   via llvm-commits
• [llvm] 06f3079 - AMDGPU: More consistently use the fold list instead of direct mutation (#127612)   via llvm-commits
• [llvm] AMDGPU: More consistently use the fold list instead of direct mutation (PR #127612)   Matt Arsenault via llvm-commits
• [llvm] [BOLT] pacret-scanner: fix regression test failure (PR #128576)   Maksim Panchenko via llvm-commits
• [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)   Akshat Oke via llvm-commits
• [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)   Matt Arsenault via llvm-commits
• [llvm] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (PR #128618)   Matt Arsenault via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Heejin Ahn via llvm-commits
• [llvm] [RISCV][NFC] Merge Xqci Decoder Tables (PR #128140)   via llvm-commits
• [llvm] [SystemZ] Handle scalar to vector bitcasts. (PR #128628)   Jonas Paulsson via llvm-commits
• [llvm] [SystemZ] Handle scalar to vector bitcasts. (PR #128628)   via llvm-commits
• [llvm] [AsmParser] Avoid repeated map lookups (NFC) (PR #128629)   Kazu Hirata via llvm-commits
• [llvm] [AsmPrinter] Avoid repeated hash lookups (NFC) (PR #128630)   Kazu Hirata via llvm-commits
• [llvm] [AsmPrinter] Avoid repeated hash lookups (NFC) (PR #128630)   via llvm-commits
• [llvm] [CodeGen] Avoid repeated hash lookups (NFC) (PR #128631)   Kazu Hirata via llvm-commits
• [llvm] [DebugInfo] Avoid repeated hash lookups (NFC) (PR #128632)   Kazu Hirata via llvm-commits
• [llvm] [GlobalISel] Avoid repeated hash lookups (NFC) (PR #128633)   Kazu Hirata via llvm-commits
• [llvm] [DebugInfo] Avoid repeated hash lookups (NFC) (PR #128632)   via llvm-commits
• [llvm] [Utils] Avoid repeated hash lookups (NFC) (PR #128634)   Kazu Hirata via llvm-commits
• [llvm] [GlobalISel] Avoid repeated hash lookups (NFC) (PR #128633)   via llvm-commits
• [llvm] [Utils] Avoid repeated hash lookups (NFC) (PR #128634)   via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Maksim Panchenko via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Maksim Panchenko via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Maksim Panchenko via llvm-commits
• [llvm] [RISCV] Use addiw for or_is_add when or input is sign extended. (PR #128635)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Hank Chang via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   via llvm-commits
• [llvm] [GlobalISel] Avoid repeated hash lookups (NFC) (PR #128633)   Matt Arsenault via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [llvm] 5deb2aa - AMDGPU: Make is.shared and is.private propagate poison (#128617)   via llvm-commits
• [llvm] AMDGPU: Make is.shared and is.private propagate poison (PR #128617)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen][NewPM] Port MachineCycleInfo to NPM (PR #114745)   Akshat Oke via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   Akshat Oke via llvm-commits
• [llvm] d85685e - [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128471)   via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   Akshat Oke via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [llvm] [RFC][BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [llvm] [RISCV] Tune flag for fast vrgather.vv (PR #124664)   Petr Penzin via llvm-commits
• [llvm] [RISCV] Tune flag for fast vrgather.vv (PR #124664)   Petr Penzin via llvm-commits
• [llvm] [RISCV] Tune flag for fast vrgather.vv (PR #124664)   Petr Penzin via llvm-commits
• [clang] [llvm] [ThinLTO] Support dead RTTI data elimination under -fno-split-lto-unit (PR #126336)   via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   Matt Arsenault via llvm-commits
• [clang] [llvm] [ThinLTO] Support dead RTTI data elimination under -fno-split-lto-unit (PR #126336)   via llvm-commits
• [clang] [lldb] [llvm] Extending LLDB to work on AIX (PR #102601)   via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Hank Chang via llvm-commits
• [llvm] [AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (PR #126696)   Vikash Gupta via llvm-commits
• [llvm] [LLVM-Reduce] - Distinct Metadata Reduction (PR #104624)   LLVM Continuous Integration via llvm-commits
• [llvm] e67cd15 - [llvm-size] Initialize Radix to correct value (#128447)   Vitaly Buka via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [llvm] 9b298a1 - [WebAssembly] Use Register instead of unsigned. NFC   Craig Topper via llvm-commits
• [llvm] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (PR #128618)   Yingwei Zheng via llvm-commits
• [llvm] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (PR #128618)   Yingwei Zheng via llvm-commits
• [llvm] AMDGPU: Add baseline tests for simplify elts of readfirstlane (PR #128645)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Add baseline tests for simplify elts of readfirstlane (PR #128645)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Add baseline tests for simplify elts of readfirstlane (PR #128645)   via llvm-commits
• [llvm] AMDGPU: Add baseline tests for simplify elts of readfirstlane (PR #128645)   Matt Arsenault via llvm-commits
• [llvm] [LV][EVL] Generate negative strided load/store for reversed load/store (PR #123608)   Pengcheng Wang via llvm-commits
• [clang] [llvm] [alpha.webkit.UnretainedLambdaCapturesChecker] Add a WebKit checker for lambda capturing NS or CF types. (PR #128651)   Ryosuke Niwa via llvm-commits
• [lld] [llvm] [CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (PR #126880)   Michał Górny via llvm-commits
• [clang] [llvm] [alpha.webkit.UnretainedLambdaCapturesChecker] Add a WebKit checker for lambda capturing NS or CF types. (PR #128651)   via llvm-commits
• [llvm] [RISCV] Tune flag for fast vrgather.vv (PR #124664)   Pengcheng Wang via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Abhishek Kaushik via llvm-commits
• [llvm] PeepholeOpt: Immediately check if a reg_sequence compose supports a subregister (PR #128279)   Matt Arsenault via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [clang] [llvm] [alpha.webkit.UnretainedLambdaCapturesChecker] Add a WebKit checker for lambda capturing NS or CF types. (PR #128651)   via llvm-commits
• [llvm] [WebAssembly] Make llvm.wasm.throw invokable (PR #128104)   Heejin Ahn via llvm-commits
• [clang] [llvm] [alpha.webkit.UnretainedLambdaCapturesChecker] Add a WebKit checker for lambda capturing NS or CF types. (PR #128651)   Ryosuke Niwa via llvm-commits
• [llvm] [AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (PR #126696)   Pravin Jagtap via llvm-commits
• [llvm] AMDGPU: Add baseline tests for simplify elts of readfirstlane (PR #128645)   Pravin Jagtap via llvm-commits
• [llvm] AMDGPU: Add baseline tests for simplify elts of readfirstlane (PR #128645)   Pravin Jagtap via llvm-commits
• [llvm] d3dae84 - [NVPTX] Switch to imm offset variants for LDG and LDU (#128270)   via llvm-commits
• [llvm] [NVPTX] Switch to imm offset variants for LDG and LDU (PR #128270)   Alex MacLean via llvm-commits
• [llvm] [WebAssembly] Make llvm.wasm.throw invokable (PR #128104)   Heejin Ahn via llvm-commits
• [llvm] [SLP][REVEC] Add getScalarizationOverhead helper function to reduce error when REVEC is enabled. (PR #128530)   Han-Kuan Chen via llvm-commits
• [llvm] [Scalarizer] Ensure valid VectorSplits for each struct element in `visitExtractValueInst` (PR #128538)   Jay Foad via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Abhishek Kaushik via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Pengcheng Wang via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Pengcheng Wang via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Pengcheng Wang via llvm-commits
• [llvm] [ctx_prof] Add analysis utility to fetch ID of a callsite (PR #104491)   LLVM Continuous Integration via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Convert vector function nvvm.annotations to attributes (PR #127736)   Guray Ozen via llvm-commits
• [llvm] [flang-rt] Make `FLANG_RT_INSTALL_RESOURCE_PATH` configurable (PR #128561)   Michał Górny via llvm-commits
• [llvm] [flang-rt] Make `FLANG_RT_INSTALL_RESOURCE_PATH` configurable (PR #128561)   Michał Górny via llvm-commits
• [llvm] 5114b9b - [ORC][llvm-jitlink] Extend weak-linking emulation to real dylibs.   Lang Hames via llvm-commits
• [llvm] [RISCV] Correct RISCVTTIImpl::getIntImmCostInst for Zba (PR #128174)   Gergely Futo via llvm-commits
• [llvm] [FlattenCFG] Fix an Imprecise Usage of AA (PR #128117)   Nikita Popov via llvm-commits
• [llvm] [FlattenCFG] Fix an Imprecise Usage of AA (PR #128117)   Nikita Popov via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Jesse Huang via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   via llvm-commits
• [llvm] ea4e19d - [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (#128514)   via llvm-commits
• [llvm] [SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (PR #128514)   Benjamin Maxwell via llvm-commits
• [llvm] [Premerge] Add flang-rt (PR #128678)   Michael Kruse via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Pavel Labath via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Pavel Labath via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   Simon Pilgrim via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Jesse Huang via llvm-commits
• [llvm] 49f60b4 - [AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (#126696)   via llvm-commits
• [llvm] [AsmParser] Avoid repeated map lookups (NFC) (PR #128629)   Nikita Popov via llvm-commits
• [llvm] [AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (PR #126696)   Vikash Gupta via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Simon Pilgrim via llvm-commits
• [llvm] [CodeGen] Avoid repeated hash lookups (NFC) (PR #128631)   Nikita Popov via llvm-commits
• [llvm] [AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (PR #126696)   Matt Arsenault via llvm-commits
• [llvm] [Utils] Avoid repeated hash lookups (NFC) (PR #128634)   Nikita Popov via llvm-commits
• [llvm] [DebugInfo] Avoid repeated hash lookups (NFC) (PR #128632)   Nikita Popov via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Jesse Huang via llvm-commits
• [llvm] [AArch64][Build Attributes] Improve Parsing and Formatting (PR #126530)   Oliver Stannard via llvm-commits
• [llvm] [Dexter] Normalise the "tools directory" into a list of tools (PR #128544)   Orlando Cazalet-Hyams via llvm-commits
• [llvm] [Dexter] Normalise the "tools directory" into a list of tools (PR #128544)   Orlando Cazalet-Hyams via llvm-commits
• [llvm] [Dexter] Normalise the "tools directory" into a list of tools (PR #128544)   Orlando Cazalet-Hyams via llvm-commits
• [llvm] [Dexter] Normalise the "tools directory" into a list of tools (PR #128544)   Orlando Cazalet-Hyams via llvm-commits
• [llvm] [Loads] Support dereferenceable assumption with variable size. (PR #128436)   Nikita Popov via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Pavel Labath via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Pavel Labath via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Pavel Labath via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Pavel Labath via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Pavel Labath via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Pavel Labath via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Pavel Labath via llvm-commits
• [llvm] [AMDGPU] combine uniform AMDGPU lane Intrinsics (PR #116953)   Juan Manuel Martinez Caamaño via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   via llvm-commits
• [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)   Akshat Oke via llvm-commits
• [compiler-rt] [asan][win] Fix CreateThread leak (PR #126738)   via llvm-commits
• [compiler-rt] [asan][win] Fix CreateThread leak (PR #126738)   via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   James Henderson via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   James Henderson via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   James Henderson via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   James Henderson via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   James Henderson via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   James Henderson via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   James Henderson via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   James Henderson via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Abhishek Kaushik via llvm-commits
• [llvm] [X86] Generate `kmov` for masking integers (PR #120593)   Abhishek Kaushik via llvm-commits
• [llvm] b36a18d - [AArch64][Build Attributes] Improve Parsing and Formatting (#126530)   via llvm-commits
• [llvm] [AArch64][Build Attributes] Improve Parsing and Formatting (PR #126530)   via llvm-commits
• [llvm] Do not treat llvm.fake.use as a debug instruction (PR #128684)   Orlando Cazalet-Hyams via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   David Sherwood via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   David Sherwood via llvm-commits
• [llvm] [Support] Ensure complete type DelimitedScope (PR #127459)   Jonas Hahnfeld via llvm-commits
• [llvm] 85cf958 - [AArch64] Improve codegen for some fixed-width partial reductions (#126529)   via llvm-commits
• [llvm] [AArch64] Improve codegen for some fixed-width partial reductions (PR #126529)   David Sherwood via llvm-commits
• [llvm] [Support] Ensure complete type DelimitedScope (PR #127459)   Jonas Hahnfeld via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Justin Bogner via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Justin Bogner via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Justin Bogner via llvm-commits
• [llvm] [LV, VPlan] Check if plan is compatible to EVL transform (PR #92092)   Pengcheng Wang via llvm-commits
• [llvm] [Support] Ensure complete type DelimitedScope (PR #127459)   via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   James Henderson via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   James Henderson via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   James Henderson via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   James Henderson via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   James Henderson via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   James Henderson via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   James Henderson via llvm-commits
• [llvm] [AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)   Pankaj Dwivedi via llvm-commits
• [llvm] [AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)   via llvm-commits
• [llvm] [AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)   Pankaj Dwivedi via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Justin Bogner via llvm-commits
• [llvm] [AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)   via llvm-commits
• [llvm] [GVN][NFC] Match coding standards (PR #128683)   Nikita Popov via llvm-commits
• [llvm] 2a0946b - [GVN][NFC] Match coding standards (#128683)   via llvm-commits
• [llvm] [GVN][NFC] Match coding standards (PR #128683)   Madhur Amilkanthwar via llvm-commits
• [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)   Matt Arsenault via llvm-commits
• [llvm] [X86][NFC] Added/Updated Trigonometric functions testcases (PR #127094)   Evgenii Kudriashov via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   Jose E. Marchesi via llvm-commits
• [llvm] [X86][NFC] Added/Updated Trigonometric functions testcases (PR #127094)   Evgenii Kudriashov via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Jay Foad via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Jay Foad via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Jay Foad via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Jay Foad via llvm-commits
• [llvm] [ConstraintElim] Preserve analyses when IR is unchanged. (PR #128588)   Antonio Frighetto via llvm-commits
• [llvm] [mlir] [OpenMPIRBuilder] Add support for distribute-parallel-for/do constructs (PR #127818)   Sergio Afonso via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Matt Arsenault via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Hans Wennborg via llvm-commits
• [llvm] [LV][VPlan] Prevent calculate cost for skiped instructions in precomputeCosts(). (PR #127966)   Florian Hahn via llvm-commits
• [llvm] SplitKit: Fix rematerialization undoing subclass based split (PR #122110)   Matt Arsenault via llvm-commits
• [llvm] [InstCombine] Increase recursion limit to 3 in `simplifyNonNullOperand` (PR #128695)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Increase recursion limit to 3 in `simplifyNonNullOperand` (PR #128695)   via llvm-commits
• [llvm] [DXIL][Analysis] Make sure resource accessors are contiguous (PR #128696)   Justin Bogner via llvm-commits
• [llvm] [DXIL][Analysis] Make sure resource accessors are contiguous (PR #128696)   via llvm-commits
• [llvm] [DXIL][Analysis] Make sure resource accessors are contiguous (PR #128696)   via llvm-commits
• [llvm] Enable logf128 constant folding for hosts with 128bit long double (PR #104929)   LLVM Continuous Integration via llvm-commits
• [llvm] [DXIL][Analysis] Make sure resource accessors are contiguous (PR #128696)   Justin Bogner via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Jay Foad via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Justin Bogner via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Alexey Bataev via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   via llvm-commits
• [llvm] f95ad44 - AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (#128677)   via llvm-commits
• [llvm] AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (PR #128677)   Matt Arsenault via llvm-commits
• [llvm] [llvm][ELF]Add Shdr check for getBuildID (PR #126537)   Ruoyu Qiu via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Justin Bogner via llvm-commits
• [llvm] [llvm][ELF]Add Shdr check for getBuildID (PR #126537)   Ruoyu Qiu via llvm-commits
• [llvm] AMDGPU: Drop legacy r600.read.global.size intrinsics from amdgcn (PR #128700)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Drop legacy r600.read.global.size intrinsics from amdgcn (PR #128700)   Matt Arsenault via llvm-commits
• [llvm] [SimplifyCFG] Treat umul + extract pattern as one cheap single instruction (#115683) (Approach 2) (PR #128021)   Gábor Spaits via llvm-commits
• [llvm] AMDGPU: Drop legacy r600.read.global.size intrinsics from amdgcn (PR #128700)   via llvm-commits
• [llvm] AMDGPU: Drop legacy r600.read.global.size intrinsics from amdgcn (PR #128700)   Matt Arsenault via llvm-commits
• [llvm] 6aeec5e - [ConstraintElim] Test for #128588   Andreas Jonson via llvm-commits
• [llvm] AMDGPU: Drop legacy r600.read.global.size intrinsics from amdgcn (PR #128700)   Jay Foad via llvm-commits
• [llvm] AMDGPU/GlobalISel: Disable LCSSA pass (PR #124297)   Petar Avramovic via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   Florian Hahn via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   Benjamin Maxwell via llvm-commits
• [llvm] AMDGPU/GlobalISel: Disable LCSSA pass (PR #124297)   Petar Avramovic via llvm-commits
• [llvm] AMDGPU/GlobalISel: Disable LCSSA pass (PR #124297)   Petar Avramovic via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Djordje Todorovic via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   Benjamin Maxwell via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Djordje Todorovic via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   Benjamin Maxwell via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Djordje Todorovic via llvm-commits
• [llvm] AMDGPU/GlobalISel: Disable LCSSA pass (PR #124297)   Matt Arsenault via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   Florian Hahn via llvm-commits
• [llvm] [BOLT] pacret-scanner: fix regression test failure (PR #128576)   Kristof Beyls via llvm-commits
• [llvm] [MergeFuncs] Don't introduce calls to (linkonce,weak)_odr functions. (PR #125050)   Florian Hahn via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   Florian Hahn via llvm-commits
• [llvm] [ConstraintElim] Preserve analyses when IR is unchanged. (PR #128588)   Andreas Jonson via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   Benjamin Maxwell via llvm-commits
• [llvm] [ConstraintElim] Preserve analyses when IR is unchanged. (PR #128588)   Andreas Jonson via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   Benjamin Maxwell via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   Benjamin Maxwell via llvm-commits
• [llvm] [AArch64] Improve urem by constant costs (PR #122236)   Sushant Gokhale via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Alan Li via llvm-commits
• [llvm] Do not treat llvm.fake.use as a debug instruction (PR #128684)   Stephen Tozer via llvm-commits
• [llvm] [SelectionDAG] Added target hook convertSelectOfConstantsToMath check for SelectwithConstant (PR #127599)   Vikash Gupta via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   Ruoyu Qiu via llvm-commits
• [llvm] [AMDGPU] Introduce "amdgpu-sw-lower-lds" pass to lower LDS accesses. (PR #87265)   LLVM Continuous Integration via llvm-commits
• [llvm] [DebugInfo] Merge partially matching chains of textual inclusions (PR #125780)   Stephen Tozer via llvm-commits
• [llvm] [ConstraintElim] Preserve analyses when IR is unchanged. (PR #128588)   Florian Hahn via llvm-commits
• [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Luke Quinn via llvm-commits
• [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [llvm] [SelectionDAG] Added target hook convertSelectOfConstantsToMath check for SelectwithConstant (PR #127599)   Matt Arsenault via llvm-commits
• [llvm] Do not treat llvm.fake.use as a debug instruction (PR #128684)   Orlando Cazalet-Hyams via llvm-commits
• [llvm] [InstCombine] Increase recursion limit to 3 in `simplifyNonNullOperand` (PR #128695)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Increase recursion limit to 3 in `simplifyNonNullOperand` (PR #128695)   Nikita Popov via llvm-commits
• [llvm] [InstCombine] Increase recursion limit to 3 in `simplifyNonNullOperand` (PR #128695)   Nikita Popov via llvm-commits
• [llvm] [InstCombine] Increase recursion limit to 3 in `simplifyNonNullOperand` (PR #128695)   Nikita Popov via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [llvm] a93cda4 - [X86] combineX86ShuffleChain - pull out repeated getOpcode() calls. NFC.   Simon Pilgrim via llvm-commits
• [llvm] e47cd46 - [X86] combineX86ShuffleChain - pass IsMaskedShuffle flag as argument from combineX86ShufflesRecursively instead of computing it internally. NFC.   Simon Pilgrim via llvm-commits
• [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Luke Quinn via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [llvm] 4b29c28 - [ConstraintElim] Preserve analyses when IR is unchanged. (#128588)   via llvm-commits
• [llvm] [ConstraintElim] Preserve analyses when IR is unchanged. (PR #128588)   Andreas Jonson via llvm-commits
• [llvm] [InstCombine] Increase recursion limit to 3 in `simplifyNonNullOperand` (PR #128695)   Yingwei Zheng via llvm-commits
• [llvm] Add unit tests for size returning new funcs in the MemProf use pass. (PR #105473)   LLVM Continuous Integration via llvm-commits
• [llvm] [IR][Instructions] Add `CallBase::getCalledFunctionName` helper (PR #127038)   Thomas Symalla via llvm-commits
• [llvm] [LAA] Be more careful when evaluating AddRecs at symbolic max BTC. (PR #128061)   Florian Hahn via llvm-commits
• [llvm] [LoopVectorizer][AArch64] Add support for partial reduce subtraction (PR #123636)   David Sherwood via llvm-commits
• [llvm] [LoopVectorizer][AArch64] Add support for partial reduce subtraction (PR #123636)   David Sherwood via llvm-commits
• [llvm] [IR][Instructions] Add `CallBase::getCalledFunctionName` helper (PR #127038)   via llvm-commits
• [llvm] Obviously Redundant Assert In AsmWriter (PR #128543)   JP Hafer via llvm-commits
• [llvm] [CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (PR #126807)   Phoebe Wang via llvm-commits
• [llvm] [LAA] Be more careful when evaluating AddRecs at symbolic max BTC. (PR #128061)   Nikita Popov via llvm-commits
• [llvm] Do not treat llvm.fake.use as a debug instruction (PR #128684)   Jeremy Morse via llvm-commits
• [llvm] [SPIR-V] Fix generation of gMIR vs. SPIR-V code from utility methods (PR #128159)   Dmitry Sidorov via llvm-commits
• [llvm] [CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (PR #126807)   Matt Arsenault via llvm-commits
• [llvm] [SPIR-V] Fix generation of gMIR vs. SPIR-V code from utility methods (PR #128159)   Vyacheslav Levytskyy via llvm-commits
• [llvm] d21b2e6 - [SPIR-V] Fix generation of gMIR vs. SPIR-V code from utility methods (#128159)   via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [SPIR-V] Fix generation of gMIR vs. SPIR-V code from utility methods (PR #128159)   LLVM Continuous Integration via llvm-commits
• [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Luke Quinn via llvm-commits
• [llvm] [LoopVectorizer][AArch64] Add support for partial reduce subtraction (PR #123636)   David Sherwood via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   Virginia Cangelosi via llvm-commits
• [llvm] [PowerPC] Retire PPCExpandISel pass (PR #84289)   LLVM Continuous Integration via llvm-commits
• [llvm] [LAA] Be more careful when evaluating AddRecs at symbolic max BTC. (PR #128061)   Florian Hahn via llvm-commits
• [llvm] [LAA] Be more careful when evaluating AddRecs at symbolic max BTC. (PR #128061)   Florian Hahn via llvm-commits
• [llvm] [LAA] Be more careful when evaluating AddRecs at symbolic max BTC. (PR #128061)   Florian Hahn via llvm-commits
• [llvm] [LAA] Be more careful when evaluating AddRecs at symbolic max BTC. (PR #128061)   Florian Hahn via llvm-commits
• [llvm] [LAA] Be more careful when evaluating AddRecs at symbolic max BTC. (PR #128061)   Florian Hahn via llvm-commits
• [llvm] 44d1dbd - [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (#128618)   via llvm-commits
• [llvm] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (PR #128618)   Yingwei Zheng via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   Fabian Ritter via llvm-commits
• [llvm] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (PR #128618)   Yingwei Zheng via llvm-commits
• [llvm] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (PR #128618)   Yingwei Zheng via llvm-commits
• [clang] [llvm] [MergeFuncs] Don't introduce calls to (linkonce,weak)_odr functions. (PR #125050)   Florian Hahn via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Luke Lau via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Luke Lau via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Luke Lau via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   Fabian Ritter via llvm-commits
• [llvm] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (PR #128618)   via llvm-commits
• [llvm] [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (PR #128190)   Dmitry Sidorov via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [LV] Support strided memory accesses with a stride of -1 (PR #128718)   Mel Chen via llvm-commits
• [llvm] [LV] Support strided memory accesses with a stride of -1 (PR #128718)   Mel Chen via llvm-commits
• [llvm] [LV] Support strided memory accesses with a stride of -1 (PR #128718)   via llvm-commits
• [llvm] WIP:[LV] Support strided memory accesses with a stride of -1 (PR #128718)   Mel Chen via llvm-commits
• [llvm] [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (PR #128190)   Vyacheslav Levytskyy via llvm-commits
• [llvm] d23da7d - [InstCombine] Increase recursion limit to 3 in `simplifyNonNullOperand` (#128695)   via llvm-commits
• [llvm] [InstCombine] Increase recursion limit to 3 in `simplifyNonNullOperand` (PR #128695)   Yingwei Zheng via llvm-commits
• [llvm] 522b05a - [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (#128374)   via llvm-commits
• [llvm] [VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (PR #128374)   Florian Hahn via llvm-commits
• [llvm] WIP:[LV] Support strided memory accesses with a stride of -1 (PR #128718)   Mel Chen via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   Matt Arsenault via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [llvm] On Windows, remove the UCRT libraries from the release script (PR #128378)   Alexandre Ganea via llvm-commits
• [llvm] On Windows, remove the UCRT libraries from the release script (PR #128378)   Alexandre Ganea via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   David Sherwood via llvm-commits
• [llvm] On Windows, remove the UCRT libraries from the release script (PR #128378)   via llvm-commits
• [llvm] [LV][EVL] Generate negative strided load/store for reversed load/store (PR #123608)   Mel Chen via llvm-commits
• [llvm] [LV] Limits the splat operations be hoisted must not be defined by a recipe. (PR #117138)   Mel Chen via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   David Sherwood via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [llvm] [IR][Instructions] Add `CallBase::getCalledFunctionName` helper (PR #127038)   Thomas Symalla via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Antonio Frighetto via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Alan Li via llvm-commits
• [llvm] [SystemZ] Handle scalar to vector bitcasts. (PR #128628)   Ulrich Weigand via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   Benjamin Maxwell via llvm-commits
• [llvm] af68927 - Do not treat llvm.fake.use as a debug instruction (#128684)   via llvm-commits
• [llvm] Do not treat llvm.fake.use as a debug instruction (PR #128684)   Stephen Tozer via llvm-commits
• [llvm] [SystemZ] Drop regstate of SELRMux operand in selectSLRMux(). (PR #128555)   Ulrich Weigand via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   Simon Pilgrim via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [llvm] [SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath check for SelectwithConstant (PR #127599)   Vikash Gupta via llvm-commits
• [llvm] [SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (PR #127599)   Vikash Gupta via llvm-commits
• [llvm] 352c48f - [SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)   via llvm-commits
• [llvm] [SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (PR #127599)   Vikash Gupta via llvm-commits
• [llvm] [SLP][REVEC] Add getScalarizationOverhead helper function to reduce error when REVEC is enabled. (PR #128530)   Alexey Bataev via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] Do not treat llvm.fake.use as a debug instruction (PR #128684)   LLVM Continuous Integration via llvm-commits
• [llvm] 4f7d894 - [Hexagon] Add a case to BitTracker for new register class (#128580)   via llvm-commits
• [llvm] [Hexagon] Add a case to BitTracker for new register class (PR #128580)   Ikhlas Ajbar via llvm-commits
• [llvm] LiveIntervals: Use BumpPtrAllocator (PR #127057)   Nikita Popov via llvm-commits
• [llvm] LiveIntervals: Use BumpPtrAllocator (PR #127057)   Nikita Popov via llvm-commits
• [llvm] [AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)   Pankaj Dwivedi via llvm-commits
• [llvm] a12ca57 - [SLP][REVEC] Add getScalarizationOverhead helper function to reduce error when REVEC is enabled. (#128530)   via llvm-commits
• [llvm] [SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (PR #127599)   LLVM Continuous Integration via llvm-commits
• [llvm] [SLP][REVEC] Add getScalarizationOverhead helper function to reduce error when REVEC is enabled. (PR #128530)   Han-Kuan Chen via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Antonio Frighetto via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor build attribute parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor build attribute parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor build attribute parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] [LLVM] Automatically strip `-fno-lifetime-dse` from compile_commands.json (PR #124623)   Joseph Huber via llvm-commits
• [llvm] SplitKit: Fix rematerialization undoing subclass based split (PR #122110)   Christudasan Devadasan via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] 1affadb - AMDGPU: Drop legacy r600.read.global.size intrinsics from amdgcn (#128700)   via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] AMDGPU: Drop legacy r600.read.global.size intrinsics from amdgcn (PR #128700)   Matt Arsenault via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] [X86] Fold AND(Y, XOR(X, SUB(0, X))) to ANDN(Y, BLSMSK(X)) (PR #128348)   Marius Kamp via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)   Christudasan Devadasan via llvm-commits
• [clang] [llvm] [CMake][Release] Enable bolt optimization for clang on Linux (PR #128090)   Tom Stellard via llvm-commits
• [clang] [llvm] [CMake][Release] Enable bolt optimization for clang on Linux (PR #128090)   Tom Stellard via llvm-commits
• [clang] [llvm] [CMake][Release] Enable bolt optimization for clang on Linux (PR #128090)   Tom Stellard via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)   Christudasan Devadasan via llvm-commits
• [clang] [llvm] [CMake][Release] Enable bolt optimization for clang on Linux (PR #128090)   via llvm-commits
• [llvm] [InstCombine] Simplify nonnull phi nodes (PR #128466)   Yingwei Zheng via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] f10e0f7 - [MergeFuncs] Don't introduce calls to (linkonce,weak)_odr functions. (#125050)   via llvm-commits
• [llvm] [RISCV] Use addiw for or_is_add when or input is sign extended. (PR #128635)   Philip Reames via llvm-commits
• [clang] [llvm] [MergeFuncs] Don't introduce calls to (linkonce,weak)_odr functions. (PR #125050)   Florian Hahn via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [llvm] [BOLT] pacret-scanner: fix regression test failure (PR #128576)   Kristof Beyls via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Matt Arsenault via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Matt Arsenault via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Philip Reames via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Philip Reames via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Sudharsan Veeravalli via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] Preserve range metadata when load is narrowed (PR #128144)   via llvm-commits
• [llvm] Preserve range metadata when load is narrowed (PR #128144)   via llvm-commits
• [llvm] Preserve range metadata when load is narrowed (PR #128144)   via llvm-commits
• [llvm] Preserve range metadata when load is narrowed (PR #128144)   via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Alexey Bataev via llvm-commits
• [llvm] Do not treat llvm.fake.use as a debug instruction (PR #128684)   Stephen Tozer via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Antonio Frighetto via llvm-commits
• [llvm] Do not treat llvm.fake.use as a debug instruction (PR #128684)   Stephen Tozer via llvm-commits
• [llvm] [llvm-dwarfdump] Make --verify for .debug_names multithreaded. (PR #127281)   Alexander Yermolovich via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Philip Reames via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Philip Reames via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Philip Reames via llvm-commits
• [llvm] 37559c8 - [Hexagon] Handle Call Operand vxi1 in Hexagon Backend (#128027)   via llvm-commits
• [llvm] Handle Call Operand vxi1 in Hexagon Backend (PR #128027)   Ikhlas Ajbar via llvm-commits
• [llvm] Do not treat llvm.fake.use as a debug instruction (PR #128684)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   Brox Chen via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Lucas Ramirez via llvm-commits
• [llvm] Handle Call Operand vxi1 in Hexagon Backend (PR #128027)   Ikhlas Ajbar via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sudharsan Veeravalli via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Alexey Bataev via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Lucas Ramirez via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Jay Foad via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Lucas Ramirez via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Alexey Bataev via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] [InstCombine] Use known bits to simplify mask in foldSelectICmpAnd (PR #128741)   Julian Nagele via llvm-commits
• [llvm] [InstCombine] Use known bits to simplify mask in foldSelectICmpAnd (PR #128741)   via llvm-commits
• [clang] [llvm] [Clang] [OpenMP] Support NOWAIT with optional argument (PR #128742)   via llvm-commits
• [clang] [llvm] [Clang] [OpenMP] Support NOWAIT with optional argument (PR #128742)   via llvm-commits
• [clang] [llvm] [Clang] [OpenMP] Support NOWAIT with optional argument (PR #128742)   via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Mirko Brkušanin via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Mirko Brkušanin via llvm-commits
• [llvm] 7501c9c - [AsmParser] Avoid repeated map lookups (NFC) (#128629)   via llvm-commits
• [llvm] [AsmParser] Avoid repeated map lookups (NFC) (PR #128629)   Kazu Hirata via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Mirko Brkušanin via llvm-commits
• [llvm] 791da3c - [AsmPrinter] Avoid repeated hash lookups (NFC) (#128630)   via llvm-commits
• [llvm] [AsmPrinter] Avoid repeated hash lookups (NFC) (PR #128630)   Kazu Hirata via llvm-commits
• [llvm] 9388e42 - [CodeGen] Avoid repeated hash lookups (NFC) (#128631)   via llvm-commits
• [llvm] [CodeGen] Avoid repeated hash lookups (NFC) (PR #128631)   Kazu Hirata via llvm-commits
• [llvm] 38f8ca1 - [DebugInfo] Avoid repeated hash lookups (NFC) (#128632)   via llvm-commits
• [llvm] [DebugInfo] Avoid repeated hash lookups (NFC) (PR #128632)   Kazu Hirata via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Mirko Brkušanin via llvm-commits
• [llvm] 9889de8 - [Utils] Avoid repeated hash lookups (NFC) (#128634)   via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Mirko Brkušanin via llvm-commits
• [llvm] [Utils] Avoid repeated hash lookups (NFC) (PR #128634)   Kazu Hirata via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   Krzysztof Drewniak via llvm-commits
• [llvm] PeepholeOpt: Immediately check if a reg_sequence compose supports a subregister (PR #128279)   Quentin Colombet via llvm-commits
• [llvm] 8bea511 - [X86] Fold AND(Y, XOR(X, SUB(0, X))) to ANDN(Y, BLSMSK(X)) (#128348)   via llvm-commits
• [llvm] [X86] Fold AND(Y, XOR(X, SUB(0, X))) to ANDN(Y, BLSMSK(X)) (PR #128348)   Simon Pilgrim via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   Ali Raeisdanaei via llvm-commits
• [llvm] [AArch64] Runtime-unroll small multi-exit loops on Apple Silicon. (PR #124751)   Florian Hahn via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Guy David via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   via llvm-commits
• [llvm] [MachineSink] Lower SplitEdgeProbabilityThreshold (PR #127666)   Guy David via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] f08824b - [AArch64] Add udiv and urem uniform tests. NFC   David Green via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] 24b7759 - [FLANG][OpenMP]Add frontend support for ASSUME and ASSUMES (#120770)   via llvm-commits
• [flang] [llvm] [FLANG][OpenMP]Add frontend support for ASSUME and ASSUMES (PR #120770)   Mats Petersson via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] [RISCV] Correct RISCVTTIImpl::getIntImmCostInst for Zba (PR #128174)   Craig Topper via llvm-commits
• [llvm] [RISCV] Tune flag for fast vrgather.vv (PR #124664)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Craig Topper via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Mikhail R. Gadelha via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Craig Topper via llvm-commits
• [llvm] [Aarch64] [ISel] Don't save vaargs registers if vaargs are unused (PR #126780)   Pavel Skripkin via llvm-commits
• [llvm] [Aarch64] [ISel] Don't save vaargs registers if vaargs are unused (PR #126780)   Pavel Skripkin via llvm-commits
• [llvm] [Support] Replace deprecated std::aligned_union, NFCI. (PR #127417)   David Blaikie via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   Fangrui Song via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   Fangrui Song via llvm-commits
• [llvm] d2d469e - [WebAssembly] Make llvm.wasm.throw invokable (#128104)   via llvm-commits
• [llvm] [WebAssembly] Make llvm.wasm.throw invokable (PR #128104)   Heejin Ahn via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   Fangrui Song via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   Fangrui Song via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   LLVM Continuous Integration via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   Fangrui Song via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
• [llvm] [RISCV] Use addiw for or_is_add when or input is sign extended. (PR #128635)   Craig Topper via llvm-commits
• [llvm] [LTO][Pipelines][NFC] Exctract isLTOPostLink (PR #128653)   Arthur Eubanks via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [llvm] 4f18f3f - [RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)   via llvm-commits
• [llvm] [RISCV] Use addiw for or_is_add when or input is sign extended. (PR #128635)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Craig Topper via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
• [llvm] [AArch64] Improve urem by constant costs (PR #122236)   David Green via llvm-commits
• [llvm] [AArch64] Improve urem by constant costs (PR #122236)   David Green via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Zahira Ammarguellat via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Luke Quinn via llvm-commits
• [llvm] [MachinePipeliner] Fix loop-carried dependencies analysis (PR #121907)   Ikhlas Ajbar via llvm-commits
• [llvm] [DXIL][Analysis] Make sure resource accessors are contiguous (PR #128696)   Chris B via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Convert vector function nvvm.annotations to attributes (PR #127736)   Alex MacLean via llvm-commits
• [llvm] [OFFLOAD] Update ffi_cif structure to match libffi (PR #128756)   via llvm-commits
• [llvm] [OFFLOAD] Update ffi_cif structure to match libffi (PR #128756)   via llvm-commits
• [llvm] [OFFLOAD] Update ffi_cif structure to match libffi (PR #128756)   Joseph Huber via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Nicolai Hähnle via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Nicolai Hähnle via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Nicolai Hähnle via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Nicolai Hähnle via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Chris B via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Chris B via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Chris B via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Convert vector function nvvm.annotations to attributes (PR #127736)   Han-Chung Wang via llvm-commits
• [llvm] 67056c2 - [WebAssembly] Support shuffle for F16x8 vectors. (#127857)   via llvm-commits
• [llvm] [WebAssembly] Support shuffle for F16x8 vectors. (PR #127857)   Brendan Dahl via llvm-commits
• [llvm] AMDGPU/GlobalISel: Disable LCSSA pass (PR #124297)   Nicolai Hähnle via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Convert vector function nvvm.annotations to attributes (PR #127736)   Alex MacLean via llvm-commits
• [llvm] [BOLT] Keep multi-entry functions simple in aggregation mode (PR #128253)   Davide Italiano via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Helena Kotas via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Helena Kotas via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Helena Kotas via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [BOLT] Keep multi-entry functions simple in aggregation mode (PR #128253)   Amir Ayupov via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [BOLT] Fix doTrace in BAT mode (PR #128546)   Amir Ayupov via llvm-commits
• [llvm] [BOLT] Fix doTrace in BAT mode (PR #128546)   Amir Ayupov via llvm-commits
• [llvm] [WebAssembly] Use the same lowerings for f16x8 as other float vectors. (PR #127897)   Brendan Dahl via llvm-commits
• [clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Luke Quinn via llvm-commits
• [llvm] [RISCV] Change the vendor prefix for Rivos from "rv." to "ri." (PR #128761)   Philip Reames via llvm-commits
• [llvm] [RISCV] Change the vendor prefix for Rivos from "rv." to "ri." (PR #128761)   via llvm-commits
• [llvm] 7c26675 - [gn build] Port 66af4923ce24   LLVM GN Syncbot via llvm-commits
• [llvm] 9102afc - [WebAssembly] Use the same lowerings for f16x8 as other float vectors. (#127897)   via llvm-commits
• [llvm] [WebAssembly] Use the same lowerings for f16x8 as other float vectors. (PR #127897)   Brendan Dahl via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Convert vector function nvvm.annotations to attributes (PR #127736)   Han-Chung Wang via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Justin Bogner via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Justin Bogner via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Helena Kotas via llvm-commits
• [clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Luke Quinn via llvm-commits
• [llvm] [RISCV] Change the vendor prefix for Rivos from "rv." to "ri." (PR #128761)   Craig Topper via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Craig Topper via llvm-commits
• [llvm] [RISCV] Change the vendor prefix for Rivos from "rv." to "ri." (PR #128761)   Sam Elliott via llvm-commits
• [llvm] c8136da - [RISCV] Correctly Decode Unsigned Immediates with Ranges (#128584)   via llvm-commits
• [llvm] [RISCV] Correctly Decode Unsigned Immediates with Ranges (PR #128584)   Sam Elliott via llvm-commits
• [llvm] f22291c - [RISCV][NFC] Merge Xqci Decoder Tables (#128140)   via llvm-commits
• [llvm] [RISCV][NFC] Merge Xqci Decoder Tables (PR #128140)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   David Blaikie via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   David Blaikie via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Min-Yih Hsu via llvm-commits
• [llvm] Obviously Redundant Assert In AsmWriter (PR #128543)   JP Hafer via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   Miro Bucko via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   Miro Bucko via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   Miro Bucko via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   Miro Bucko via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   Miro Bucko via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
• [llvm] 00f02fe - [RISCV] Change the vendor prefix for Rivos from "rv." to "ri." (#128761)   via llvm-commits
• [llvm] [RISCV] Change the vendor prefix for Rivos from "rv." to "ri." (PR #128761)   Philip Reames via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Min-Yih Hsu via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Min-Yih Hsu via llvm-commits
• [libcxx] [llvm] [libc++] Diagnose when nullptrs are passed to string APIs (PR #122790)   Mark de Wever via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   Nikita Popov via llvm-commits
• [llvm] [llvm-ifs] Handle more e_machine values for --target (PR #128559)   Roland McGrath via llvm-commits
• [llvm] [llvm-ifs] Handle more e_machine values for --target (PR #128559)   Roland McGrath via llvm-commits
• [llvm] clang-format aliasing analysis files (PR #128526)   via llvm-commits
• [llvm] f1025e6 - [Support] Replace deprecated std::aligned_union, NFCI. (#127417)   via llvm-commits
• [llvm] [Support] Replace deprecated std::aligned_union, NFCI. (PR #127417)   Jonas Hahnfeld via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   via llvm-commits
• [llvm] [Support] Replace deprecated std::aligned_union, NFCI. (PR #127417)   LLVM Continuous Integration via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [DXIL][Analysis] Make sure resource accessors are contiguous (PR #128696)   Helena Kotas via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] [Support] Replace deprecated std::aligned_union, NFCI. (PR #127417)   Jan Patrick Lehr via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Djordje Todorovic via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Djordje Todorovic via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   via llvm-commits
• [llvm] [AMDGPU] Skip handling non-byte types in promote alloca. (PR #128769)   Sumanth Gundapaneni via llvm-commits
• [llvm] [AMDGPU] Skip handling non-byte types in promote alloca. (PR #128769)   via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Sumanth Gundapaneni via llvm-commits
• [llvm] [Support] Replace deprecated std::aligned_union, NFCI. (PR #127417)   Jonas Hahnfeld via llvm-commits
• [llvm] [Support] Replace deprecated std::aligned_union, NFCI. (PR #127417)   Jan Patrick Lehr via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Damyan Pepper via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Farzon Lotfi via llvm-commits
• [llvm] 6a5dd04 - [Support] Try to fix AlignedCharArrayUnion with GCC 7.5   Jonas Hahnfeld via llvm-commits
• [llvm] c79e867 - [DirectX] Update CBuffer to refer to a `dx.Layout` type (#128697)   via llvm-commits
• [llvm] [DirectX] Update CBuffer to refer to a `dx.Layout` type (PR #128697)   Justin Bogner via llvm-commits
• [llvm] [Support] Replace deprecated std::aligned_union, NFCI. (PR #127417)   Jonas Hahnfeld via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Deric Cheung via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Deric Cheung via llvm-commits
• [llvm] Create Claudia-swift-Code-Owner (PR #74578)   via llvm-commits
• [llvm] [DXIL][Analysis] Make sure resource accessors are contiguous (PR #128696)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] Fix printing of DXIL cbuffer info (PR #128698)   Justin Bogner via llvm-commits
• [llvm] [DirectX] Fix printing of DXIL cbuffer info (PR #128698)   Justin Bogner via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Philip Reames via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Shilei Tian via llvm-commits
• [llvm] [Support] Replace deprecated std::aligned_union, NFCI. (PR #127417)   Jan Patrick Lehr via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [llvm] 0be3f13 - [DirectX] only allow intrinsics defined in DXIL.td (#128613)   via llvm-commits
• [llvm] [DirectX] only allow intrinsics defined in DXIL.td (PR #128613)   Farzon Lotfi via llvm-commits
• [lld] [LLD][ELF] Generically report "address assignment did not converge" (PR #128774)   Daniel Thornburgh via llvm-commits
• [lld] [LLD][ELF] Generically report "address assignment did not converge" (PR #128774)   Daniel Thornburgh via llvm-commits
• [lld] [LLD][ELF] Generically report "address assignment did not converge" (PR #128774)   via llvm-commits
• [lld] [LLD][ELF] Generically report "address assignment did not converge" (PR #128774)   via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Philip Reames via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Sumanth Gundapaneni via llvm-commits
• [llvm] [llvm-objdump] Add support for HIP offload bundles (PR #114834)   David Salinas via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Sumanth Gundapaneni via llvm-commits
• [lld] wasm-ld: Implement function pointer alignment (PR #105532)   Sam Clegg via llvm-commits
• [lld] [LLD][ELF] Generically report "address assignment did not converge" (PR #128774)   Daniel Thornburgh via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Shilei Tian via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Shilei Tian via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   Ellis Hoag via llvm-commits
• [llvm] 44ffeec - [DXIL][Analysis] Make sure resource accessors are contiguous (#128696)   via llvm-commits
• [llvm] [DXIL][Analysis] Make sure resource accessors are contiguous (PR #128696)   Justin Bogner via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Brox Chen via llvm-commits
• [llvm] e6f6a1e - [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   Brox Chen via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   Reid Kleckner via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   LLVM Continuous Integration via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   David Blaikie via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   LLVM Continuous Integration via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Derek Schuff via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   LLVM Continuous Integration via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Min-Yih Hsu via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   LLVM Continuous Integration via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   Brox Chen via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Craig Topper via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Craig Topper via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Guy David via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Guy David via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Craig Topper via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   Krzysztof Drewniak via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Alireza Torabian via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   Alexander Yermolovich via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Craig Topper via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Craig Topper via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Craig Topper via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Craig Topper via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Alireza Torabian via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] Bazel fixes for a778930f85b6d17cf31ff0e15964a7c7116e2a9d (PR #128783)   via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Min-Yih Hsu via llvm-commits
• [llvm] [SimplifyCFG] Treat umul + extract pattern as one cheap single instruction (#115683) (Approach 2) (PR #128021)   Gábor Spaits via llvm-commits
• [llvm] Bazel fixes for a778930f85b6d17cf31ff0e15964a7c7116e2a9d (PR #128783)   via llvm-commits
• [llvm] 30a7c81 - [LTO][Pipelines][NFC] Exctract isLTOPostLink (#128653)   via llvm-commits
• [llvm] [LTO][Pipelines][NFC] Exctract isLTOPostLink (PR #128653)   Vitaly Buka via llvm-commits
• [llvm] quick fix for test failure (PR #128784)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] buildbot fix for uaddsat/usubsat true16 selection (PR #128784)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] buildbot fix for uaddsat/usubsat true16 selection (PR #128784)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] buildbot fix for uaddsat/usubsat true16 selection (PR #128784)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] buildbot fix for uaddsat/usubsat true16 selection (PR #128784)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] buildbot fix for uaddsat/usubsat true16 selection (PR #128784)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] buildbot fix for uaddsat/usubsat true16 selection (PR #128784)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (PR #128784)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   Alexander Yermolovich via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   Brox Chen via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Craig Topper via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (PR #128784)   Brox Chen via llvm-commits
• [llvm] [LTO][Pipelines][NFC] Exctract isLTOPostLink (PR #128653)   LLVM Continuous Integration via llvm-commits
• [llvm] [LTO][Pipelines][Coro] De-duplicate Coro passes (PR #128654)   Vitaly Buka via llvm-commits
• [llvm] [LoopPeel] Fix branch weights (PR #128785)   Joel E. Denny via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (PR #128784)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (PR #128784)   Brox Chen via llvm-commits
• [llvm] [DirectX] Fix printing of DXIL cbuffer info (PR #128698)   Justin Bogner via llvm-commits
• [llvm] [DirectX] Support the CBufferLoadLegacy operation (PR #128699)   Justin Bogner via llvm-commits
• [llvm] [CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (PR #126807)   Eli Friedman via llvm-commits
• [llvm] 1b39328 - [CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (#126807)   via llvm-commits
• [llvm] [CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (PR #126807)   Eli Friedman via llvm-commits
• [llvm] [RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models (PR #128786)   Min-Yih Hsu via llvm-commits
• [llvm] [RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models (PR #128786)   via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Min-Yih Hsu via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Min-Yih Hsu via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Min-Yih Hsu via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Min-Yih Hsu via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] b7060d0 - [DirectX] Fix printing of DXIL cbuffer info (#128698)   Justin Bogner via llvm-commits
• [llvm] [DirectX] Support the CBufferLoadLegacy operation (PR #128699)   Justin Bogner via llvm-commits
• [clang] [llvm] [llvm:ir] Add support for constant data exceeding 4GiB (PR #126481)   Eli Friedman via llvm-commits
• [clang] [llvm] [llvm:ir] Add support for constant data exceeding 4GiB (PR #126481)   Eli Friedman via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [DirectX] Support the CBufferLoadLegacy operation (PR #128699)   Justin Bogner via llvm-commits
• [llvm] [DirectX] Support the CBufferLoadLegacy operation (PR #128699)   Justin Bogner via llvm-commits
• [llvm] [DirectX] Support the CBufferLoadLegacy operation (PR #128699)   Justin Bogner via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   Zequan Wu via llvm-commits
• [llvm] [Analysis]: Allow inlining recursive call IF recursion depth is 1. (PR #119677)   Hassnaa Hamdi via llvm-commits
• [llvm] [Analysis]: Allow inlining recursive call IF recursion depth is 1. (PR #119677)   Hassnaa Hamdi via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Heejin Ahn via llvm-commits
• [llvm] [Analysis]: Allow inlining recursive call IF recursion depth is 1. (PR #119677)   Hassnaa Hamdi via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   Shilei Tian via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   Shilei Tian via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Shilei Tian via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Shilei Tian via llvm-commits
• [llvm] [RISCV] Merge a some of the Sifive decoder tables. (PR #128794)   Craig Topper via llvm-commits
• [llvm] [RISCV] Merge a some of the Sifive decoder tables. (PR #128794)   via llvm-commits
• [llvm] [JumpThreading] Remove deleted BB from Unreachable (PR #126984)   via llvm-commits
• [llvm] [JumpThreading] Remove deleted BB from Unreachable (PR #126984)   via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   Zequan Wu via llvm-commits
• [llvm] [FlattenCFG] Fix an Imprecise Usage of AA (PR #128117)   via llvm-commits
• [llvm] c8b4086 - [AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (#128784)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (PR #128784)   Brox Chen via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Convert vector function nvvm.annotations to attributes (PR #127736)   Alex MacLean via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Convert vector function nvvm.annotations to attributes (PR #127736)   Alex MacLean via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   Zequan Wu via llvm-commits
• [llvm] [JumpThreading] Remove deleted BB from Unreachable (PR #126984)   via llvm-commits
• [llvm] [FlattenCFG] Fix an Imprecise Usage of AA (PR #128117)   via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   Zequan Wu via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   LLVM Continuous Integration via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] [LoongArch] use TypeWidenVector for most illegal vector types (PR #126456)   via llvm-commits
• [llvm] [Analysis]: Allow inlining recursive call IF recursion depth is 1. (PR #119677)   Hassnaa Hamdi via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] [RISCV] Merge a some of the Sifive decoder tables. (PR #128794)   Philip Reames via llvm-commits
• [llvm] [llvm-objdump] Add support for HIP offload bundles (PR #114834)   Joseph Huber via llvm-commits
• [llvm] [llvm-objdump] Add support for HIP offload bundles (PR #114834)   Joseph Huber via llvm-commits
• [llvm] [RISCV] Merge some of the Sifive decoder tables. (PR #128794)   Craig Topper via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   Vitaly Buka via llvm-commits
• [llvm] 439de05 - [RISCV] Rename function name to start with prefix vpreduce for consistency. (NFC)   Jim Lin via llvm-commits
• [llvm] a565f9e - [RISCV] The test for vp.reduce.fminimum/fmaximum with fixed-length should stay in fixed-vectors-reduction-fp-vp.ll. (NFC)   Jim Lin via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   Vitaly Buka via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   Brox Chen via llvm-commits
• [llvm] 01cc1d1 - [RISCV] Use Priv tablegen class for sf.cease instruction.   Craig Topper via llvm-commits
• [llvm] [LTO][Pipelines][Coro] De-duplicate Coro passes (PR #128654)   Vitaly Buka via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Jim Lin via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Jim Lin via llvm-commits
• [llvm] [LoongArch] use TypeWidenVector for most illegal vector types (PR #126456)   via llvm-commits
• [llvm] [AA] Move Target Specific AA before BasicAA (PR #125965)   via llvm-commits
• [llvm] [BOLT][AArch64] Basic support for Linux kernel (PR #118022)   via llvm-commits
• [llvm] [BOLT][Linux] Remove long-jump-labels option (PR #120929)   via llvm-commits
• [llvm] c53eb93 - PeepholeOpt: Immediately check if a reg_sequence compose supports a subregister (#128279)   via llvm-commits
• [llvm] PeepholeOpt: Immediately check if a reg_sequence compose supports a subregister (PR #128279)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Merge some of the Sifive decoder tables. (PR #128794)   Sam Elliott via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Matt Arsenault via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Matt Arsenault via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Merge some of the Sifive decoder tables. (PR #128794)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Pengcheng Wang via llvm-commits
• [lld] [LLD][COFF] Rebuild nodefaultlibs after updating search paths and support /noexp (PR #128808)   via llvm-commits
• [lld] [LLD][COFF] Rebuild nodefaultlibs after updating search paths and support /noexp (PR #128808)   via llvm-commits
• [lld] [LLD][COFF] Rebuild nodefaultlibs after updating search paths and support /noexp (PR #128808)   via llvm-commits
• [llvm] Update BUILD.bazel post - PR #128541 (PR #128809)   Mircea Trofin via llvm-commits
• [clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Sudharsan Veeravalli via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Pengcheng Wang via llvm-commits
• [llvm] [RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models (PR #128786)   Pengcheng Wang via llvm-commits
• [llvm] Update BUILD.bazel post - PR #128541 (PR #128809)   Aiden Grossman via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Matt Arsenault via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Hank Chang via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Hank Chang via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [llvm] [InstCombine] Simplify nonnull phi nodes (PR #128466)   Yingwei Zheng via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)   Craig Topper via llvm-commits
• [lld] [LLD][COFF] Rebuild nodefaultlibs after updating search paths and support /noexp (PR #128808)   via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   via llvm-commits
• [llvm] posisel fix (PR #128812)   Brox Chen via llvm-commits
• [llvm] 31897e6 - [LTO][Pipelines][Coro] De-duplicate Coro passes (#128654)   via llvm-commits
• [llvm] [LTO][Pipelines][Coro] De-duplicate Coro passes (PR #128654)   Vitaly Buka via llvm-commits
• [lld] [LLD][COFF] Update nodefaultlibs after updating search paths (PR #128813)   via llvm-commits
• [lld] [LLD][COFF] Update nodefaultlibs after updating search paths (PR #128813)   via llvm-commits
• [lld] [LLD][COFF] Add /noexp for link.exe compatibility (PR #128814)   via llvm-commits
• [lld] [LLD][COFF] Update nodefaultlibs after updating search paths (PR #128813)   via llvm-commits
• [lld] [LLD][COFF] Add /noexp for link.exe compatibility (PR #128814)   via llvm-commits
• [lld] [LLD][COFF] Add /noexp for link.exe compatibility (PR #128814)   via llvm-commits
• [llvm] [LoongArch] use TypeWidenVector for most illegal vector types (PR #126456)   Lu Weining via llvm-commits
• [llvm] [LoongArch] use TypeWidenVector for most illegal vector types (PR #126456)   Lu Weining via llvm-commits
• [llvm] 8529238 - [AMDGPU][NewPM] Port AMDGPUInsertDelayAlu to NPM (#128003)   via llvm-commits
• [llvm] [AMDGPU][NewPM] Port AMDGPUInsertDelayAlu to NPM (PR #128003)   Akshat Oke via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [llvm] [AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (PR #128471)   Akshat Oke via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   via llvm-commits
• [clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Sam Elliott via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Luke Lau via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Luke Lau via llvm-commits
• [lld] [LLD][COFF] Rebuild nodefaultlibs after updating search paths and support /noexp (PR #128808)   via llvm-commits
• [llvm] [AMDGPU][NewPM] Port AMDGPUInsertDelayAlu to NPM (PR #128003)   LLVM Continuous Integration via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Luke Lau via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Luke Lau via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Craig Topper via llvm-commits
• [llvm] Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128… (PR #128662)   Kazu Hirata via llvm-commits
• [llvm] Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128… (PR #128662)   Kazu Hirata via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Craig Topper via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Craig Topper via llvm-commits
• [llvm] 472ea0b - [RISCV] Merge some of the Sifive decoder tables. (#128794)   via llvm-commits
• [llvm] [RISCV] Merge some of the Sifive decoder tables. (PR #128794)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Luke Lau via llvm-commits
• [llvm] [DirectX] initialize registers properties by calling addRegisterClass and computeRegisterProperties (PR #128818)   Farzon Lotfi via llvm-commits
• [llvm] [DirectX] initialize registers properties by calling addRegisterClass and computeRegisterProperties (PR #128818)   via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Craig Topper via llvm-commits
• [clang] [llvm] [mlir] [NVPTX] Convert vector function nvvm.annotations to attributes (PR #127736)   Alex MacLean via llvm-commits
• [llvm] [AArch64] Improve urem by constant costs (PR #122236)   Sushant Gokhale via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (NFCI) (PR #113903)   Elvis Wang via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [llvm] [AArch64] Improve urem by constant costs (PR #122236)   Sushant Gokhale via llvm-commits
• [llvm] [InstCombine] Use known bits to simplify mask in foldSelectICmpAnd (PR #128741)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Use known bits to simplify mask in foldSelectICmpAnd (PR #128741)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Use known bits to simplify mask in foldSelectICmpAnd (PR #128741)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Use known bits to simplify mask in foldSelectICmpAnd (PR #128741)   Yingwei Zheng via llvm-commits
• [llvm] [LoongArch] use TypeWidenVector for most illegal vector types (PR #126456)   via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (NFCI) (PR #113903)   Elvis Wang via llvm-commits
• [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (NFCI) (PR #113903)   Elvis Wang via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Craig Topper via llvm-commits
• [llvm] e927cf6 - Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128… (#128662)   via llvm-commits
• [llvm] Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128… (PR #128662)   Akshat Oke via llvm-commits
• [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)   Akshat Oke via llvm-commits
• [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)   Akshat Oke via llvm-commits
• [llvm] Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128… (PR #128662)   LLVM Continuous Integration via llvm-commits
• [llvm] Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128… (PR #128662)   LLVM Continuous Integration via llvm-commits
• [llvm] Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128… (PR #128662)   LLVM Continuous Integration via llvm-commits
• [llvm] Revert "Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128…" (PR #128819)   Akshat Oke via llvm-commits
• [llvm] e3ece07 - Revert "Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128…" (#128819)   via llvm-commits
• [llvm] Revert "Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128…" (PR #128819)   Akshat Oke via llvm-commits
• [llvm] Revert "Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128…" (PR #128819)   via llvm-commits
• [llvm] PeepholeOpt: Immediately check if a reg_sequence compose supports a subregister (PR #128279)   LLVM Continuous Integration via llvm-commits
• [llvm] Support: Do not check if a file exists before executing (PR #128821)   Matt Arsenault via llvm-commits
• [llvm] Support: Do not check if a file exists before executing (PR #128821)   Matt Arsenault via llvm-commits
• [llvm] Support: Do not check if a file exists before executing (PR #128821)   via llvm-commits
• [llvm] Revert "Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128…" (PR #128819)   LLVM Continuous Integration via llvm-commits
• [llvm] Support: Do not check if a file exists before executing (PR #128821)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)   Matt Arsenault via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [llvm] [X86] Draft Scheduling model for Zen5 (PR #128822)   via llvm-commits
• [llvm] [X86] Add scheduling model for Zen5 (PR #128822)   via llvm-commits
• [llvm] [X86] Add scheduling model for Zen5 (PR #128822)   via llvm-commits
• [llvm] Support: Do not check if a file exists before executing (PR #128821)   Fangrui Song via llvm-commits
• [llvm] Support: Do not check if a file exists before executing (PR #128821)   Fangrui Song via llvm-commits
• [llvm] Support: Do not check if a file exists before executing (PR #128821)   Matt Arsenault via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   Fangrui Song via llvm-commits
• [clang] [lldb] [llvm] Extending LLDB to work on AIX (PR #102601)   via llvm-commits
• [llvm] [AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)   Pankaj Dwivedi via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   Matt Arsenault via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++][ranges] P2542R8: Implement `views::concat` (PR #120920)   A. Jiang via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++][ranges] P2542R8: Implement `views::concat` (PR #120920)   A. Jiang via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++][ranges] P2542R8: Implement `views::concat` (PR #120920)   A. Jiang via llvm-commits
• [llvm] [AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)   Pankaj Dwivedi via llvm-commits
• [llvm] [AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)   Christudasan Devadasan via llvm-commits
• [llvm] [AMDGPU] Introduce "amdgpu-uniform-intrinsic-combine" pass to combine uniform AMDGPU lane Intrinsics. (PR #116953)   Pankaj Dwivedi via llvm-commits
• [llvm] [WIP][AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)   Pankaj Dwivedi via llvm-commits
• [llvm] [LoongArch] use TypeWidenVector for most illegal vector types (PR #126456)   via llvm-commits
• [llvm] VirtRegRewriter: Fix verifier errors after regalloc failures (PR #128280)   Matt Arsenault via llvm-commits
• [llvm] VirtRegRewriter: Fix verifier errors after regalloc failures (PR #128280)   Matt Arsenault via llvm-commits
• [llvm] [Bitcode] Avoid repeated hash lookups (NFC) (PR #128824)   Kazu Hirata via llvm-commits
• [llvm] [DWARFLinker] Avoid repeated hash lookups (NFC) (PR #128825)   Kazu Hirata via llvm-commits
• [llvm] b5dd1fe - VirtRegRewriter: Fix verifier errors after regalloc failures (#128280)   via llvm-commits
• [llvm] VirtRegRewriter: Fix verifier errors after regalloc failures (PR #128280)   Matt Arsenault via llvm-commits
• [llvm] RegAllocFast: Fix verifier errors after assigning to reserved registers (PR #128281)   Matt Arsenault via llvm-commits
• [llvm] RegAllocFast: Fix verifier errors after assigning to reserved registers (PR #128281)   Matt Arsenault via llvm-commits
• [llvm] [DebugInfo] Avoid repeated map lookups (NFC) (PR #128826)   Kazu Hirata via llvm-commits
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• [llvm] [ExecutionEngine] Avoid repeated hash lookups (NFC) (PR #128827)   Kazu Hirata via llvm-commits
• [llvm] [Passes] Avoid repeated hash lookups (NFC) (PR #128828)   Kazu Hirata via llvm-commits
• [llvm] [LoongArch] use TypeWidenVector for most illegal vector types (PR #126456)   via llvm-commits
• [llvm] 75aff78 - RegAllocFast: Fix verifier errors after assigning to reserved registers (#128281)   via llvm-commits
• [llvm] RegAllocFast: Fix verifier errors after assigning to reserved registers (PR #128281)   Matt Arsenault via llvm-commits
• [llvm] [ProfileData] Avoid repeated hash lookups (NFC) (PR #128829)   Kazu Hirata via llvm-commits
• [llvm] Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)" (PR #128400)   Matt Arsenault via llvm-commits
• [llvm] [ProfileData] Avoid repeated hash lookups (NFC) (PR #128829)   via llvm-commits
• [llvm] [X86] Handle multiple use freeze(undef) in LowerAVXCONCAT_VECTORS as zero vectors (PR #128830)   Phoebe Wang via llvm-commits
• [llvm] [X86] Handle multiple use freeze(undef) in LowerAVXCONCAT_VECTORS as zero vectors (PR #128830)   Phoebe Wang via llvm-commits
• [llvm] [X86] Handle multiple use freeze(undef) in LowerAVXCONCAT_VECTORS as zero vectors (PR #128830)   via llvm-commits
• [llvm] [LoopInterchange] Avoid using CacheCost if cache line size is zero (PR #126021)   Ryotaro Kasuga via llvm-commits
• [llvm] [LoopInterchange] Avoid using CacheCost if cache line size is zero (PR #126021)   Ryotaro Kasuga via llvm-commits
• [llvm] Create Claudia-swift-Code-Owner (PR #74578)   Timm Baeder via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   via llvm-commits
• [llvm] fe13cb9 - [CodeGen][NewPM] Port RegAllocGreedy to NPM (#119540)   via llvm-commits
• [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)   Akshat Oke via llvm-commits
• [llvm] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (PR #120557)   Akshat Oke via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Luke Lau via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Luke Lau via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Luke Lau via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Luke Lau via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Luke Lau via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   Sudharsan Veeravalli via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   via llvm-commits
• [llvm] 8dd6095 - Support: Do not check if a file exists before executing (#128821)   via llvm-commits
• [llvm] Support: Do not check if a file exists before executing (PR #128821)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)   LLVM Continuous Integration via llvm-commits
• [llvm] [LoongArch] Pre-commit tests for vector sext & zext (PR #128835)   via llvm-commits
• [llvm] [MachineOutliner] Add skipModule call for opt-bisect-limit. (PR #128836)   Craig Topper via llvm-commits
• [llvm] [LoongArch] Pre-commit tests for vector sext & zext (PR #128835)   via llvm-commits
• [llvm] [MachineOutliner] Add skipModule call for opt-bisect-limit. (PR #128836)   Matt Arsenault via llvm-commits
• [llvm] Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)" (PR #128400)   Matt Arsenault via llvm-commits
• [llvm] [MachinePipeliner] Fix loop-carried dependencies analysis (PR #121907)   Ryotaro Kasuga via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Matt Arsenault via llvm-commits
• [llvm] 29c5e42 - AMDGPU: Add baseline tests for bitcast + readlane intrinsics (#128493)   via llvm-commits
• [llvm] AMDGPU: Add baseline tests for bitcast + readlane intrinsics (PR #128493)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Fold bitcasts into readfirstlane, readlane, and permlane64 (PR #128494)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Fold bitcasts into readfirstlane, readlane, and permlane64 (PR #128494)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)   LLVM Continuous Integration via llvm-commits
• [llvm] [LangRef] Document accessing memory outside of object is UB. (PR #128429)   Matt Arsenault via llvm-commits
• [clang] [llvm] [RISCV] Assembler support for XRivosVizip (PR #127694)   Sudharsan Veeravalli via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Jim Lin via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Jim Lin via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [LoongArch] Pre-commit tests for vector sext & zext (PR #128835)   via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Luke Lau via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Luke Lau via llvm-commits
• [llvm] [LoongArch] Pre-commit tests for vector sext & zext (PR #128835)   via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Luke Lau via llvm-commits
• [llvm] 92d8222 - [LoongArch] Pre-commit tests for vector sext & zext (#128835)   via llvm-commits
• [llvm] [LoongArch] Pre-commit tests for vector sext & zext (PR #128835)   via llvm-commits
• [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)   Akshat Oke via llvm-commits
• [llvm] [Asan] Provide TTI hook to provide memory reference infromation of ta… (PR #127753)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Matt Arsenault via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Luke Lau via llvm-commits
• [llvm] [RISCV] Optimize divide by constant for VP intrinsics (PR #125991)   Jesse Huang via llvm-commits
• [llvm] [LoongArch] Pre-commit tests for vector sext & zext (PR #128835)   LLVM Continuous Integration via llvm-commits
• [llvm] Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)" (PR #128400)   Matt Arsenault via llvm-commits
• [llvm] e160c35 - Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)" (#128400)   via llvm-commits
• [llvm] Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)" (PR #128400)   Matt Arsenault via llvm-commits
• [llvm] RegAlloc: Use new approach to handling failed allocations (PR #128469)   Matt Arsenault via llvm-commits
• [llvm] RegAlloc: Use new approach to handling failed allocations (PR #128469)   Matt Arsenault via llvm-commits
• [llvm] [Bitcode] Avoid repeated hash lookups (NFC) (PR #128824)   Nikita Popov via llvm-commits
• [llvm] 1a114fa - RegAlloc: Use new approach to handling failed allocations (#128469)   via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Matt Arsenault via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Matt Arsenault via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][MC] Disassembler warning for v_cmpx instructions (PR #127925)   Matt Arsenault via llvm-commits
• [llvm] [DebugInfo] Avoid repeated map lookups (NFC) (PR #128826)   Nikita Popov via llvm-commits
• [llvm] [ExecutionEngine] Avoid repeated hash lookups (NFC) (PR #128827)   Nikita Popov via llvm-commits
• [llvm] [AMDGPU][MC] Disassembler warning for v_cmpx instructions (PR #128256)   Matt Arsenault via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   Simon Pilgrim via llvm-commits
• [llvm] [Passes] Avoid repeated hash lookups (NFC) (PR #128828)   Nikita Popov via llvm-commits
• [llvm] [ProfileData] Avoid repeated hash lookups (NFC) (PR #128829)   Nikita Popov via llvm-commits
• [flang] [llvm] [Flang] Remove FLANG_INCLUDE_RUNTIME (PR #124126)   Michael Kruse via llvm-commits
• [llvm] [SelectionDAG] Wire up -gen-sdnode-info TableGen backend (PR #125358)   Matt Arsenault via llvm-commits
• [llvm] bd9e31e - [DWARFLinker] Avoid repeated hash lookups (NFC) (#128825)   via llvm-commits
• [llvm] [DWARFLinker] Avoid repeated hash lookups (NFC) (PR #128825)   Kazu Hirata via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   LLVM Continuous Integration via llvm-commits
• [llvm] e49c8d5 - [DebugInfo] Avoid repeated map lookups (NFC) (#128826)   via llvm-commits
• [llvm] [DebugInfo] Avoid repeated map lookups (NFC) (PR #128826)   Kazu Hirata via llvm-commits
• [llvm] 67d92cf - [ExecutionEngine] Avoid repeated hash lookups (NFC) (#128827)   via llvm-commits
• [llvm] [ExecutionEngine] Avoid repeated hash lookups (NFC) (PR #128827)   Kazu Hirata via llvm-commits
• [llvm] b2c8f66 - [Passes] Avoid repeated hash lookups (NFC) (#128828)   via llvm-commits
• [llvm] [Passes] Avoid repeated hash lookups (NFC) (PR #128828)   Kazu Hirata via llvm-commits
• [llvm] e264b0e - [ProfileData] Avoid repeated hash lookups (NFC) (#128829)   via llvm-commits
• [llvm] [ProfileData] Avoid repeated hash lookups (NFC) (PR #128829)   Kazu Hirata via llvm-commits
• [clang] [llvm] [clang] Always pass fp128 arguments indirectly on Windows (PR #115052)   Trevor Gross via llvm-commits
• [llvm] [Bitcode] Avoid repeated hash lookups (NFC) (PR #128824)   Kazu Hirata via llvm-commits
• [lld] [llvm] [lld] Fix -ObjC load behavior with LTO (PR #92162)   via llvm-commits
• [llvm] [Bitcode] Avoid repeated hash lookups (NFC) (PR #128824)   Kazu Hirata via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Correct RISCVTTIImpl::getIntImmCostInst for Zba (PR #128174)   Gergely Futo via llvm-commits
• [llvm] [llc] Report error in lieu of warning for invalid cl option (PR #128846)   Akshat Oke via llvm-commits
• [llvm] [windows] Always pass libcall fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [llvm] PeepholeOpt: Remove pointless check for subregister def (PR #128850)   Matt Arsenault via llvm-commits
• [llvm] PeepholeOpt: Remove pointless check for subregister def (PR #128850)   Matt Arsenault via llvm-commits
• [llvm] PeepholeOpt: Remove pointless check for subregister def (PR #128850)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (PR #128851)   Pierre van Houtryve via llvm-commits
• [llvm] [CodeGen][NPM] Allow nested MF pass managers for -passes (PR #128852)   Akshat Oke via llvm-commits
• [lld] [LLD][ELF] Generically report "address assignment did not converge" (PR #128774)   Peter Smith via llvm-commits
• [llvm] [AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (PR #128851)   via llvm-commits
• [llvm] [AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (PR #128851)   via llvm-commits
• [llvm] [CodeGen][NPM] Allow nested MF pass managers for -passes (PR #128852)   Akshat Oke via llvm-commits
• [llvm] [CodeGen][NPM] Allow nested MF pass managers for -passes (PR #128852)   Akshat Oke via llvm-commits
• [libcxx] [llvm] [libc++] Diagnose when nullptrs are passed to string APIs (PR #122790)   Nikolas Klauser via llvm-commits
• [llvm] [AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (PR #128851)   Matt Arsenault via llvm-commits
• [llvm] [SLP] Improve block traversal in getSpillCost() (PR #128620)   Alexey Bataev via llvm-commits
• [llvm] [AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (PR #128851)   Matt Arsenault via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   Benjamin Maxwell via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Sander de Smalen via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Sander de Smalen via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Sander de Smalen via llvm-commits
• [llvm] [LoopInterchange] Redundant isLexicographicallyPositive check (PR #117343)   Ryotaro Kasuga via llvm-commits
• [llvm] [LoopInterchange] Redundant isLexicographicallyPositive check (PR #117343)   Ryotaro Kasuga via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Virginia Cangelosi via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Paul Walker via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] 5cbff43 - [InstCombine] Test for trunc to i1 in foldLogOpOfMaskedICmps.   Andreas Jonson via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   Florian Hahn via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   Florian Hahn via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   Florian Hahn via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   Florian Hahn via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   Florian Hahn via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   Florian Hahn via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   Florian Hahn via llvm-commits
• [llvm] [CodeGen][ARM64EC] Mangle EH personality handler names (PR #121652)   Billy Laws via llvm-commits
• [llvm] [CodeGen][ARM64EC] Mangle EH personality handler names (PR #121652)   Billy Laws via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [CodeGen][ARM64EC] Mangle EH personality handler names (PR #121652)   Jacek Caban via llvm-commits
• [llvm] a98c294 - [X86] Handle multiple use freeze(undef) in LowerAVXCONCAT_VECTORS as zero vectors (#128830)   via llvm-commits
• [llvm] [X86] Handle multiple use freeze(undef) in LowerAVXCONCAT_VECTORS as zero vectors (PR #128830)   Phoebe Wang via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Virginia Cangelosi via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (PR #128233)   LLVM Continuous Integration via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [llvm] [NVPTX] Add intrinsics for st.bulk instruction (PR #128856)   Srinivasa Ravi via llvm-commits
• [llvm] [NVPTX] Add intrinsics for st.bulk instruction (PR #128856)   via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Simon Pilgrim via llvm-commits
• [llvm] [CodeGen][NPM] Port BranchFolder to NPM (PR #128858)   Akshat Oke via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   Katya Romanova via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   via llvm-commits
• [llvm] [X86][GlobalISel] Enable Trigonometric functions with libcall mapping (PR #126931)   via llvm-commits
• [llvm] [CodeGen][NPM] Port BranchFolder to NPM (PR #128858)   via llvm-commits
• [llvm] [CodeGen][NPM] Port BranchFolder to NPM (PR #128858)   via llvm-commits
• [llvm] [CodeGen][NPM] Port BranchFolder to NPM (PR #128858)   Akshat Oke via llvm-commits
• [llvm] [InstCombine] handle trunc to i1 in foldLogOpOfMaskedICmps. (PR #128861)   Andreas Jonson via llvm-commits
• [llvm] [InstCombine] handle trunc to i1 in foldLogOpOfMaskedICmps. (PR #128861)   via llvm-commits
• [llvm] [X86][GlobalISel] Enable Trigonometric functions with libcall mapping (PR #126931)   Simon Pilgrim via llvm-commits
• [llvm] 28cf323 - [LLVM] Port a few InstCombine tests to use splat instead of shufflevector.   Paul Walker via llvm-commits
• [llvm] 5756568 - [LLVM][AArch64] Reduce uses of "undef" in SVE InstCombine tests.   Paul Walker via llvm-commits
• [llvm] 6f2345a - [LLVM][AArch64] Change SVE CodeGen tests to use splat().   Paul Walker via llvm-commits
• [llvm] 01371d6 - [LLVM][AArch64] Reduce uses of "undef" in SVE CodeGen tests.   Paul Walker via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   Katya Romanova via llvm-commits
• [llvm] [InstCombine] handle trunc to i1 in foldLogOpOfMaskedICmps. (PR #128861)   Andreas Jonson via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Frederik Harwath via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Frederik Harwath via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Frederik Harwath via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Frederik Harwath via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Frederik Harwath via llvm-commits
• [llvm] [CodeGen][NPM] Port BranchFolder to NPM (PR #128858)   Akshat Oke via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Ricardo Jesus via llvm-commits
• [llvm] [LoopInterchange] Redundant isLexicographicallyPositive check (PR #117343)   Ryotaro Kasuga via llvm-commits
• [llvm] [CodeGen][NPM] Allow nested MF pass managers for -passes (PR #128852)   via llvm-commits
• [llvm] 178b9e5 - [MergeFunc] Add linkonce test with discardable functions.   Florian Hahn via llvm-commits
• [llvm] [AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (PR #128851)   Jay Foad via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Ricardo Jesus via llvm-commits
• [llvm] [VPlan] Introduce explicit broadcasts for live-ins. (PR #124644)   Florian Hahn via llvm-commits
• [llvm] [X86][GlobalISel] Enable Trigonometric functions with libcall mapping (PR #126931)   via llvm-commits
• [llvm] [X86][GlobalISel] Enable Trigonometric functions with libcall mapping (PR #126931)   via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Ricardo Jesus via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Paul Walker via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Ana Mihajlovic via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (PR #127212)   Ana Mihajlovic via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Ricardo Jesus via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Paul Walker via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Paul Walker via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Paul Walker via llvm-commits
• [llvm] [AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (PR #128851)   Pierre van Houtryve via llvm-commits
• [llvm] 5231736 - [AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)   via llvm-commits
• [llvm] [AMDGPU] Do not allow M0 as v_readlane_b32 dst (PR #128867)   Pierre van Houtryve via llvm-commits
• [llvm] [AMDGPU] Do not allow M0 as v_readlane_b32 dst (PR #128867)   via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Simon Pilgrim via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Ricardo Jesus via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Ricardo Jesus via llvm-commits
• [llvm] [Attributor] Do not optimize away externally_initialized loads. (PR #128170)   Pierre van Houtryve via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Ash Dobrescu via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Ash Dobrescu via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Ash Dobrescu via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Ash Dobrescu via llvm-commits
• [llvm] WIP: [Offload] Add testing for Offload program and kernel related entry points (PR #127803)   Callum Fare via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   Benjamin Maxwell via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Ash Dobrescu via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   Simon Pilgrim via llvm-commits
• [llvm] [Offload] Implement the remaining initial Offload API (PR #122106)   Callum Fare via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Michael Kruse via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Michael Kruse via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Michael Kruse via llvm-commits
• [llvm] [AMDGPU] Do not allow M0 as v_readlane_b32 dst (PR #128867)   Matt Arsenault via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Michael Kruse via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Phoebe Wang via llvm-commits
• [clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Luke Quinn via llvm-commits
• [llvm] aace6a2 - [RISCV] Xqcia 0.4 The spec was recently updated, this changes the name in the TD files associated and increments the Extension number in the clang driver. This is mostly a MC change as there is no other generated code for these instructions yet.   via llvm-commits
• [clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)   Luke Quinn via llvm-commits
• [llvm] [DependenceAnalysis] Extending SIV to handle separate loops (PR #128782)   Michael Kruse via llvm-commits
• [llvm] 0f0d3fb - [AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)   via llvm-commits
• [llvm] [AMDGPU] Do not allow M0 as v_readlane_b32 dst (PR #128867)   Pierre van Houtryve via llvm-commits
• [llvm] [LoongArch] use TypeWidenVector for most illegal vector types (PR #126456)   via llvm-commits
• [llvm] [LV][EVL] Support fixed-order recurrence idiom with EVL tail folding. (PR #124093)   Luke Lau via llvm-commits
• [llvm] [AArch64] Disable Pre-RA Scheduler for Neoverse V2 (PR #127784)   Sjoerd Meijer via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Frederik Harwath via llvm-commits
• [llvm] [IndVars] Fix high-cost-expand check in LFTR (PR #125828)   Ramkumar Ramachandra via llvm-commits
• [llvm] [IndVars] Fix high-cost-expand check in LFTR (PR #125828)   Ramkumar Ramachandra via llvm-commits
• [llvm] PeepholeOpt: Remove pointless check for subregister def (PR #128850)   Christudasan Devadasan via llvm-commits
• [llvm] [VPlan] Expand VPWidenIntOrFpInductionRecipe into separate recipes (PR #118638)   Luke Lau via llvm-commits
• [llvm] [VPlan] Expand VPWidenIntOrFpInductionRecipe into separate recipes (PR #118638)   Luke Lau via llvm-commits
• [llvm] 83ccab3 - PeepholeOpt: Remove pointless check for subregister def (#128850)   via llvm-commits
• [llvm] PeepholeOpt: Remove pointless check for subregister def (PR #128850)   Matt Arsenault via llvm-commits
• [llvm] [AArch64] Disable Pre-RA Scheduler for Neoverse V2 (PR #127784)   Sjoerd Meijer via llvm-commits
• [llvm] [CodeGen][NPM] Port BranchFolder to NPM (PR #128858)   Matt Arsenault via llvm-commits
• [llvm] [LoopVectorize] Use CodeSize as the cost kind for minsize (PR #124119)   John Brawn via llvm-commits
• [llvm] 3c4fa5a - [MergeFunc] Add tests showing incorrect handling of metadata call args.   Florian Hahn via llvm-commits
• [llvm] a5d8b7a - [AArch64] Improve urem by constant costs (#122236)   via llvm-commits
• [llvm] [AArch64] Improve urem by constant costs (PR #122236)   David Green via llvm-commits
• [llvm] [AArch64] Improve urem by constant costs (PR #122236)   David Green via llvm-commits
• [llvm] [SLP] SLP's copyable elements based upon Main/Alt operations. (PR #124242)   Dinar Temirbulatov via llvm-commits
• [llvm] [LLVM][SVE] Add isel for bfloat based (de)interleave operations. (PR #128875)   Paul Walker via llvm-commits
• [llvm] [LLVM][SVE] Add isel for bfloat based (de)interleave operations. (PR #128875)   via llvm-commits
• [llvm] [Offload] Implement the remaining initial Offload API (PR #122106)   Callum Fare via llvm-commits
• [llvm] [X86] Allow select(cond,pshufb,pshufb) -> or(pshufb,pshufb) fold to peek through bitcasts (PR #128876)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Allow select(cond,pshufb,pshufb) -> or(pshufb,pshufb) fold to peek through bitcasts (PR #128876)   via llvm-commits
• [llvm] 15fbdc2 - [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (#127837)   via llvm-commits
• [clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)   Ricardo Jesus via llvm-commits
• [llvm] 4277c21 - [VPlan] Introduce explicit broadcasts for live-ins. (#124644)   via llvm-commits
• [llvm] [VPlan] Introduce explicit broadcasts for live-ins. (PR #124644)   Florian Hahn via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Simon Pilgrim via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Sam Tebbs via llvm-commits
• [llvm] [X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (PR #128877)   via llvm-commits
• [llvm] [X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (PR #128877)   via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   via llvm-commits
• [llvm] [FuncComp] Compare MDNodes in cmpMetadata using cmpMDNode. (PR #128878)   Florian Hahn via llvm-commits
• [llvm] [FuncComp] Compare MDNodes in cmpMetadata using cmpMDNode. (PR #128878)   via llvm-commits
• [llvm] [X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (PR #128877)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   Simon Pilgrim via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   Virginia Cangelosi via llvm-commits
• [llvm] [RISCV] Move VMV0 elimination past machine SSA opts (PR #126850)   via llvm-commits
• [llvm] [LV] Optimise latch exit induction users for some early exit loops (PR #128880)   David Sherwood via llvm-commits
• [llvm] [LV] Optimise latch exit induction users for some early exit loops (PR #128880)   via llvm-commits
• [llvm] [llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (PR #128367)   Alex Voicu via llvm-commits
• [llvm] [llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (PR #128367)   Alex Voicu via llvm-commits
• [llvm] 8634635 - RegAllocFast: Stop reading uninitalized memory   Benjamin Kramer via llvm-commits
• [llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)   via llvm-commits
• [llvm] [CodeGen][NPM] Allow nested MF pass managers for -passes (PR #128852)   Akshat Oke via llvm-commits
• [llvm] [LLVM][SVE] Add isel for bfloat based select operations. (PR #128881)   Paul Walker via llvm-commits
• [clang] [llvm] [CaptureTracking][FunctionAttrs] Add support for CaptureInfo (PR #125880)   Nikita Popov via llvm-commits
• [llvm] [LLVM][SVE] Add isel for bfloat based select operations. (PR #128881)   via llvm-commits
• [llvm] 2c1df22 - RegAllocFast: Fix 8634635d689c5a7adfb19cde4a313d7c02e95194 to not trip assertions   Benjamin Kramer via llvm-commits
• [llvm] [RISCV] Move VMV0 elimination past machine SSA opts (PR #126850)   Luke Lau via llvm-commits
• [llvm] [PowerPC] custom lower v1024i1 load/store (PR #126969)   Lei Huang via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   David Sherwood via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   David Sherwood via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   David Sherwood via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   David Sherwood via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   David Sherwood via llvm-commits
• [llvm] workflows/release-binaries-all: Add missing secret input (PR #126921)   Tom Stellard via llvm-commits
• [llvm] workflows/release-binaries-all: Add missing secret input (PR #126921)   Tom Stellard via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   via llvm-commits
• [llvm] [CostModel][Test] Replace multiple flags with `-intrinsic-cost-strategy` (PR #128885)   Benjamin Maxwell via llvm-commits
• [llvm] workflows/release-binaries-all: Add missing secret input (PR #126921)   via llvm-commits
• [llvm] [CostModel][Test] Replace multiple flags with `-intrinsic-cost-strategy` (PR #128885)   via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [llvm] [LAA] Be more careful when evaluating AddRecs at symbolic max BTC. (PR #128061)   David Sherwood via llvm-commits
• [llvm] [RISCV] Move VMV0 elimination past machine SSA opts (PR #126850)   via llvm-commits
• [llvm] [llvm-diff] add optional call to IRNormalizer (PR #123314)   Serval MARTINOT-LAGARDE via llvm-commits
• [llvm] [LV] Fix tryToWiden logic for binop simplification (PR #128886)   Ramkumar Ramachandra via llvm-commits
• [llvm] [LV] Fix tryToWiden logic for binop simplification (PR #128886)   via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Benjamin Maxwell via llvm-commits
• [llvm] [LAA] Be more careful when evaluating AddRecs at symbolic max BTC. (PR #128061)   David Sherwood via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Benjamin Maxwell via llvm-commits
• [clang] [llvm] Reapply [CaptureTracking][FunctionAttrs] Add support for CaptureInfo (#125880) (PR #128020)   Nikita Popov via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Benjamin Maxwell via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Simon Pilgrim via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Benjamin Maxwell via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Benjamin Maxwell via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Simon Pilgrim via llvm-commits
• [llvm] [CostModel] Handle vector struct results and cost `llvm.sincos` (PR #123210)   Benjamin Maxwell via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] [CostModel][Test] Replace multiple flags with `-intrinsic-cost-strategy` (PR #128885)   David Sherwood via llvm-commits
• [llvm] [CostModel][Test] Replace multiple flags with `-intrinsic-cost-strategy` (PR #128885)   David Sherwood via llvm-commits
• [llvm] [CostModel][Test] Replace multiple flags with `-intrinsic-cost-strategy` (PR #128885)   David Sherwood via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   David Sherwood via llvm-commits
• [llvm] 7f33242 - [MemCpyOpt] Add stack move test with ret-only capture (NFC)   Nikita Popov via llvm-commits
• [llvm] [LV] Fix tryToWiden logic for binop simplification (PR #128886)   Ramkumar Ramachandra via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Teresa Johnson via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Teresa Johnson via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Teresa Johnson via llvm-commits
• [llvm] 1b17d1e - [X86] Allow select(cond,pshufb,pshufb) -> or(pshufb,pshufb) fold to peek through bitcasts (#128876)   via llvm-commits
• [llvm] [X86] Allow select(cond,pshufb,pshufb) -> or(pshufb,pshufb) fold to peek through bitcasts (PR #128876)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Simon Pilgrim via llvm-commits
• [llvm] [RISCV] Move VMV0 elimination past machine SSA opts (PR #126850)   Philip Reames via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   Krzysztof Drewniak via llvm-commits
• [llvm] 35bf925 - [RISCV] Delete dead COPYs to vmv0 during vmv0 elimination   Luke Lau via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] [ARM] Use correct ABI for atomic functions (PR #128891)   Oliver Stannard via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   Krzysztof Drewniak via llvm-commits
• [llvm] [ARM] Use correct ABI for atomic functions (PR #128891)   via llvm-commits
• [llvm] [ARM] Use correct ABI for atomic functions (PR #128891)   via llvm-commits
• [llvm] [RISCV] Move VMV0 elimination past machine SSA opts (PR #126850)   Luke Lau via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [lld] [llvm] [lld] Fix -ObjC load behavior with LTO (PR #92162)   Nuri Amari via llvm-commits
• [llvm] [MCA] Adding missing instructions in AArch64 Neoverse V1 tests (PR #128892)   Julien Villette via llvm-commits
• [llvm] [MCA] Adding missing instructions in AArch64 Neoverse V1 tests (PR #128892)   via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [clang] [llvm] Reapply [CaptureTracking][FunctionAttrs] Add support for CaptureInfo (#125880) (PR #128020)   Nikita Popov via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [llvm] [ARM] Use correct ABI for atomic functions (PR #128891)   via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [ARM] Use correct ABI for atomic functions (PR #128891)   Oliver Stannard via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] Expanding the Histogram Intrinsic (PR #127399)   via llvm-commits
• [llvm] [X86][GlobalISel] Enable Trigonometric functions with libcall mapping (PR #126931)   Evgenii Kudriashov via llvm-commits
• [llvm] [X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (PR #128877)   via llvm-commits
• [llvm] [X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (PR #128877)   via llvm-commits
• [llvm] Expanding the Histogram Intrinsic (PR #127399)   Florian Hahn via llvm-commits
• [llvm] [LLVM][SVE] Add isel for bfloat based (de)interleave operations. (PR #128875)   David Sherwood via llvm-commits
• [llvm] [LLVM][SVE] Add isel for bfloat based (de)interleave operations. (PR #128875)   David Sherwood via llvm-commits
• [llvm] [LLVM][SVE] Add isel for bfloat based (de)interleave operations. (PR #128875)   David Sherwood via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   Teresa Johnson via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   Teresa Johnson via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   Teresa Johnson via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   Teresa Johnson via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   Teresa Johnson via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Teresa Johnson via llvm-commits
• [llvm] [VPlan] Introduce explicit broadcasts for live-ins. (PR #124644)   via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [llvm] eeb8c20 - [X86] Fix a warning   Kazu Hirata via llvm-commits
• [llvm] [VPlan] Introduce explicit broadcasts for live-ins. (PR #124644)   via llvm-commits
• [llvm] [X86] Allow select(cond,pshufb,pshufb) -> or(pshufb,pshufb) fold to peek through bitcasts (PR #128876)   Kazu Hirata via llvm-commits
• [llvm] [RISCV] Move VMV0 elimination past machine SSA opts (PR #126850)   via llvm-commits
• [llvm] [LLVM][SVE] Add isel for bfloat based (de)interleave operations. (PR #128875)   Graham Hunter via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Virginia Cangelosi via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Benjamin Maxwell via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Benjamin Maxwell via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Philip Reames via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Philip Reames via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Philip Reames via llvm-commits
• [llvm] [LLVM][SVE] Add isel for bfloat based (de)interleave operations. (PR #128875)   Paul Walker via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   David Sherwood via llvm-commits
• [llvm] bb62af7 - [AMDGPU][True16][CodeGen] true16 codegen for valu op (#124797)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   Brox Chen via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] [X86][GlobalISel] Enable Trigonometric functions with libcall mapping (PR #126931)   via llvm-commits
• [llvm] [X86][GlobalISel] Enable Trigonometric functions with libcall mapping (PR #126931)   via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Philip Reames via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Nathan Gauër via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Teresa Johnson via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Teresa Johnson via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Teresa Johnson via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Teresa Johnson via llvm-commits
• [clang] [llvm] [CaptureTracking][FunctionAttrs] Add support for CaptureInfo (PR #125880)   Nikita Popov via llvm-commits
• [llvm] [X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (PR #128877)   Simon Pilgrim via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   LLVM Continuous Integration via llvm-commits
• [llvm] Expanding the Histogram Intrinsic (PR #127399)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   LLVM Continuous Integration via llvm-commits
• [llvm] [AMDGPU] Verify SdwaSel value range (PR #128898)   Frederik Harwath via llvm-commits
• [llvm] [AMDGPU] Verify SdwaSel value range (PR #128898)   via llvm-commits
• [llvm] [IR][Instructions] Add `CallBase::getCalledFunctionName` helper (PR #127038)   Thomas Symalla via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   LLVM Continuous Integration via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Frederik Harwath via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Ash Dobrescu via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Ash Dobrescu via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   Brox Chen via llvm-commits
• [llvm] [BOLT] Support computed goto and allow map addrs inside functions (PR #120267)   Ash Dobrescu via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Philip Reames via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Philip Reames via llvm-commits
• [llvm] [X86] combineINSERT_SUBVECTOR - use getBROADCAST_LOAD helper in insert_subvector(undef, broadcast(p), hi) -> broadcast(p) fold (PR #128900)   Simon Pilgrim via llvm-commits
• [llvm] [X86] combineINSERT_SUBVECTOR - use getBROADCAST_LOAD helper in insert_subvector(undef, broadcast(p), hi) -> broadcast(p) fold (PR #128900)   via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   Jose E. Marchesi via llvm-commits
• [clang] [llvm] [DebugInfo] Place local ODR-uniqued types in decl DISubprograms (PR #119001)   Vladislav Dzhidzhoev via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Florian Hahn via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Florian Hahn via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Florian Hahn via llvm-commits
• [llvm] [AMDGPU] Verify SdwaSel value range (PR #128898)   Matt Arsenault via llvm-commits
• [llvm] [PowerPC] custom lower v1024i1 load/store (PR #126969)   Lei Huang via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   Virginia Cangelosi via llvm-commits
• [llvm] 1ec1d25 - [MachineOutliner] Add skipModule call for opt-bisect-limit. (#128836)   via llvm-commits
• [llvm] [MachineOutliner] Add skipModule call for opt-bisect-limit. (PR #128836)   Craig Topper via llvm-commits
• [llvm] [CostModel][Test] Replace multiple flags with `-intrinsic-cost-strategy` (PR #128885)   Benjamin Maxwell via llvm-commits
• [llvm] [CostModel][Test] Replace multiple flags with `-intrinsic-cost-strategy` (PR #128885)   Benjamin Maxwell via llvm-commits
• [llvm] AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (PR #128903)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (PR #128903)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (PR #128903)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (PR #128903)   via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] truncate/ftruncate interception. (PR #128904)   David CARLIER via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] truncate/ftruncate interception. (PR #128904)   via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Craig Topper via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (PR #128905)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (PR #128905)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (PR #128905)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (PR #128905)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (PR #128905)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (PR #128905)   Brox Chen via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Benjamin Maxwell via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   Oliver Stannard via llvm-commits
• [llvm] [AMDGPU] Verify SdwaSel value range (PR #128898)   Frederik Harwath via llvm-commits
• [llvm] [SLP]Reduce number of alternate instruction, where possible (PR #128907)   via llvm-commits
• [llvm] [SLP]Reduce number of alternate instruction, where possible (PR #128907)   via llvm-commits
• [llvm] [DAGCombiner] Add some very basic folds for ADDRSPACECAST (PR #127733)   Alex MacLean via llvm-commits
• [llvm] [DAGCombiner] Add some very basic folds for ADDRSPACECAST (PR #127733)   Alex MacLean via llvm-commits
• [llvm] Calculate KnownBits from Metadata correctly for vector loads (PR #128908)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (PR #128905)   Matt Arsenault via llvm-commits
• [llvm] Calculate KnownBits from Metadata correctly for vector loads (PR #128908)   via llvm-commits
• [llvm] Calculate KnownBits from Metadata correctly for vector loads (PR #128908)   via llvm-commits
• [llvm] [DAGCombiner] Attempt to fold 'add' nodes to funnel-shift or rotate (PR #125612)   Alex MacLean via llvm-commits
• [llvm] [AArch64] Do not split bfloat HFA args between regs and stack (PR #128909)   Oliver Stannard via llvm-commits
• [llvm] [AArch64] Do not split bfloat HFA args between regs and stack (PR #128909)   via llvm-commits
• [llvm] Calculate KnownBits from Metadata correctly for vector loads (PR #128908)   Nikita Popov via llvm-commits
• [compiler-rt] [compiler-rt][test] Apply CFLAGS from sanitizer_common to all tests (PR #120798)   Aaron Puchert via llvm-commits
• [llvm] [X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (PR #128910)   Daniel Zabawa via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [llvm] dfda75f - [AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (#128905)   via llvm-commits
• [lld] [LLD][ELF] Generically report "address assignment did not converge" (PR #128774)   Fangrui Song via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (PR #128905)   Matt Arsenault via llvm-commits
• [llvm] 8039f8e - [RISCV][MC] Add assembler support for XRivosVisni (#128773)   via llvm-commits
• [clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)   Philip Reames via llvm-commits
• [llvm] [RISCV][Docs] RISCV -> RISC-V in RISCVUsage.rst. NFC (PR #128906)   Philip Reames via llvm-commits
• [llvm] LiveIntervals: Use BumpPtrAllocator (PR #127057)   Matt Arsenault via llvm-commits
• [llvm] [ARM] Use correct ABI for atomic functions (PR #128891)   Jon Roelofs via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   Craig Topper via llvm-commits
• [llvm] gisel lower fp64 to fp16 (PR #128911)   Brox Chen via llvm-commits
• [llvm] add v_cndmask_t16 to hazardmask (PR #128912)   Brox Chen via llvm-commits
• [llvm] [CodeGen][NPM] Port BranchFolder to NPM (PR #128858)   Christudasan Devadasan via llvm-commits
• [llvm] true16 codegen madmixpat GISEL (PR #124995)   Brox Chen via llvm-commits
• [llvm] gisel update (PR #128913)   Brox Chen via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] 8ffda96 - [RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models (#128786)   via llvm-commits
• [llvm] [RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models (PR #128786)   Min-Yih Hsu via llvm-commits
• [llvm] [AggressiveInstCombine] Shrink loads used in shufflevector rebroadcasts. (PR #128914)   Leon Clark via llvm-commits
• [llvm] [AggressiveInstCombine] Shrink loads used in shufflevector rebroadcasts. (PR #128914)   via llvm-commits
• [llvm] gisel update (PR #128913)   via llvm-commits
• [lld] 7ffeab3 - [LLD][ELF] Generically report "address assignment did not converge" (#128774)   via llvm-commits
• [lld] [LLD][ELF] Generically report "address assignment did not converge" (PR #128774)   Daniel Thornburgh via llvm-commits
• [llvm] [SLP]Reduce number of alternate instruction, where possible (PR #128907)   Alexey Bataev via llvm-commits
• [llvm] [X86][GlobalISel] Enable Trigonometric functions with libcall mapping (PR #126931)   Evgenii Kudriashov via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Craig Topper via llvm-commits
• [llvm] [InstCombine] Add support for GEPs in `simplifyNonNullOperand` (PR #128365)   via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Craig Topper via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   Fangrui Song via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   Ellis Hoag via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   via llvm-commits
• [llvm] gisel update (PR #128913)   Brox Chen via llvm-commits
• [llvm] [LLVM] Automatically strip `-fno-lifetime-dse` from compile_commands.json (PR #124623)   Fangrui Song via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Guy David via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [llvm] [LLVM] Automatically strip `-fno-lifetime-dse` from compile_commands.json (PR #124623)   Joseph Huber via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   via llvm-commits
• [llvm] [X86] combineINSERT_SUBVECTOR - use getBROADCAST_LOAD helper in insert_subvector(undef, broadcast(p), hi) -> broadcast(p) fold (PR #128900)   Simon Pilgrim via llvm-commits
• [llvm] fplower update (PR #128917)   Brox Chen via llvm-commits
• [llvm] check t16 in dpp inst creator (PR #128918)   Brox Chen via llvm-commits
• [llvm] [DAG] replaceShuffleOfInsert - add support for shuffle_vector(scalar_to_vector(x),y) -> insert_vector_elt(y,x,c) (PR #127210)   Simon Pilgrim via llvm-commits
• [llvm] 5d501c6 - [RISCV][Docs] RISCV -> RISC-V in RISCVUsage.rst. NFC (#128906)   via llvm-commits
• [llvm] [AArch64] Do not split bfloat HFA args between regs and stack (PR #128909)   David Green via llvm-commits
• [llvm] [RISCV][Docs] RISCV -> RISC-V in RISCVUsage.rst. NFC (PR #128906)   Craig Topper via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [llvm] check t16 in dpp inst creator (PR #128918)   via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #126331)   David Stuttard via llvm-commits
• [llvm] true16 for fold clamp (PR #128919)   Brox Chen via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   via llvm-commits
• [llvm] AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (PR #128903)   Christudasan Devadasan via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   Krzysztof Drewniak via llvm-commits
• [llvm] [X86][AsmParser] Improve rel8 validation (PR #126073)   via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Shilei Tian via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Lucas Ramirez via llvm-commits
• [llvm] [InstCombine] matchOrConcat - return Value* not Instruction* (PR #128921)   Simon Pilgrim via llvm-commits
• [llvm] [InstCombine] matchOrConcat - return Value* not Instruction* (PR #128921)   via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Shilei Tian via llvm-commits
• [llvm] [AMD][GISel] legalize `G_INSERT_SUBVECTOR` (PR #128922)   Maksim Levental via llvm-commits
• [llvm] AMDGPU: Do not try to commute instruction with same input register (PR #127562)   Shilei Tian via llvm-commits
• [llvm] [X86][AsmParser] Improve rel8 validation (PR #126073)   Simon Pilgrim via llvm-commits
• [llvm] [X86][AsmParser] Improve rel8 validation (PR #126073)   Simon Pilgrim via llvm-commits
• [llvm] [AMD][GISel] legalize `G_INSERT_SUBVECTOR` (PR #128923)   Maksim Levental via llvm-commits
• [llvm] [Symbolize] Always use filename:line from debug info when debug info for the given address is available. (PR #128619)   David Blaikie via llvm-commits
• [llvm] [AMD][GISel] legalize `G_INSERT_SUBVECTOR` (PR #128924)   Maksim Levental via llvm-commits
• [llvm] [AMD][GISel] legalize `G_INSERT_SUBVECTOR` (PR #128922)   Maksim Levental via llvm-commits
• [llvm] [AMD][GISel] legalize `G_INSERT_SUBVECTOR` (PR #128923)   Maksim Levental via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   LLVM Continuous Integration via llvm-commits
• [llvm] [AMD][GISel] legalize `G_INSERT_SUBVECTOR` (PR #128922)   via llvm-commits
• [llvm] [OFFLOAD] Update ffi_cif structure to match libffi (PR #128756)   via llvm-commits
• [llvm] [TargetInstrInfo] Add target hook for InstrSchedModel latency. [NFCI] (PR #128925)   Austin Kerbow via llvm-commits
• [llvm] [TargetInstrInfo] Add target hook for InstrSchedModel latency. [NFCI] (PR #128925)   Austin Kerbow via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #126331)   Adam Yang via llvm-commits
• [llvm] [AMD][GISel] legalize `G_INSERT_SUBVECTOR` (PR #128923)   via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [llvm] [AMD][GISel] legalize `G_INSERT_SUBVECTOR` (PR #128924)   via llvm-commits
• [llvm] [TargetInstrInfo] Add target hook for InstrSchedModel latency. [NFCI] (PR #128925)   via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] 159b872 - [llvm][telemetry]Change Telemetry-disabling mechanism. (#128534)   via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Vy Nguyen via llvm-commits
• [llvm] [DAG] replaceShuffleOfInsert - add support for shuffle_vector(scalar_to_vector(x),y) -> insert_vector_elt(y,x,c) (PR #127210)   via llvm-commits
• [llvm] [LV] Optimise latch exit induction users for some early exit loops (PR #128880)   Benjamin Maxwell via llvm-commits
• [llvm] [LV] Optimise latch exit induction users for some early exit loops (PR #128880)   Benjamin Maxwell via llvm-commits
• [llvm] [LV] Optimise latch exit induction users for some early exit loops (PR #128880)   Benjamin Maxwell via llvm-commits
• [llvm] [LV] Optimise latch exit induction users for some early exit loops (PR #128880)   Benjamin Maxwell via llvm-commits
• [llvm] [LV] Optimise latch exit induction users for some early exit loops (PR #128880)   Benjamin Maxwell via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Brox Chen via llvm-commits
• [llvm] [PowerPC] custom lower v1024i1 load/store (PR #126969)   via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Alan Li via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Alan Li via llvm-commits
• [llvm] insertwaitcnt pass update for true16 (PR #128927)   Brox Chen via llvm-commits
• [llvm] [DAG] replaceShuffleOfInsert - add support for shuffle_vector(scalar_to_vector(x),y) -> insert_vector_elt(y,x,c) (PR #127210)   Simon Pilgrim via llvm-commits
• [llvm] True16 Add OpSel when optimizing exec mask (PR #128928)   Brox Chen via llvm-commits
• [llvm] 4059faf - [TableGen] Update comment for size of NumToSkip field in DecoderEmitter. NFC   Craig Topper via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen]Support V2S copy with True16 flow (PR #118037)   Brox Chen via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   Amir Ayupov via llvm-commits
• [llvm] experiment to reduce extra COPY in sdag pattern (PR #126942)   Brox Chen via llvm-commits
• [llvm] 5a5a9e7 - [Telemetry] Fix a warning   Kazu Hirata via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Guy David via llvm-commits
• [llvm] true16 codegen madmixpat GISEL (PR #124995)   Brox Chen via llvm-commits
• [llvm] true16 codegen madmixpat (PR #124995)   Brox Chen via llvm-commits
• [llvm] G_Merge value and ICMP GISEL (PR #128913)   Brox Chen via llvm-commits
• [llvm] G_Merge value and ICMP GISEL (PR #128913)   Brox Chen via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   Kazu Hirata via llvm-commits
• [llvm] true16 codegen madmixpat (PR #124995)   Brox Chen via llvm-commits
• [llvm] 74306af - Fix the schedule of vectorizer improvement monthly sync   via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Peter Smith via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Peter Smith via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Peter Smith via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Peter Smith via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for madmixpat true16 pattern (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for madmixmods true16 pattern (PR #124995)   Brox Chen via llvm-commits
• [llvm] check t16 in dpp inst creator (PR #128918)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix-sgpr-copy pass update for 16bit sgpr in true16 flow (PR #118037)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix-sgpr-copy pass update for 16bit sgpr in true16 flow (PR #118037)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix-sgpr-copy pass update for 16bit sgpr in true16 flow (PR #118037)   Brox Chen via llvm-commits
• [llvm] AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (PR #128903)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Sebastian Pop via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [DirectX] Support the CBufferLoadLegacy operation (PR #128699)   LLVM Continuous Integration via llvm-commits
• [llvm] [RFC][BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fix-sgpr-copy pass update for 16bit sgpr in true16 flow (PR #118037)   Brox Chen via llvm-commits
• [llvm] [NFC][CodingStandard] Fix text style for C++ keywords (PR #128932)   Rahul Joshi via llvm-commits
• [llvm] [Dwarf][Transforms] Add dwarf support when func signature changed (PR #127855)   via llvm-commits
• [llvm] f6703a4 - [ctxprof] don't inline weak symbols after instrumentation (#128811)   via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   Mircea Trofin via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Min-Yih Hsu via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   LLVM Continuous Integration via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [llvm-objcopy] Let --change-section-lma change segments wth filesz=0,… (PR #127724)   Jonathon Penix via llvm-commits
• [llvm] [memprof] std::move matchings (NFC) (PR #128933)   Kazu Hirata via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Derek Schuff via llvm-commits
• [llvm] [memprof] std::move matchings (NFC) (PR #128933)   via llvm-commits
• [llvm] [libc][bazel] Add targets for stdbit functions (PR #128934)   Michael Jones via llvm-commits
• [llvm] cfdeca3 - [gn build] Port 8dd8e5f7d692 (BuiltinTemplates.td)   Nico Weber via llvm-commits
• [llvm] [libc][bazel] Add targets for stdbit functions (PR #128934)   via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] [llvm-objcopy] Let --change-section-lma change segments wth filesz=0,… (PR #127724)   Jonathon Penix via llvm-commits
• [llvm] [memprof] std::move matchings (NFC) (PR #128933)   Snehasish Kumar via llvm-commits
• [llvm] [memprof] std::move matchings (NFC) (PR #128933)   Snehasish Kumar via llvm-commits
• [llvm] [memprof] std::move matchings (NFC) (PR #128933)   Snehasish Kumar via llvm-commits
• [llvm] [llvm-objcopy] Let --change-section-lma change segments wth filesz=0,… (PR #127724)   Jonathon Penix via llvm-commits
• [llvm] [X86][AsmParser] Improve rel8 validation (PR #126073)   Evgenii Kudriashov via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] DAG: Preserve range metadata when load is narrowed (PR #128144)   Thurston Dang via llvm-commits
• [clang] [llvm] [HLSL][RootSignature] Implement Parsing of Descriptor Tables (PR #122982)   Joshua Batista via llvm-commits
• [llvm] [LoopVectorize] Use CodeSize as the cost kind for minsize (PR #124119)   Florian Hahn via llvm-commits
• [llvm] [libc][bazel] Add targets for stdbit functions (PR #128934)   Alexey Samsonov via llvm-commits
• [llvm] [libc][bazel] Add targets for stdbit functions (PR #128934)   Alexey Samsonov via llvm-commits
• [llvm] [libc][bazel] Add targets for stdbit functions (PR #128934)   Alexey Samsonov via llvm-commits
• [llvm] [docs] Add Included Suites to Test Suite Guide (PR #128937)   Sam Elliott via llvm-commits
• [llvm] [docs] Add Included Suites to Test Suite Guide (PR #128937)   Sam Elliott via llvm-commits
• [llvm] [ctxprof] don't inline weak symbols after instrumentation (PR #128811)   LLVM Continuous Integration via llvm-commits
• [llvm] [X86][AsmParser] Improve rel8 validation (PR #126073)   Evgenii Kudriashov via llvm-commits
• [llvm] [DAGCombiner] Add some very basic folds for ADDRSPACECAST (PR #127733)   Artem Belevich via llvm-commits
• [llvm] [X86][AsmParser] Improve rel8 validation (PR #126073)   Evgenii Kudriashov via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [libc][bazel] Add targets for stdbit functions (PR #128934)   Michael Jones via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Craig Topper via llvm-commits
• [llvm] [AggressiveInstCombine] Shrink loads used in shufflevector rebroadcasts. (PR #128938)   Leon Clark via llvm-commits
• [llvm] [AggressiveInstCombine] Shrink loads used in shufflevector rebroadcasts. (PR #128938)   via llvm-commits
• [llvm] DAG: Preserve range metadata when load is narrowed (PR #128144)   via llvm-commits
• [llvm] [VectorCombine] support mismatching extract/insert indices for foldInsExtFNeg (PR #126408)   via llvm-commits
• [lldb] [llvm] [llvm][telemetry]Change Telemetry-disabling mechanism. (PR #128534)   LLVM Continuous Integration via llvm-commits
• [llvm] [memprof] std::move matchings (NFC) (PR #128933)   Kazu Hirata via llvm-commits
• [llvm] [memprof] std::move matchings (NFC) (PR #128933)   Kazu Hirata via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Mircea Trofin via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Mircea Trofin via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Mircea Trofin via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Mircea Trofin via llvm-commits
• [llvm] [DAGCombiner] Add some very basic folds for ADDRSPACECAST (PR #127733)   Kai Nacke via llvm-commits
• [llvm] [llvm-size] Add test for invalid conversion spec on error (PR #128941)   Vitaly Buka via llvm-commits
• [llvm] [llvm-size] Add test for invalid conversion spec on error (PR #128941)   via llvm-commits
• [llvm] [AMDGPU] Set inst_pref_size to maximum (PR #126981)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Florian Hahn via llvm-commits
• [llvm] [DAGCombiner] Add some very basic folds for ADDRSPACECAST (PR #127733)   Kai Nacke via llvm-commits
• [llvm] [windows] Always pass libcall fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [lld] [llvm] ldd(wasm): Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [llvm] [DAGCombiner] Add some very basic folds for ADDRSPACECAST (PR #127733)   Kai Nacke via llvm-commits
• [lld] [llvm] ldd(wasm): Support for the custom-page-sizes WebAssembly proposal (PR #128942)   via llvm-commits
• [lld] [llvm] ldd(wasm): Support for the custom-page-sizes WebAssembly proposal (PR #128942)   via llvm-commits
• [lld] [llvm] ldd(wasm): Support for the custom-page-sizes WebAssembly proposal (PR #128942)   via llvm-commits
• [lld] [llvm] ldd(wasm): Support for the custom-page-sizes WebAssembly proposal (PR #128942)   via llvm-commits
• [llvm] [windows] Always pass libcall fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] [LV] Optimise latch exit induction users for some early exit loops (PR #128880)   Florian Hahn via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [lld] [llvm] ldd(wasm): Support for the custom-page-sizes WebAssembly proposal (PR #128942)   via llvm-commits
• [llvm] be28365 - [LV] Generate check lines for if-conversion.ll   Florian Hahn via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   Florian Hahn via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] [BOLT] Build CFG for non-simple functions in aggregation mode (PR #128944)   Amir Ayupov via llvm-commits
• [llvm] [BOLT] Build CFG for non-simple functions in aggregation mode (PR #128944)   via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Sebastian Pop via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)   Ramkumar Ramachandra via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Sebastian Pop via llvm-commits
• [llvm] [BOLT] Build CFG for non-simple functions in aggregation mode (PR #128944)   Amir Ayupov via llvm-commits
• [llvm] [libc][bazel] Add targets for stdbit functions (PR #128934)   Michael Jones via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Florian Hahn via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Teresa Johnson via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] 7b6abd8 - [LV] Remove stray check lines after be28365ca78.   Florian Hahn via llvm-commits
• [llvm] 364b97f - [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (#128060)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)   Brox Chen via llvm-commits
• [llvm] [DirectX] initialize registers properties by calling addRegisterClass and computeRegisterProperties (PR #128818)   via llvm-commits
• [llvm] [DirectX] initialize registers properties by calling addRegisterClass and computeRegisterProperties (PR #128818)   via llvm-commits
• [llvm] Introducing a new ISD::POISON SDNode to represent the poison value in the IR. (PR #125883)   zhijian lin via llvm-commits
• [clang] [llvm] [AggressiveInstCombine] Shrink loads used in shufflevector rebroadcasts. (PR #128938)   Leon Clark via llvm-commits
• [clang] [llvm] [OpenEmbedded] Fix include and lib paths for multilib targets (PR #121302)   Mike Crowe via llvm-commits
• [clang] [llvm] [AggressiveInstCombine] Shrink loads used in shufflevector rebroadcasts. (PR #128938)   via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Florian Hahn via llvm-commits
• [llvm] [FuncComp] Compare MDNodes in cmpMetadata using cmpMDNode. (PR #128878)   Nikita Popov via llvm-commits
• [llvm] [FuncComp] Compare MDNodes in cmpMetadata using cmpMDNode. (PR #128878)   Nikita Popov via llvm-commits
• [llvm] [FuncComp] Compare MDNodes in cmpMetadata using cmpMDNode. (PR #128878)   Nikita Popov via llvm-commits
• [llvm] [FuncComp] Compare MDNodes in cmpMetadata using cmpMDNode. (PR #128878)   Nikita Popov via llvm-commits
• [llvm] [FuncComp] Compare MDNodes in cmpMetadata using cmpMDNode. (PR #128878)   Nikita Popov via llvm-commits
• [llvm] [FuncComp] Compare MDNodes in cmpMetadata using cmpMDNode. (PR #128878)   Nikita Popov via llvm-commits
• [llvm] [FuncComp] Compare MDNodes in cmpMetadata using cmpMDNode. (PR #128878)   Nikita Popov via llvm-commits
• [llvm] [FuncComp] Compare MDNodes in cmpMetadata using cmpMDNode. (PR #128878)   Nikita Popov via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Florian Hahn via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Florian Hahn via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Florian Hahn via llvm-commits
• [llvm] 418a987 - [SLP]Do not use node, if it is a subvector or buildvector node   Alexey Bataev via llvm-commits
• [llvm] [InstCombine] matchOrConcat - return Value* not Instruction* (PR #128921)   Nikita Popov via llvm-commits
• [llvm] [llvm] replace static_assert with std::enable_if_t in ilist_node_impl (PR #127722)   Andrew Rogers via llvm-commits
• [llvm] workflows/release-binaries: Fix macos-14 build (PR #127157)   Tom Stellard via llvm-commits
• [llvm] workflows/release-binaries: Fix macos-14 build (PR #127157)   Tom Stellard via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Nicolai Hähnle via llvm-commits
• [llvm] [JumpThreading] Remove deleted BB from Unreachable (PR #126984)   Nikita Popov via llvm-commits
• [llvm] [llvm] replace static_assert with std::enable_if_t in ilist_node_impl (PR #127722)   Jakub Kuderski via llvm-commits
• [llvm] [RFC][BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [clang] [llvm] [AggressiveInstCombine] Shrink loads used in shufflevector rebroadcasts. (PR #128938)   Nikita Popov via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   via llvm-commits
• [llvm] workflows/release-binaries: Fix macos-14 build (PR #127157)   via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   via llvm-commits
• [llvm] [DAGCombiner] Add some very basic folds for ADDRSPACECAST (PR #127733)   Kai Nacke via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] workflows/release-binaries: Limit the number of projects built for pull requests (PR #128947)   Tom Stellard via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Justin Bogner via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Justin Bogner via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Mircea Trofin via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   via llvm-commits
• [llvm] [DirectX] initialize registers properties by calling addRegisterClass and computeRegisterProperties (PR #128818)   Justin Bogner via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Mircea Trofin via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Teresa Johnson via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Mircea Trofin via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Teresa Johnson via llvm-commits
• [llvm] DAG: Preserve range metadata when load is narrowed (PR #128144)   Daniel Thornburgh via llvm-commits
• [llvm] Revert "DAG: Preserve range metadata when load is narrowed" (PR #128948)   Daniel Thornburgh via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [llvm] Revert "DAG: Preserve range metadata when load is narrowed" (PR #128948)   via llvm-commits
• [llvm] Revert "DAG: Preserve range metadata when load is narrowed" (PR #128948)   via llvm-commits
• [llvm] 469757e - [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (#126621)   via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   Krzysztof Drewniak via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] 147d9d6 - [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (#128564)   via llvm-commits
• [llvm] [WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (PR #128564)   Sam Clegg via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [llvm] [AMD][GISel] legalize `G_INSERT_SUBVECTOR` (PR #128924)   Maksim Levental via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [llvm] 0212834 - Revert "DAG: Preserve range metadata when load is narrowed" (#128948)   via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   LLVM Continuous Integration via llvm-commits
• [llvm] Revert "DAG: Preserve range metadata when load is narrowed" (PR #128948)   Daniel Thornburgh via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   LLVM Continuous Integration via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   LLVM Continuous Integration via llvm-commits
• [llvm] 39bab1d - [SLP]Check if the operand for removal is the reduction operand, awaiting for the reduction   Alexey Bataev via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   LLVM Continuous Integration via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   Sam Elliott via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   LLVM Continuous Integration via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Deric Cheung via llvm-commits
• [llvm] [DWARFLinker] Adjust DW_AT_LLVM_stmt_sequence for rewritten line tables (PR #128953)   via llvm-commits
• [llvm] ff80bdc - [RISCV] Adding missing P600 sched model test for RVV segmented loads/stores   Min-Yih Hsu via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Craig Topper via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] truncate/ftruncate interception. (PR #128904)   Chris Apple via llvm-commits
• [llvm] [DWARFLinker] Adjust DW_AT_LLVM_stmt_sequence for rewritten line tables (PR #128953)   via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] effd7f0 - [gn build] Port 8fb88f568011   LLVM GN Syncbot via llvm-commits
• [llvm] [DWARFLinker] Adjust DW_AT_LLVM_stmt_sequence for rewritten line tables (PR #128953)   via llvm-commits
• [compiler-rt] f3b4d94 - [compiler-rt][rtsan] truncate/ftruncate interception. (#128904)   via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] truncate/ftruncate interception. (PR #128904)   David CARLIER via llvm-commits
• [llvm] [libc][bazel] Add targets for strfrom<float> (PR #128956)   Michael Jones via llvm-commits
• [llvm] [libc][bazel] Add targets for strfrom<float> (PR #128956)   via llvm-commits
• [llvm] 26ac742 - [memprof] std::move matchings (NFC) (#128933)   via llvm-commits
• [llvm] [memprof] std::move matchings (NFC) (PR #128933)   Kazu Hirata via llvm-commits
• [llvm] [libc][bazel] Add targets for strfrom<float> (PR #128956)   Alexey Samsonov via llvm-commits
• [llvm] [libc][bazel] Add targets for strfrom<float> (PR #128956)   Alexey Samsonov via llvm-commits
• [llvm] [llvm] replace static_assert with std::enable_if_t in ilist_node_impl (PR #127722)   Saleem Abdulrasool via llvm-commits
• [llvm] [MachinePipeliner] Fix loop-carried dependencies analysis (PR #121907)   via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [libc][bazel] Add targets for strfrom<float> (PR #128956)   Michael Jones via llvm-commits
• [llvm] d708bfb - AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (#128903)   via llvm-commits
• [llvm] AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (PR #128903)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   LLVM Continuous Integration via llvm-commits
• [llvm] [JumpThreading] Remove deleted BB from Unreachable (PR #126984)   via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   LLVM Continuous Integration via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Sam Elliott via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Sam Elliott via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Sam Elliott via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Guy David via llvm-commits
• [llvm] [AMDGPU][MC] Disassembler warning for v_cmpx instructions (PR #127925)   Jun Wang via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Guy David via llvm-commits
• [llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)   Guy David via llvm-commits
• [llvm] [llvm] replace static_assert with std::enable_if_t in ilist_node_impl (PR #127722)   Jakub Kuderski via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   LLVM Continuous Integration via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] AMDGPU: Do not try to commute instruction with same input register (PR #127562)   Matt Arsenault via llvm-commits
• [llvm] [SLP] SLP's copyable elements based upon Main/Alt operations. (PR #124242)   Alexey Bataev via llvm-commits
• [llvm] [Github] Demo premerge PR (PR #125886)   Aiden Grossman via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Eli Friedman via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Mircea Trofin via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] true16 codegen for valu op (PR #124797)   LLVM Continuous Integration via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Min-Yih Hsu via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   via llvm-commits
• [llvm] [LoongArch] use TypeWidenVector for most illegal vector types (PR #126456)   via llvm-commits
• [llvm] [LLVM] Automatically strip `-fno-lifetime-dse` from compile_commands.json (PR #124623)   Sam James via llvm-commits
• [llvm] [AMDGPU][MC] Disassembler warning for v_cmpx instructions (PR #127925)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Craig Topper via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Do not try to commute instruction with same input register (PR #127562)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Craig Topper via llvm-commits
• [llvm] AMDGPU: Do not try to commute instruction with same input register (PR #127562)   Matt Arsenault via llvm-commits
• [llvm] 4be4133 - AMDGPU: Do not try to commute instruction with same input register (#127562)   via llvm-commits
• [llvm] AMDGPU: Do not try to commute instruction with same input register (PR #127562)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Fix overly conservative immediate operand check (PR #127563)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Fix overly conservative immediate operand check (PR #127563)   Matt Arsenault via llvm-commits
• [llvm] a316539 - AMDGPU: Fix overly conservative immediate operand check (#127563)   via llvm-commits
• [llvm] AMDGPU: Fix overly conservative immediate operand check (PR #127563)   Matt Arsenault via llvm-commits
• [llvm] [BOLT][instr] Avoid WX segment (PR #128982)   YongKang Zhu via llvm-commits
• [llvm] [BOLT][instr] Avoid WX segment (PR #128982)   via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Craig Topper via llvm-commits
• [llvm] LangRef: Clarify llvm.minnum and llvm.maxnum about sNaN and signed zero (PR #112852)   YunQiang Su via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   Sudharsan Veeravalli via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   Sudharsan Veeravalli via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   Sudharsan Veeravalli via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   Sudharsan Veeravalli via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Craig Topper via llvm-commits
• [llvm] LangRef: Clarify llvm.minnum and llvm.maxnum about sNaN and signed zero (PR #112852)   Matt Arsenault via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Farzon Lotfi via llvm-commits
• [llvm] 12c7908 - [ORC] De-duplicate some logic for handling MachO::dylib-based load commands.   Lang Hames via llvm-commits
• [llvm] 2e6d9af - [ORC] Support adding LC_LOAD_WEAK_DYLIB commands to MachO JITDylib headers.   Lang Hames via llvm-commits
• [llvm] 20cea4d - [ORC] Sink include into implementation file.   Lang Hames via llvm-commits
• [llvm] 4c9f6a7 - [X86][GlobalISel] Enable Trigonometric functions with libcall mapping (#126931)   via llvm-commits
• [llvm] [X86][GlobalISel] Enable Trigonometric functions with libcall mapping (PR #126931)   Matt Arsenault via llvm-commits
• [llvm] 363b059 - LangRef: Clarify llvm.minnum and llvm.maxnum about sNaN and signed zero (#112852)   via llvm-commits
• [llvm] LangRef: Clarify llvm.minnum and llvm.maxnum about sNaN and signed zero (PR #112852)   YunQiang Su via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Phoebe Wang via llvm-commits
• [llvm] [DAGCombiner] Add some very basic folds for ADDRSPACECAST (PR #127733)   Matt Arsenault via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Teresa Johnson via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Teresa Johnson via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Teresa Johnson via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (PR #128877)   Phoebe Wang via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Mircea Trofin via llvm-commits
• [llvm] eb1c3ac - [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (#128940)   via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   Mircea Trofin via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Sam Elliott via llvm-commits
• [llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)   via llvm-commits
• [llvm] [InstCombine] matchOrConcat - return Value* not Instruction* (PR #128921)   Yingwei Zheng via llvm-commits
• [llvm] 5066d7b - [RISCV] Add Xqccmp 0.1 Assembly Support (#128731)   via llvm-commits
• [clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)   Sam Elliott via llvm-commits
• [llvm] [ctxprof] Override type of instrumentation if `-profile-context-root` is specified (PR #128940)   LLVM Continuous Integration via llvm-commits
• [llvm] LangRef: Claim llvm.{vp.,}vector.reduce.f{min,max} as deprecated (PR #118730)   YunQiang Su via llvm-commits
• [llvm] LangRef: Claim llvm.{vp.,}vector.reduce.f{min,max} as deprecated (PR #118730)   YunQiang Su via llvm-commits
• [clang] [llvm] [WIP] Correct lowering of `fp128` intrinsics (PR #76558)   Trevor Gross via llvm-commits
• [llvm] [SLP]Reduce number of alternate instruction, where possible (PR #128907)   via llvm-commits
• [clang] [lldb] [llvm] Extending LLDB to work on AIX (PR #102601)   via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [llvm] [ARM] Avoid repeated hash lookups (NFC) (PR #128994)   Kazu Hirata via llvm-commits
• [llvm] [ARM] Avoid repeated hash lookups (NFC) (PR #128994)   via llvm-commits
• [llvm] [AsmPrinter] Avoid repeated hash lookups (NFC) (PR #128995)   Kazu Hirata via llvm-commits
• [llvm] [ExecutionEngine] Avoid repeated hash lookups (NFC) (PR #128997)   Kazu Hirata via llvm-commits
• [llvm] [IR] Avoid repeated hash lookups (NFC) (PR #128998)   Kazu Hirata via llvm-commits
• [llvm] [IR] Avoid repeated hash lookups (NFC) (PR #128998)   via llvm-commits
• [llvm] [SelectionDAG] Avoid repeated hash lookups (NFC) (PR #128999)   Kazu Hirata via llvm-commits
• [llvm] [Support] Avoid repeated hash lookups (NFC) (PR #129000)   Kazu Hirata via llvm-commits
• [llvm] [SelectionDAG] Avoid repeated hash lookups (NFC) (PR #128999)   via llvm-commits
• [llvm] [Support] Avoid repeated hash lookups (NFC) (PR #129000)   via llvm-commits
• [llvm] [SelectionDAG] Avoid repeated hash lookups (NFC) (PR #128999)   Matt Arsenault via llvm-commits
• [llvm] [Support] Avoid repeated hash lookups (NFC) (PR #129000)   via llvm-commits
• [llvm] [SelectionDAG] Avoid repeated hash lookups (NFC) (PR #128999)   Craig Topper via llvm-commits
• [llvm] [LV][EVL] Generate negative strided load/store for reversed load/store (PR #123608)   Elvis Wang via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   LLVM Continuous Integration via llvm-commits
• [llvm] [AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (PR #126621)   LLVM Continuous Integration via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [llvm] AMDGPU/GlobalISel: Restore disabled test (PR #129001)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU/GlobalISel: Restore disabled test (PR #129001)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU/GlobalISel: Restore disabled test (PR #129001)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU/GlobalISel: Restore disabled test (PR #129001)   via llvm-commits
• [llvm] AMDGPU: Factor agpr reg_sequence folding into a function (PR #129002)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Factor agpr reg_sequence folding into a function (PR #129002)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Factor agpr reg_sequence folding into a function (PR #129002)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Factor agpr reg_sequence folding into a function (PR #129002)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Factor agpr reg_sequence folding into a function (PR #129002)   via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Carl Ritson via llvm-commits
• [clang] [llvm] APFloat: Fix maxnum and minnum with sNaN (PR #112854)   YunQiang Su via llvm-commits
• [clang] [llvm] APFloat: Fix maxnum and minnum with sNaN (PR #112854)   YunQiang Su via llvm-commits
• [clang] [llvm] APFloat: Fix maxnum and minnum with sNaN (PR #112854)   Matt Arsenault via llvm-commits
• [compiler-rt] [asan][win] Fix CreateThread leak (PR #126738)   Vitaly Buka via llvm-commits
• [compiler-rt] [asan][win] Fix CreateThread leak (PR #126738)   Vitaly Buka via llvm-commits
• [compiler-rt] [compiler-rt][sanitizer_common] copy_file_range syscall interception. (PR #125816)   Vitaly Buka via llvm-commits
• [llvm] [msan] Add experimental '-msan-or-shadow-for-strict-instructions' flag to pessimize output (PR #128036)   Vitaly Buka via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #126331)   Carl Ritson via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   Sudharsan Veeravalli via llvm-commits
• [llvm] [msan] Generalize handlePairwiseShadowOrIntrinsic, and handle x86 pairwise add/sub (PR #127567)   Vitaly Buka via llvm-commits
• [llvm] [SelectionDAG] Avoid repeated hash lookups (NFC) (PR #128999)   Kazu Hirata via llvm-commits
• [llvm] [Bitcode] Avoid repeated hash lookups (NFC) (PR #128824)   Kazu Hirata via llvm-commits
• [compiler-rt] Augment `uncaught-exception.test` fuzzer test to be msvc-compatible (PR #125924)   Vitaly Buka via llvm-commits
• [llvm] [msan][NFCI] Add tests for Arm NEON vector load (PR #125267)   Vitaly Buka via llvm-commits
• [lld] [llvm] [lld] Fix -ObjC load behavior with LTO (PR #92162)   via llvm-commits
• [compiler-rt] 5f6a3e6 - [compiler-rt][sanitizer_common] copy_file_range syscall interception. (#125816)   via llvm-commits
• [compiler-rt] [compiler-rt][sanitizer_common] copy_file_range syscall interception. (PR #125816)   David CARLIER via llvm-commits
• [clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)   Jessica Clarke via llvm-commits
• [llvm] [SelectionDAG] Avoid repeated hash lookups (NFC) (PR #128999)   Kazu Hirata via llvm-commits
• [llvm] [SelectionDAG] Avoid repeated hash lookups (NFC) (PR #128999)   Kazu Hirata via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Yingwei Zheng via llvm-commits
• [llvm] [SelectionDAG] Avoid repeated hash lookups (NFC) (PR #128999)   Craig Topper via llvm-commits
• [llvm] [CodeGen][NewPM] Port "RemoveRedundantDebugValues" to NPM (PR #129005)   Vikram Hegde via llvm-commits
• [llvm] [CodeGen][NewPM] Port "RemoveRedundantDebugValues" to NPM (PR #129005)   via llvm-commits
• [llvm] [InstCombine] handle trunc to i1 in foldLogOpOfMaskedICmps. (PR #128861)   Yingwei Zheng via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Alex MacLean via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Alex MacLean via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Alex MacLean via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Alex MacLean via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Alex MacLean via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Alex MacLean via llvm-commits
• [llvm] [Mips] Allow expressions in some immediate operands (PR #127581)   Fangrui Song via llvm-commits
• [llvm] 5d404d7 - [msan] Generalize handlePairwiseShadowOrIntrinsic, and handle x86 pairwise add/sub (#127567)   via llvm-commits
• [llvm] [msan] Generalize handlePairwiseShadowOrIntrinsic, and handle x86 pairwise add/sub (PR #127567)   Thurston Dang via llvm-commits
• [compiler-rt] [compiler-rt][sanitizer_common] copy_file_range syscall interception. (PR #125816)   David CARLIER via llvm-commits
• [lld] [LLD][ELF][RISCV] Handle .note.gnu.property sections for Zicfilp/Zicfiss features (PR #127193)   Fangrui Song via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [lld] [LLD][ELF][RISCV] Handle .note.gnu.property sections for Zicfilp/Zicfiss features (PR #127193)   Fangrui Song via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [llvm] [X86][AsmParser] Improve rel8 validation (PR #126073)   Phoebe Wang via llvm-commits
• [llvm] [CodeGen][NewPM] Port "RemoveRedundantDebugValues" to NPM (PR #129005)   Christudasan Devadasan via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Han-Kuan Chen via llvm-commits
• [llvm] 88ff607 - APFloat: Fix maxnum and minnum with sNaN (#112854)   via llvm-commits
• [clang] [llvm] APFloat: Fix maxnum and minnum with sNaN (PR #112854)   YunQiang Su via llvm-commits
• [llvm] [CodeGen][NewPM] Port "RemoveRedundantDebugValues" to NPM (PR #129005)   Matt Arsenault via llvm-commits
• [compiler-rt] [compiler-rt][sanitizer_common] fix copy_file_range test. (PR #129010)   David CARLIER via llvm-commits
• [clang] [llvm] Clang: emit llvm.minnum and llvm.maxnum with nsz always (PR #113133)   YunQiang Su via llvm-commits
• [compiler-rt] [compiler-rt][sanitizer_common] fix copy_file_range test. (PR #129010)   via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [llvm] [NVPTX] Add intrinsics for st.bulk instruction (PR #128856)   Srinivasa Ravi via llvm-commits
• [lld] [LLD][ELF][RISCV] Handle .note.gnu.property sections for Zicfilp/Zicfiss features (PR #127193)   Ming-Yi Lai via llvm-commits
• [llvm] [RISCV] Handle zvbb instructions in getVectorLowDemandedScalarBits. (PR #129011)   Jim Lin via llvm-commits
• [llvm] [RISCV] Handle zvbb instructions in getVectorLowDemandedScalarBits. (PR #129011)   via llvm-commits
• [compiler-rt] [compiler-rt][sanitizer_common] copy_file_range syscall interception. (PR #125816)   LLVM Continuous Integration via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] Introducing a new ISD::POISON SDNode to represent the poison value in the IR. (PR #125883)   Matt Arsenault via llvm-commits
• [llvm] Introducing a new ISD::POISON SDNode to represent the poison value in the IR. (PR #125883)   Matt Arsenault via llvm-commits
• [llvm] Introducing a new ISD::POISON SDNode to represent the poison value in the IR. (PR #125883)   Matt Arsenault via llvm-commits
• [lld] [LLD][ELF][RISCV] Handle .note.gnu.property sections for Zicfilp/Zicfiss features (PR #127193)   Ming-Yi Lai via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Matt Arsenault via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Matt Arsenault via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Matt Arsenault via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Matt Arsenault via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen][NewPM] Port "RemoveRedundantDebugValues" to NPM (PR #129005)   Akshat Oke via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Jim Lin via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Jim Lin via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Jim Lin via llvm-commits
• [llvm] [RFC][BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [llvm] Optimize fptrunc(x)>=C1 --> x>=C2 (PR #99475)   via llvm-commits
• [llvm] [ARM] Use correct ABI for atomic functions (PR #128891)   Matt Arsenault via llvm-commits
• [llvm] [ARM] Use correct ABI for atomic functions (PR #128891)   Matt Arsenault via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   Vitaly Buka via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   via llvm-commits
• [llvm] [RISCV] Handle zvbb instructions in getVectorLowDemandedScalarBits. (PR #129011)   Craig Topper via llvm-commits
• [llvm] [AMDGPU][NPM] Port SIModeRegister to NPM (PR #129014)   Akshat Oke via llvm-commits
• [llvm] [AMDGPU][NPM] Port SIModeRegister to NPM (PR #129014)   Akshat Oke via llvm-commits
• [llvm] [AMDGPU][NPM] Port SIModeRegister to NPM (PR #129014)   Akshat Oke via llvm-commits
• [llvm] [AMDGPU][NPM] Port SIModeRegister to NPM (PR #129014)   Akshat Oke via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   via llvm-commits
• [llvm] [AMDGPU][NPM] Port SIModeRegister to NPM (PR #129014)   via llvm-commits
• [llvm] [AMDGPU][NPM] Port SIModeRegister to NPM (PR #129014)   Akshat Oke via llvm-commits
• [llvm] [RISCV] Handle zvbb instructions in getVectorLowDemandedScalarBits. (PR #129011)   Luke Lau via llvm-commits
• [compiler-rt] [asan][win] Fix CreateThread leak (PR #126738)   via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++][ranges] P2542R8: Implement `views::concat` (PR #120920)   Nhat Nguyen via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Luke Lau via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Luke Lau via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Luke Lau via llvm-commits
• [llvm] [NVPTX] Add intrinsics for st.bulk instruction (PR #128856)   Srinivasa Ravi via llvm-commits
• [llvm] 51a15d9 - [RISCV] Simplify createRISCVELFStreamer registration   Fangrui Song via llvm-commits
• [llvm] [AMDGPU][NPM] Port SIModeRegister to NPM (PR #129014)   Matt Arsenault via llvm-commits
• [llvm] 50b508c - [AMDGPU] Verify SdwaSel value range (#128898)   via llvm-commits
• [llvm] [AMDGPU] Verify SdwaSel value range (PR #128898)   Frederik Harwath via llvm-commits
• [compiler-rt] 7521207 - [compiler-rt][sanitizer_common] fix copy_file_range test. (#129010)   via llvm-commits
• [compiler-rt] [compiler-rt][sanitizer_common] fix copy_file_range test. (PR #129010)   David CARLIER via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [CodeGen][NVPTX] Add a TRI function get the Dwarf register number for a virtual register. (PR #129017)   Craig Topper via llvm-commits
• [llvm] [CodeGen][NVPTX] Add a TRI function get the Dwarf register number for a virtual register. (PR #129017)   via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [CodeGen][NVPTX] Add a TRI function get the Dwarf register number for a virtual register. (PR #129017)   Matt Arsenault via llvm-commits
• [llvm] b38fdfc - [AArch64] Simplify ELFStreamer and WinCOFFStreamer   Fangrui Song via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [MCA] Adding missing instructions in AArch64 Neoverse V1 tests (PR #128892)   Julien Villette via llvm-commits
• [clang] [lldb] [llvm] Extending LLDB to work on AIX (PR #102601)   via llvm-commits
• [llvm] c11e3da - [RISCV] Correct RISCVTTIImpl::getIntImmCostInst for Zba (#128174)   via llvm-commits
• [llvm] [RISCV] Correct RISCVTTIImpl::getIntImmCostInst for Zba (PR #128174)   Gergely Futo via llvm-commits
• [llvm] [docs] fix unclosed parentheses in 'Pointer Authentication' (PR #88861)   via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Pengcheng Wang via llvm-commits
• [llvm] [LoongArch] use TypeWidenVector for most illegal vector types (PR #126456)   via llvm-commits
• [llvm] Reland "[Support] Assert that DomTree nodes share parent"" (PR #102782)   Mikael Holmén via llvm-commits
• [llvm] Reland "[Support] Assert that DomTree nodes share parent"" (PR #102782)   Mikael Holmén via llvm-commits
• [clang] [llvm] APFloat: Fix maxnum and minnum with sNaN (PR #112854)   LLVM Continuous Integration via llvm-commits
• [llvm] [AMDGPU][NPM] Port SIModeRegister to NPM (PR #129014)   Akshat Oke via llvm-commits
• [llvm] [AMDGPU][NPM] Port SIModeRegister to NPM (PR #129014)   Matt Arsenault via llvm-commits
• [llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)   Sjoerd Meijer via llvm-commits
• [llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)   Sjoerd Meijer via llvm-commits
• [llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)   Sjoerd Meijer via llvm-commits
• [llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)   Sjoerd Meijer via llvm-commits
• [llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)   via llvm-commits
• [llvm] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (PR #120557)   Akshat Oke via llvm-commits
• [llvm] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (PR #120557)   Akshat Oke via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Benjamin Maxwell via llvm-commits
• [llvm] [CodeGen][NPM] Port BranchFolder to NPM (PR #128858)   Akshat Oke via llvm-commits
• [llvm] [LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (PR #128035)   Benjamin Maxwell via llvm-commits
• [llvm] 78aa61d - [InstCombine] matchOrConcat - return Value* not Instruction* (#128921)   via llvm-commits
• [llvm] [InstCombine] matchOrConcat - return Value* not Instruction* (PR #128921)   Simon Pilgrim via llvm-commits
• [clang] [llvm] Reapply [CaptureTracking][FunctionAttrs] Add support for CaptureInfo (#125880) (PR #128020)   Nikita Popov via llvm-commits
• [llvm] eec697b - [X86] combineINSERT_SUBVECTOR - use getBROADCAST_LOAD helper in insert_subvector(undef, broadcast(p), hi) -> broadcast(p) fold (#128900)   via llvm-commits
• [llvm] [X86] combineINSERT_SUBVECTOR - use getBROADCAST_LOAD helper in insert_subvector(undef, broadcast(p), hi) -> broadcast(p) fold (PR #128900)   Simon Pilgrim via llvm-commits
• [llvm] [MCA] New option to report scheduling information: -scheduling-info (PR #126703)   Julien Villette via llvm-commits
• [compiler-rt] [tsan][RISCV] Add Go support for linux/riscv64 (PR #127295)   Pengcheng Wang via llvm-commits
• [llvm] b021bdb - [AArch64] Add codesize test coverage. NFC   David Green via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Simon Pilgrim via llvm-commits
• [compiler-rt] [tsan][RISCV] Add Go support for linux/riscv64 (PR #127295)   Pengcheng Wang via llvm-commits
• [compiler-rt] [tsan][RISCV] Add Go support for linux/riscv64 (PR #127295)   Pengcheng Wang via llvm-commits
• [compiler-rt] [tsan][RISCV] Add Go support for linux/riscv64 (PR #127295)   Pengcheng Wang via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Simon Pilgrim via llvm-commits
• [clang] [llvm] [WIP] Correct lowering of `fp128` intrinsics (PR #76558)   Trevor Gross via llvm-commits
• [compiler-rt] [tsan][RISCV] Add Go support for linux/riscv64 (PR #127295)   Meng Zhuo via llvm-commits
• [llvm] [JumpThreading] Remove deleted BB from Unreachable (PR #126984)   Nikita Popov via llvm-commits
• [llvm] fcc8802 - [Docs] Fix typo in GetElementPtr.rst (#127393)   via llvm-commits
• [llvm] Update GetElementPtr.rst (PR #127393)   Nikita Popov via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Phoebe Wang via llvm-commits
• [llvm] f5ee401 - [LLVM][NVPTX] Add codegen support for tcgen05.{ld, st} instructions (#126740)   via llvm-commits
• [llvm] [LLVM][NVPTX] Add codegen support for tcgen05.{ld, st} instructions (PR #126740)   Pradeep Kumar via llvm-commits
• [llvm] [X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (PR #128877)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (PR #128877)   Simon Pilgrim via llvm-commits
• [llvm] remove extraneous comma in OpLifetimeStart and OpLifetimeStop (PR #129025)   via llvm-commits
• [llvm] remove extraneous comma in OpLifetimeStart and OpLifetimeStop (PR #129025)   via llvm-commits
• [llvm] 4d387c4 - [X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (#128877)   via llvm-commits
• [llvm] [X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (PR #128877)   Simon Pilgrim via llvm-commits
• [llvm] remove extraneous comma in OpLifetimeStart and OpLifetimeStop (PR #129025)   via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   David Sherwood via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [llvm] [X86][AsmParser] Improve rel8 validation (PR #126073)   Simon Pilgrim via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize] Further improve cost model for early exit loops (PR #126235)   David Sherwood via llvm-commits
• [llvm] 25ebdfc - [IR] Avoid repeated hash lookups (NFC) (#128998)   via llvm-commits
• [llvm] [IR] Avoid repeated hash lookups (NFC) (PR #128998)   Kazu Hirata via llvm-commits
• [llvm] 4913e7b - [SelectionDAG] Avoid repeated hash lookups (NFC) (#128999)   via llvm-commits
• [llvm] [SelectionDAG] Avoid repeated hash lookups (NFC) (PR #128999)   Kazu Hirata via llvm-commits
• [llvm] 3ce3872 - [Support] Avoid repeated hash lookups (NFC) (#129000)   via llvm-commits
• [llvm] [Support] Avoid repeated hash lookups (NFC) (PR #129000)   Kazu Hirata via llvm-commits
• [llvm] 0e3ba99 - [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (#128857)   via llvm-commits
• [llvm] [X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (PR #128857)   Simon Pilgrim via llvm-commits
• [llvm] [VectorCombine] support mismatching extract/insert indices for foldInsExtFNeg (PR #126408)   Simon Pilgrim via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Matt Arsenault via llvm-commits
• [llvm] [VectorCombine] support mismatching extract/insert indices for foldInsExtFNeg (PR #126408)   Simon Pilgrim via llvm-commits
• [llvm] [VectorCombine] support mismatching extract/insert indices for foldInsExtFNeg (PR #126408)   Simon Pilgrim via llvm-commits
• [llvm] [VectorCombine] support mismatching extract/insert indices for foldInsExtFNeg (PR #126408)   Simon Pilgrim via llvm-commits
• [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)   David Sherwood via llvm-commits
• [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)   David Sherwood via llvm-commits
• [llvm] [LV] Compute register usage for interleaving on VPlan. (PR #126437)   Sam Tebbs via llvm-commits
• [clang] [llvm] Clang: emit llvm.minnum and llvm.maxnum with nsz always (PR #113133)   YunQiang Su via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [clang] [llvm] Clang: emit llvm.minnum and llvm.maxnum with nsz always (PR #113133)   YunQiang Su via llvm-commits
• [clang] [llvm] Clang: emit llvm.minnum and llvm.maxnum with nsz always (PR #113133)   YunQiang Su via llvm-commits
• [llvm] [VectorCombine] Handle shuffle of selects (PR #128032)   Simon Pilgrim via llvm-commits
• [clang] [llvm] Clang: emit llvm.minnum and llvm.maxnum with nsz always (PR #113133)   YunQiang Su via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] [VectorCombine] Handle shuffle of selects (PR #128032)   Simon Pilgrim via llvm-commits
• [llvm] [AMDGPU] Make S_WAIT_EVENT a scheduling boundary (PR #129032)   Jay Foad via llvm-commits
• [llvm] [VectorCombine] Handle shuffle of selects (PR #128032)   Simon Pilgrim via llvm-commits
• [llvm] [AMDGPU] Make S_WAIT_EVENT a scheduling boundary (PR #129032)   Jay Foad via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [llvm] [AMDGPU] Make S_WAIT_EVENT a scheduling boundary (PR #129032)   Jay Foad via llvm-commits
• [llvm] [LoopVectorize][NFC] Fix formatting issue with a comment (PR #129033)   David Sherwood via llvm-commits
• [llvm] [LoopVectorize][NFC] Fix formatting issue with a comment (PR #129033)   via llvm-commits
• [llvm] [LoopVectorize][NFC] Fix formatting issue with a comment (PR #129033)   via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Lucas Ramirez via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Matt Arsenault via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Matt Arsenault via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [clang] [llvm] Clang: emit llvm.minnum and llvm.maxnum with nsz always (PR #113133)   Matt Arsenault via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Lucas Ramirez via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] 15e295d - [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (#128739)   via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Lucas Ramirez via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Luke Lau via llvm-commits
• [llvm] [InstCombine] handle trunc to i1 in foldLogOpOfMaskedICmps. (PR #128861)   Andreas Jonson via llvm-commits
• [llvm] [BPF] support indirect branch (callx) in AsmParser (PR #74988)   via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   via llvm-commits
• [llvm] 63caaa2 - [LLVM][SVE] Add isel for bfloat based (de)interleave operations. (#128875)   via llvm-commits
• [llvm] [LLVM][SVE] Add isel for bfloat based (de)interleave operations. (PR #128875)   Paul Walker via llvm-commits
• [llvm] 8150ab9 - [LoopVectorize] Use CodeSize as the cost kind for minsize (#124119)   via llvm-commits
• [llvm] [LoopVectorize] Use CodeSize as the cost kind for minsize (PR #124119)   John Brawn via llvm-commits
• [llvm] [SandboxIR][Region] Implement an auxiliary vector in Region (PR #126376)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Simon Pilgrim via llvm-commits
• [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)   Pierre van Houtryve via llvm-commits
• [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)   Pierre van Houtryve via llvm-commits
• [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)   via llvm-commits
• [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)   Ramkumar Ramachandra via llvm-commits
• [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)   Matt Arsenault via llvm-commits
• [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)   Ramkumar Ramachandra via llvm-commits
• [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)   Matt Arsenault via llvm-commits
• [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)   Ramkumar Ramachandra via llvm-commits
• [llvm] WIP:[LV] Support strided memory accesses with a stride of -1 (PR #128718)   Mel Chen via llvm-commits
• [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)   Pierre van Houtryve via llvm-commits
• [llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)   Benjamin Maxwell via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Vyacheslav Levytskyy via llvm-commits
• [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)   Jay Foad via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Vyacheslav Levytskyy via llvm-commits
• [llvm] WIP:[LV] Support strided memory accesses with a stride of -1 (PR #128718)   Mel Chen via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Vyacheslav Levytskyy via llvm-commits
• [llvm] [SLP]Reduce number of alternate instruction, where possible (PR #128907)   Alexey Bataev via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Alexey Bataev via llvm-commits
• [clang] [llvm] Clang: emit llvm.minnum and llvm.maxnum with nsz always (PR #113133)   Matt Arsenault via llvm-commits
• [llvm] [LV][EVL] Generate negative strided load/store for reversed load/store (PR #123608)   Mel Chen via llvm-commits
• [llvm] [LoopVectorize] Use CodeSize as the cost kind for minsize (PR #124119)   LLVM Continuous Integration via llvm-commits
• [llvm] [LoopVectorize] Use CodeSize as the cost kind for minsize (PR #124119)   LLVM Continuous Integration via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] fd534e5 - [AArch64] Do not split bfloat HFA args between regs and stack (#128909)   via llvm-commits
• [llvm] [AArch64] Do not split bfloat HFA args between regs and stack (PR #128909)   Oliver Stannard via llvm-commits
• [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)   David Sherwood via llvm-commits
• [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)   David Sherwood via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   Florian Hahn via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)   Pierre van Houtryve via llvm-commits
• [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)   Jay Foad via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   David CARLIER via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   David CARLIER via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #115331)   via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   David CARLIER via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   via llvm-commits
• [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)   Florian Hahn via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #126331)   Jay Foad via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   David CARLIER via llvm-commits
• [llvm] [LoopVectorize] Use CodeSize as the cost kind for minsize (PR #124119)   LLVM Continuous Integration via llvm-commits
• [llvm] [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (PR #129042)   Simon Pilgrim via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   David CARLIER via llvm-commits
• [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)   Florian Hahn via llvm-commits
• [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)   Florian Hahn via llvm-commits
• [llvm] [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (PR #129042)   via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   David CARLIER via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #126331)   Jay Foad via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   Florian Hahn via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Nathan Gauër via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   David CARLIER via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Nathan Gauër via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   David CARLIER via llvm-commits
• [llvm] [AMDGPU][Scheduler] Refactor ArchVGPR rematerialization during scheduling (PR #125885)   Lucas Ramirez via llvm-commits
• [llvm] 649f4dc - [LV] Fix tests after 8150ab93f741.   Florian Hahn via llvm-commits
• [llvm] [LoopVectorize] Use CodeSize as the cost kind for minsize (PR #124119)   Florian Hahn via llvm-commits
• [llvm] [SLP]Reduce number of alternate instruction, where possible (PR #128907)   Alexey Bataev via llvm-commits
• [llvm] [LoopVectorize] Use CodeSize as the cost kind for minsize (PR #124119)   John Brawn via llvm-commits
• [llvm] [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (PR #129042)   Simon Pilgrim via llvm-commits
• [llvm] 65c45bf - [LoopVectorize][NFC] Fix formatting issue with a comment (#129033)   via llvm-commits
• [llvm] [LoopVectorize][NFC] Fix formatting issue with a comment (PR #129033)   David Sherwood via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Florian Hahn via llvm-commits
• [llvm] 816e7cd - AMDGPU: Factor agpr reg_sequence folding into a function (#129002)   via llvm-commits
• [llvm] AMDGPU: Factor agpr reg_sequence folding into a function (PR #129002)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)   Jay Foad via llvm-commits
• [llvm] [LV][NFC] Regen some partial reduction tests (PR #129047)   David Sherwood via llvm-commits
• [llvm] [BOLT][AArch64] Introduce SPE mode in BasicAggregation (PR #120741)   Paschalis Mpeis via llvm-commits
• [llvm] [LV][NFC] Regen some partial reduction tests (PR #129047)   via llvm-commits
• [llvm] [BOLT][AArch64] Introduce SPE mode in BasicAggregation (PR #120741)   Paschalis Mpeis via llvm-commits
• [llvm] [LV][NFC] Regen some partial reduction tests (PR #129047)   Mel Chen via llvm-commits
• [llvm] [MCA] Adding missing instructions in AArch64 Neoverse V1 tests (PR #128892)   Julien Villette via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Hood Chatham via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   via llvm-commits
• [llvm] 040860a - AMDGPU: Add a mir variant of a regalloc failure test   Matt Arsenault via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   via llvm-commits
• [llvm] a88f4f1 - AMDGPU: Fix a test typo reading a partially undefined vector   Matt Arsenault via llvm-commits
• [llvm] [MCA] Adding missing instructions in AArch64 Neoverse V1 tests (PR #128892)   Julien Villette via llvm-commits
• [llvm] AMDGPU: Use helper function for use/def chain walk (PR #129052)   Matt Arsenault via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Hans Wennborg via llvm-commits
• [llvm] AMDGPU: Use helper function for use/def chain walk (PR #129052)   Matt Arsenault via llvm-commits
• [llvm] [GitHub] Add workflows to manage merging of PRs from authors without commit access (PR #124910)   David Spickett via llvm-commits
• [llvm] AMDGPU: Use helper function for use/def chain walk (PR #129052)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Use helper function for use/def chain walk (PR #129052)   via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Hans Wennborg via llvm-commits
• [llvm] [GitHub] Add workflows to manage merging of PRs from authors without commit access (PR #124910)   David Spickett via llvm-commits
• [llvm] [GitHub] Add workflows to manage merging of PRs from authors without commit access (PR #124910)   David Spickett via llvm-commits
• [llvm] [LV][EVL] Support fixed-order recurrence idiom with EVL tail folding. (PR #124093)   Mel Chen via llvm-commits
• [llvm] [LV][NFC] Regen some partial reduction tests (PR #129047)   Florian Hahn via llvm-commits
• [llvm] [LV][EVL] Support fixed-order recurrence idiom with EVL tail folding. (PR #124093)   Mel Chen via llvm-commits
• [llvm] [LV][EVL] Support fixed-order recurrence idiom with EVL tail folding. (PR #124093)   Florian Hahn via llvm-commits
• [llvm] [LoopInterchange] Prevent from undoing its own transformation (PR #127473)   Ryotaro Kasuga via llvm-commits
• [llvm] [LoopVectorize] Use CodeSize as the cost kind for minsize (PR #124119)   LLVM Continuous Integration via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Hood Chatham via llvm-commits
• [llvm] workflows: Run `apt update` before `apt install` (PR #67136)   David Spickett via llvm-commits
• [llvm] workflows: Run `apt update` before `apt install` (PR #67136)   David Spickett via llvm-commits
• [llvm] AMDGPU: Fold bitcasts into readfirstlane, readlane, and permlane64 (PR #128494)   Matt Arsenault via llvm-commits
• [llvm] 447abfc - AMDGPU: Fold bitcasts into readfirstlane, readlane, and permlane64 (#128494)   via llvm-commits
• [llvm] AMDGPU: Fold bitcasts into readfirstlane, readlane, and permlane64 (PR #128494)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU GlobalISel Add64 support (PR #124763)   Alan Li via llvm-commits
• [llvm] [InstCombine] Add support for GEPs in `simplifyNonNullOperand` (PR #128365)   Alexander Kornienko via llvm-commits
• [llvm] [NVPTX] Add intrinsics for st.bulk instruction (PR #128856)   Srinivasa Ravi via llvm-commits
• [llvm] [X86] Generalise lowerShuffleAsSpecificZeroOrAnyExtend to handle sign extension (PR #129063)   Simon Pilgrim via llvm-commits
• [llvm] [X86] Generalise lowerShuffleAsSpecificZeroOrAnyExtend to handle sign extension (PR #129063)   via llvm-commits
• [llvm] [X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (PR #128910)   Daniel Zabawa via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [llvm] AMDGPU GlobalISel Add64 support (PR #124763)   Alan Li via llvm-commits
• [llvm] [VPlan] Expand VPWidenIntOrFpInductionRecipe into separate recipes (PR #118638)   Alexey Bataev via llvm-commits
• [lld] [llvm] [readobj][Arm][AArch64] Refactor Build Attributes parsing under ELFAtributeParser and add support for AArch64 Build Attributes (PR #128727)   via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #115331)   via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [LV] Teach the vectorizer to cost and vectorize modf and sincospi intrinsics (PR #129064)   Benjamin Maxwell via llvm-commits
• [llvm] [LV] Teach the vectorizer to cost and vectorize modf and sincospi intrinsics (PR #129064)   via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #115331)   via llvm-commits
• [llvm] [LV][NFC] Regen some partial reduction tests (PR #129047)   David Sherwood via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   Miro Bucko via llvm-commits
• [llvm] [InstCombine] Add support for GEPs in `simplifyNonNullOperand` (PR #128365)   Alexander Kornienko via llvm-commits
• [llvm] [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (PR #128190)   Vyacheslav Levytskyy via llvm-commits
• [llvm] c19a303 - [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (#128190)   via llvm-commits
• [llvm] [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (PR #129042)   Simon Pilgrim via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   Sushant Gokhale via llvm-commits
• [llvm] [NFC][CodingStandard] Fix text style for C++ keywords (PR #128932)   Rahul Joshi via llvm-commits
• [llvm] [llvm-dwarfdump] Make --verify for .debug_names multithreaded. (PR #127281)   Alexander Yermolovich via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #115331)   via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Sebastian Pop via llvm-commits
• [llvm] Introducing a new ISD::POISON SDNode to represent the poison value in the IR. (PR #125883)   zhijian lin via llvm-commits
• [llvm] [LV] Teach the vectorizer to cost and vectorize modf and sincospi intrinsics (PR #129064)   Sam Tebbs via llvm-commits
• [llvm] [MemProf] Fix handling of recursive edges during func assignment (PR #129066)   Teresa Johnson via llvm-commits
• [llvm] [MemProf] Fix handling of recursive edges during func assignment (PR #129066)   via llvm-commits
• [llvm] [LoopVectorize] Use CodeSize as the cost kind for minsize (PR #124119)   LLVM Continuous Integration via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Craig Topper via llvm-commits
• [llvm] [LoopVectorize] Use CodeSize as the cost kind for minsize (PR #124119)   LLVM Continuous Integration via llvm-commits
• [llvm] [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (PR #129042)   Phoebe Wang via llvm-commits
• [llvm] [NVPTX] Add intrinsics for st.bulk instruction (PR #128856)   Srinivasa Ravi via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #115331)   via llvm-commits
• [llvm] [FunctionAttrs] Add `errno` inference logic (PR #129067)   Antonio Frighetto via llvm-commits
• [llvm] [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (PR #129042)   Phoebe Wang via llvm-commits
• [llvm] [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (PR #129042)   Phoebe Wang via llvm-commits
• [llvm] [FunctionAttrs] Add `errno` inference logic (PR #129067)   via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #115331)   Teresa Johnson via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #115331)   Teresa Johnson via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #115331)   Teresa Johnson via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #115331)   Teresa Johnson via llvm-commits
• [lldb] [llvm] Modify the localCache API to require an explicit commit on CachedFile… (PR #115331)   Teresa Johnson via llvm-commits
• [llvm] [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (PR #129042)   Phoebe Wang via llvm-commits
• [llvm] [X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (PR #128910)   Daniel Zabawa via llvm-commits
• [llvm] [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (PR #129042)   Simon Pilgrim via llvm-commits
• [llvm] 61aab82 - [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (#129042)   via llvm-commits
• [llvm] [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (PR #129042)   Simon Pilgrim via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Florian Hahn via llvm-commits
• [llvm] 3afc3f4 - [MergeFunc] Remove discardables function before writing alias or thunk. (#128865)   via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   Florian Hahn via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Antonio Frighetto via llvm-commits
• [llvm] [DirectX] initialize registers properties by calling addRegisterClass and computeRegisterProperties (PR #128818)   Farzon Lotfi via llvm-commits
• [llvm] dc764f5 - [DirectX] initialize registers properties by calling addRegisterClass and computeRegisterProperties (#128818)   via llvm-commits
• [llvm] [DirectX] initialize registers properties by calling addRegisterClass and computeRegisterProperties (PR #128818)   Farzon Lotfi via llvm-commits
• [llvm] c630de9 - [gn build] Port dc764f5c689f   LLVM GN Syncbot via llvm-commits
• [llvm] AMDGPU: Use helper function for use/def chain walk (PR #129052)   Matt Arsenault via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [DebugInfo] Handle additional types of stores in assignment tracking (PR #129070)   Stephen Tozer via llvm-commits
• [llvm] [MergeFunc] Remove discardables function before writing alias or thunk. (PR #128865)   LLVM Continuous Integration via llvm-commits
• [llvm] [DebugInfo] Handle additional types of stores in assignment tracking (PR #129070)   via llvm-commits
• [llvm] AMDGPU: Use helper function for use/def chain walk (PR #129052)   Janek van Oirschot via llvm-commits
• [llvm] [DebugInfo] Handle additional types of stores in assignment tracking (PR #129070)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Jonathan Thackray via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] 8635b8e - [AMDGPU][True16][MC] true16 for v_alignbit_b32 (#119409)   via llvm-commits
• [llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)   Brox Chen via llvm-commits
• [llvm] [X86] getFauxShuffleMask - insert_subvector - skip undemanded subvectors (PR #129042)   Simon Pilgrim via llvm-commits
• [llvm] [DebugInfo] Handle additional types of stores in assignment tracking (PR #129070)   Stephen Tozer via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   Madhur Amilkanthwar via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   Nikita Popov via llvm-commits
• [llvm] [SPIR-V] Support 2 more instructions from SPV_INTEL_long_composites (PR #128190)   LLVM Continuous Integration via llvm-commits
• [llvm] 7defbf9 - [StackProtector] Add test for atomicrmw xchg (NFC)   Nikita Popov via llvm-commits
• [llvm] b2aba39 - [StackProtector] Handle atomicrmw xchg in HasAddressTaken heuristic   Nikita Popov via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   Florian Hahn via llvm-commits
• [llvm] Introducing a new ISD::POISON SDNode to represent the poison value in the IR. (PR #125883)   zhijian lin via llvm-commits
• [llvm] 4af2e36 - [CodeGen][NVPTX] Add a TRI function get the Dwarf register number for a virtual register. (#129017)   via llvm-commits
• [llvm] [CodeGen][NVPTX] Add a TRI function get the Dwarf register number for a virtual register. (PR #129017)   Craig Topper via llvm-commits
• [llvm] [AMDGPU] Added hot-block-rematerialize pass (PR #126331)   David Stuttard via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   Madhur Amilkanthwar via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   Madhur Amilkanthwar via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   Nikita Popov via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   Madhur Amilkanthwar via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   Madhur Amilkanthwar via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   Madhur Amilkanthwar via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   Nikita Popov via llvm-commits
• [llvm] [GVN/PRE] Run tests for AArch64 triple too (PR #129073)   Madhur Amilkanthwar via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [GVN/PRE] Remove triple from GVN/PRE tests (PR #129073)   Madhur Amilkanthwar via llvm-commits
• [llvm] Introducing a new ISD::POISON SDNode to represent the poison value in the IR. (PR #125883)   zhijian lin via llvm-commits
• [llvm] Reapply "[AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (#126621)" (PR #129078)   Krzysztof Drewniak via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Nathan Gauër via llvm-commits
• [llvm] [GVN/PRE] Remove triple from GVN/PRE tests (PR #129073)   Madhur Amilkanthwar via llvm-commits
• [llvm] Reapply "[AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (#126621)" (PR #129078)   via llvm-commits
• [llvm] [LoopUtils] Don't wrap in getLoopEstimatedTripCount (PR #129080)   Ramkumar Ramachandra via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Sumanth Gundapaneni via llvm-commits
• [llvm] [LoopUtils] Don't wrap in getLoopEstimatedTripCount (PR #129080)   via llvm-commits
• [llvm] [LoopUtils] Don't wrap in getLoopEstimatedTripCount (PR #129080)   via llvm-commits
• [llvm] [AMDGPU] Cosmetic tweaks in AMDGPUAtomicOptimizer. NFC. (PR #129081)   Jay Foad via llvm-commits
• [llvm] [DebugInfo] Handle additional types of stores in assignment tracking (PR #129070)   Jeremy Morse via llvm-commits
• [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)   Ramkumar Ramachandra via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Sumanth Gundapaneni via llvm-commits
• [clang] [llvm] Add support for template as type parameter (PR #127654)   via llvm-commits
• [llvm] [AMDGPU] Cosmetic tweaks in AMDGPUAtomicOptimizer. NFC. (PR #129081)   via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Sumanth Gundapaneni via llvm-commits
• [llvm] [MemProf] Fix handling of recursive edges during func assignment (PR #129066)   Snehasish Kumar via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Sumanth Gundapaneni via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Nathan Gauër via llvm-commits
• [llvm] [JITLink][XCOFF] Setup initial build support for XCOFF (PR #127266)   Henry Jiang via llvm-commits
• [llvm] e8379ea - [SLP]Add a test with incorrect bitwidth after minbitwidth analysis, NFC   Alexey Bataev via llvm-commits
• [llvm] [AMDGPU] Cosmetic tweaks in AMDGPUAtomicOptimizer. NFC. (PR #129081)   Shilei Tian via llvm-commits
• [llvm] [DebugInfo] Handle additional types of stores in assignment tracking (PR #129070)   Stephen Tozer via llvm-commits
• [llvm] [LoopUtils] Don't wrap in getLoopEstimatedTripCount (PR #129080)   Ramkumar Ramachandra via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Nathan Gauër via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [llvm] [AMDGPU] Add custom MachineValueType entries for buffer fat poiners (PR #127692)   Krzysztof Drewniak via llvm-commits
• [llvm] 6a5bb4c - [MemProf] Fix handling of recursive edges during func assignment (#129066)   via llvm-commits
• [llvm] [MemProf] Fix handling of recursive edges during func assignment (PR #129066)   Teresa Johnson via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Nathan Gauër via llvm-commits
• [llvm] 69effe0 - [SLP]Check for potential safety of the truncation for vectorized scalars with multi uses   Alexey Bataev via llvm-commits
• [llvm] [SandboxIR][Region][NFC] Fix windows build issue (PR #129082)   via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Nathan Gauër via llvm-commits
• [llvm] [X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (PR #128910)   Daniel Zabawa via llvm-commits
• [llvm] [X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (PR #128910)   Daniel Zabawa via llvm-commits
• [llvm] [X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (PR #128910)   via llvm-commits
• [llvm] [DebugInfo] Handle additional types of stores in assignment tracking (PR #129070)   Orlando Cazalet-Hyams via llvm-commits
• [llvm] [DebugInfo] Handle additional types of stores in assignment tracking (PR #129070)   Orlando Cazalet-Hyams via llvm-commits
• [llvm] [DebugInfo] Handle additional types of stores in assignment tracking (PR #129070)   Orlando Cazalet-Hyams via llvm-commits
• [llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)   Alexey Bataev via llvm-commits
• [llvm] [SPIR-V] Add pass to remove spv_ptrcast intrinsics (PR #128896)   Steven Perron via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [SandboxIR][Region] Implement an auxiliary vector in Region (PR #126376)   via llvm-commits
• [llvm] WIP:[LV] Support strided memory accesses with a stride of -1 (PR #128718)   Alexey Bataev via llvm-commits
• [llvm] WIP:[LV] Support strided memory accesses with a stride of -1 (PR #128718)   Alexey Bataev via llvm-commits
• [llvm] WIP:[LV] Support strided memory accesses with a stride of -1 (PR #128718)   Alexey Bataev via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Alexey Bataev via llvm-commits
• [llvm] Reapply "[AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (#126621)" (PR #129078)   Kazu Hirata via llvm-commits
• [llvm] [DebugInfo] Handle additional types of stores in assignment tracking (PR #129070)   Stephen Tozer via llvm-commits
• [llvm] [AMDGPU] Cosmetic tweaks in AMDGPUAtomicOptimizer. NFC. (PR #129081)   Matt Arsenault via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   via llvm-commits
• [llvm] bc91acc - [AMDGPU][MC] Disassembler warning for v_cmpx instructions (#127925)   via llvm-commits
• [llvm] [AMDGPU][MC] Disassembler warning for v_cmpx instructions (PR #127925)   Jun Wang via llvm-commits
• [llvm] [AMDGPU][MC] Disassembler warning for v_cmpx instructions (PR #128256)   Jun Wang via llvm-commits
• [llvm] [AMDGPU][MC] Disassembler warning for v_cmpx instructions (PR #128256)   Jun Wang via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fshr true16 pattern (PR #129085)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fshr true16 pattern (PR #129085)   Brox Chen via llvm-commits
• [llvm] AMDGPU: Use helper function for use/def chain walk (PR #129052)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Djordje Todorovic via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fshr true16 pattern (PR #129085)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] fshr true16 pattern (PR #129085)   via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Alan Li via llvm-commits
• [llvm] f8cc509 - Reapply "[AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (#126621)" (#129078)   via llvm-commits
• [llvm] Reapply "[AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (#126621)" (PR #129078)   Krzysztof Drewniak via llvm-commits
• [llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)   Ricardo Jesus via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Alan Li via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Alan Li via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Zahira Ammarguellat via llvm-commits
• [libcxx] [llvm] [libc++] Diagnose when nullptrs are passed to string APIs (PR #122790)   Mark de Wever via llvm-commits
• [llvm] [SPIR-V] Add `OpConstantCompositeContinuedINTEL` instruction (PR #129086)   Viktoria Maximova via llvm-commits
• [llvm] [BOLT] Enable hugify for AArch64 (PR #117158)   via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [SPIR-V] Add `OpConstantCompositeContinuedINTEL` instruction (PR #129086)   Viktoria Maximova via llvm-commits
• [llvm] [LAA] Consider accessed addrspace when mapping underlying obj to access. (PR #129087)   Florian Hahn via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Alexey Bataev via llvm-commits
• [llvm] [LAA] Consider accessed addrspace when mapping underlying obj to access. (PR #129087)   via llvm-commits
• [llvm] 1e1b9bc - [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (#128375)   via llvm-commits
• [llvm] [VPlan] Simplify BLEND %a, %b, NOT(%m) -> BLEND %b, %a, %m. (PR #128375)   Florian Hahn via llvm-commits
• [llvm] [PAC] Make ValueMapper handle ConstantPtrAuth values (PR #129088)   Anatoly Trosinenko via llvm-commits
• [llvm] [LAA] Consider accessed addrspace when mapping underlying obj to access. (PR #129087)   Colin Davidson via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Craig Topper via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Craig Topper via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Craig Topper via llvm-commits
• [llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)   Craig Topper via llvm-commits
• [llvm] [GISel][AMDGPU] Expand ShuffleVector (PR #124527)   Alan Li via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Min-Yih Hsu via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Min-Yih Hsu via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Sebastian Pop via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Min-Yih Hsu via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Min-Yih Hsu via llvm-commits
• [llvm] [SLP]Reduce number of alternate instruction, where possible (PR #128907)   via llvm-commits
• [llvm] ba400e8 - AMDGPU: Use helper function for use/def chain walk (#129052)   via llvm-commits
• [llvm] AMDGPU: Use helper function for use/def chain walk (PR #129052)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Add mir test for agpr constant reg_sequence handling (PR #129058)   Matt Arsenault via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Sebastian Pop via llvm-commits
• [llvm] [DirectX] Set function-level flag Int64Ops in DXIL Shader Flags Analysis (PR #129089)   Deric Cheung via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Sebastian Pop via llvm-commits
• [llvm] [DirectX] Set function-level flag Int64Ops in DXIL Shader Flags Analysis (PR #129089)   via llvm-commits
• [llvm] [DirectX] Set function-level flag Int64Ops in DXIL Shader Flags Analysis (PR #129089)   Deric Cheung via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Sebastian Pop via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Zahira Ammarguellat via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Sebastian Pop via llvm-commits
• [llvm] [SLP]Reduce number of alternate instruction, where possible (PR #128907)   via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Zahira Ammarguellat via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Zahira Ammarguellat via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Alexey Bataev via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] Introducing a new ISD::POISON SDNode to represent the poison value in the IR. (PR #125883)   zhijian lin via llvm-commits
• [llvm] [flang][runtime] Detect byte order reversal problems (PR #129093)   Peter Klausler via llvm-commits
• [llvm] [flang][runtime] Detect byte order reversal problems (PR #129093)   Peter Klausler via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] Introducing a new ISD::POISON SDNode to represent the poison value in the IR. (PR #125883)   Craig Topper via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)   Justin Bogner via llvm-commits
• [llvm] [SandboxVec][Scheduler] Enforce scheduling SchedBundle instrs back-to-back (PR #128092)   Sriraman Tallam via llvm-commits
• [llvm] [SandboxVec][Scheduler] Enforce scheduling SchedBundle instrs back-to-back (PR #128092)   Sriraman Tallam via llvm-commits
• [llvm] [SandboxVec][Scheduler] Enforce scheduling SchedBundle instrs back-to-back (PR #128092)   via llvm-commits
• [llvm] e2b0d5d - [SandboxVec][Scheduler] Enforce scheduling SchedBundle instrs back-to-back (#128092)   via llvm-commits
• [llvm] [SandboxVec][Scheduler] Enforce scheduling SchedBundle instrs back-to-back (PR #128092)   via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [compiler-rt] Augment `uncaught-exception.test` fuzzer test to be msvc-compatible (PR #125924)   David Justo via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Zahira Ammarguellat via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for madmixmods true16 pattern (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for madmixmods true16 pattern (PR #124995)   Brox Chen via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   Sam Clegg via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   Sam Clegg via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   Sam Clegg via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   Sam Clegg via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Alexey Bataev via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   Sam Clegg via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Add -sbvec-stop-at flag for debugging (PR #129097)   via llvm-commits
• [llvm] [SandboxVec][Scheduler] Enforce scheduling SchedBundle instrs back-to-back (PR #128092)   Simon Pilgrim via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Eli Friedman via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Add -sbvec-stop-at flag for debugging (PR #129097)   via llvm-commits
• [llvm] [SandboxVec][Scheduler] Enforce scheduling SchedBundle instrs back-to-back (PR #128092)   via llvm-commits
• [llvm] [SandboxVec][Scheduler] Enforce scheduling SchedBundle instrs back-to-back (PR #128092)   LLVM Continuous Integration via llvm-commits
• [llvm] [DWARFLinker] Adjust DW_AT_LLVM_stmt_sequence for rewritten line tables (PR #128953)   via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Eli Friedman via llvm-commits
• [llvm] ead7b7b - [SandboxVec] Fix unused variables warnings   Vasileios Porpodas via llvm-commits
• [llvm] [SandboxVec][Scheduler] Enforce scheduling SchedBundle instrs back-to-back (PR #128092)   via llvm-commits
• [compiler-rt] [libc] [libc][sched] Implement proxy headers for `cpu_set_t`, `struct sched_param` and `sched_macros`. (PR #126303)   Krishna Pandey via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Zahira Ammarguellat via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [docs] Fix typo in GettingStarted.rst Unlinke -> Unlike (NFC) (PR #128616)   Benjamin Maxwell via llvm-commits
• [llvm] [docs] Fix typo in GettingStarted.rst Unlinke -> Unlike (NFC) (PR #128616)   Benjamin Maxwell via llvm-commits
• [llvm] 78c96aa - [docs] Fix typo in GettingStarted.rst Unlinke -> Unlike (NFC) (#128616)   via llvm-commits
• [llvm] [docs] Fix typo in GettingStarted.rst Unlinke -> Unlike (NFC) (PR #128616)   Benjamin Maxwell via llvm-commits
• [llvm] [docs] Fix typo in GettingStarted.rst Unlinke -> Unlike (NFC) (PR #128616)   via llvm-commits
• [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)   Sumanth Gundapaneni via llvm-commits
• [clang] [llvm] [AMDGPU] Use 32-bit index for SWMMAC builtins (PR #129101)   Shilei Tian via llvm-commits
• [llvm] [VectorCombine] support mismatching extract/insert indices for foldInsExtFNeg (PR #126408)   via llvm-commits
• [clang] [llvm] [AMDGPU] Use 32-bit index for SWMMAC builtins (PR #129101)   Shilei Tian via llvm-commits
• [clang] [llvm] [AMDGPU] Use 32-bit index for SWMMAC builtins (PR #129101)   via llvm-commits
• [llvm] 253d691 - [VPlan] Update VPBranchOnMaskRecipe to always set the mask (NFC).   Florian Hahn via llvm-commits
• [clang] [llvm] [Clang][AMDGPU] Use 32-bit index for SWMMAC builtins (PR #129101)   Shilei Tian via llvm-commits
• [llvm] [RFC][BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [llvm] [NVPTX] Combine addressing-mode variants of ld, st, wmma (PR #129102)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] Combine addressing-mode variants of ld, st, wmma (PR #129102)   via llvm-commits
• [llvm] [NFC][CodingStandard] Fix text style for C++ keywords (PR #128932)   Rahul Joshi via llvm-commits
• [clang] [llvm] [Clang][AMDGPU] Use 32-bit index for SWMMAC builtins (PR #129101)   Shilei Tian via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Add -sbvec-stop-at flag for debugging (PR #129097)   via llvm-commits
• [llvm] [BOLT][instr] Avoid WX segment (PR #128982)   Maksim Panchenko via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Alexey Bataev via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Sam Clegg via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Sam Clegg via llvm-commits
• [llvm] [PAC] Make ValueMapper handle ConstantPtrAuth values (PR #129088)   Anatoly Trosinenko via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Sam Clegg via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Sam Clegg via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Sam Clegg via llvm-commits
• [llvm] [PAC] Make ValueMapper handle ConstantPtrAuth values (PR #129088)   Anatoly Trosinenko via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [PAC] Make ValueMapper handle ConstantPtrAuth values (PR #129088)   Anatoly Trosinenko via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Sam Clegg via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Sam Clegg via llvm-commits
• [llvm] [PAC] Make ValueMapper handle ConstantPtrAuth values (PR #129088)   via llvm-commits
• [llvm] [PAC] Make ValueMapper handle ConstantPtrAuth values (PR #129088)   Anton Korobeynikov via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [PAC] Make ValueMapper handle ConstantPtrAuth values (PR #129088)   Anton Korobeynikov via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][NFC] Move isXDL and isDGEMM to SIInstrInfo. (PR #129103)   via llvm-commits
• [llvm] [AMDGPU][NFC] Move isXDL and isDGEMM to SIInstrInfo. (PR #129103)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [AMDGPU][NFC] Move isXDL and isDGEMM to SIInstrInfo. (PR #129103)   via llvm-commits
• [llvm] [RISCV] Order the implicit defs on MC vset(i)vl(i) instructions the s… (PR #129104)   Craig Topper via llvm-commits
• [llvm] [RISCV] Order the implicit defs on MC vset(i)vl(i) instructions the same as the pseudo version. (PR #129104)   Craig Topper via llvm-commits
• [llvm] [RISCV] Order the implicit defs on MC vset(i)vl(i) instructions the same as the pseudo version. (PR #129104)   Craig Topper via llvm-commits
• [compiler-rt] [asan] Define mallopt and mallinfo for Fuchsia asan runtime (PR #129105)   via llvm-commits
• [llvm] [RISCV] Order the implicit defs on MC vset(i)vl(i) instructions the same as the pseudo version. (PR #129104)   via llvm-commits
• [llvm] [RISCV] Order the implicit defs on MC vset(i)vl(i) instructions the same as the pseudo version. (PR #129104)   Craig Topper via llvm-commits
• [compiler-rt] [asan] Define mallopt and mallinfo for Fuchsia asan runtime (PR #129105)   via llvm-commits
• [llvm] [RISCV] Order the implicit defs on MC vset(i)vl(i) instructions the same as the pseudo version. (PR #129104)   Craig Topper via llvm-commits
• [compiler-rt] Augment `uncaught-exception.test` fuzzer test to be msvc-compatible (PR #125924)   David Justo via llvm-commits
• [llvm] [AMDGPU] Add custom MachineValueType entries for buffer fat poiners (PR #127692)   Craig Topper via llvm-commits
• [llvm] [AMDGPU] Add custom MachineValueType entries for buffer fat poiners (PR #127692)   Craig Topper via llvm-commits
• [llvm] [RISCV] Order the implicit defs on MC vset(i)vl(i) instructions the same as the pseudo version. (PR #129104)   Craig Topper via llvm-commits
• [llvm] [RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (PR #129104)   Craig Topper via llvm-commits
• [llvm] [RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (PR #129104)   Craig Topper via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Brox Chen via llvm-commits
• [llvm] [PowerPC] custom lower v1024i1 load/store (PR #126969)   Lei Huang via llvm-commits
• [llvm] True16 Add OpSel when optimizing exec mask (PR #128928)   Brox Chen via llvm-commits
• [llvm] True16 Add OpSel when optimizing exec mask (PR #128928)   Brox Chen via llvm-commits
• [llvm] [AIX] Add -pthread to build on AIX (PR #129108)   Mark Danial via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Eli Friedman via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Zahira Ammarguellat via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   via llvm-commits
• [llvm] [PAC] Make ValueMapper handle ConstantPtrAuth values (PR #129088)   Tom Stellard via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   via llvm-commits
• [llvm] [NVPTX] Combine addressing-mode variants of ld, st, wmma (PR #129102)   Alex MacLean via llvm-commits
• [llvm] [VectorCombine] support mismatching extract/insert indices for foldInsExtFNeg (PR #126408)   via llvm-commits
• [llvm] [DirectX] Set module-level flag `LowPrecisionPresent` in DXIL Shader Flags Analysis (PR #129109)   Deric Cheung via llvm-commits
• [llvm] [DirectX] Set module-level flag `LowPrecisionPresent` in DXIL Shader Flags Analysis (PR #129109)   via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [compiler-rt] [compiler-rt][sanitizer_common] copy_file_range syscall interception. (PR #125816)   Daniel Thornburgh via llvm-commits
• [llvm] [DirectX] Set module-level flag `LowPrecisionPresent` in DXIL Shader Flags Analysis (PR #129109)   Deric Cheung via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [compiler-rt] e5d9310 - Revert "[compiler-rt][sanitizer_common] copy_file_range syscall interception. (#125816)" and fix   Daniel Thornburgh via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   Ellis Hoag via llvm-commits
• [clang] [llvm] [memprof] Add memprof options as a clang frontend flag (PR #128615)   Ellis Hoag via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   David Green via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   David Green via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   David Green via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   David Green via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   David Green via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   David Green via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   David Green via llvm-commits
• [llvm] 6ce41db - [VPlan] Preserve DebugLoc for VPBranchOnMaskRecipe.   Florian Hahn via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Nikita Popov via llvm-commits
• [compiler-rt] [compiler-rt][sanitizer_common] copy_file_range syscall interception. (PR #125816)   David CARLIER via llvm-commits
• [llvm] [MCA] Adding missing instructions in AArch64 Neoverse V1 tests (PR #128892)   David Green via llvm-commits
• [llvm] [MCA] Adding missing instructions in AArch64 Neoverse V1 tests (PR #128892)   David Green via llvm-commits
• [llvm] [MCA] Adding missing instructions in AArch64 Neoverse V1 tests (PR #128892)   David Green via llvm-commits
• [llvm] [MCA] Adding missing instructions in AArch64 Neoverse V1 tests (PR #128892)   David Green via llvm-commits
• [compiler-rt] Reland copy file range san (PR #129114)   David CARLIER via llvm-commits
• [compiler-rt] Reland copy file range san (PR #129114)   via llvm-commits
• [compiler-rt] Reland copy file range san (PR #129114)   David CARLIER via llvm-commits
• [compiler-rt] Reland copy file range san (PR #129114)   via llvm-commits
• [compiler-rt] Reland copy file range san (PR #129114)   David CARLIER via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Add -sbvec-stop-at flag for debugging (PR #129097)   Sriraman Tallam via llvm-commits
• [llvm] [RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (PR #129104)   Philip Reames via llvm-commits
• [compiler-rt] [asan][win] Fix CreateThread leak (PR #126738)   Reid Kleckner via llvm-commits
• [lld] 94f34c0 - [LLD][COFF] Use primary symbol table machine in Writer::writeHeader (NFC) (#128442)   via llvm-commits
• [lld] [LLD][COFF] Use primary symbol table machine in Writer::writeHeader (NFC) (PR #128442)   Jacek Caban via llvm-commits
• [lld] 14bab65 - [LLD][COFF] Support CF guards on ARM64X (#128440)   via llvm-commits
• [lld] [LLD][COFF] Support CF guards on ARM64X (PR #128440)   Jacek Caban via llvm-commits
• [compiler-rt] [compiler-rt][sanitizer_common] copy_file_range syscall interception. (PR #125816)   Daniel Thornburgh via llvm-commits
• [compiler-rt] Reland copy file range san (PR #129114)   Daniel Thornburgh via llvm-commits
• [compiler-rt] 9a54c77 - Reland copy file range san (#129114)   via llvm-commits
• [compiler-rt] Reland copy file range san (PR #129114)   Daniel Thornburgh via llvm-commits
• [llvm] [DirectX] initialize registers properties by calling addRegisterClass and computeRegisterProperties (PR #128818)   LLVM Continuous Integration via llvm-commits
• [llvm] [libc][bazel] Rephrase list comp for downstream (PR #129119)   Michael Jones via llvm-commits
• [llvm] [libc][bazel] Rephrase list comp for downstream (PR #129119)   via llvm-commits
• [llvm] [libc][bazel] Rephrase list comp for downstream (PR #129119)   via llvm-commits
• [llvm] [libc][bazel] Rephrase list comp for downstream (PR #129119)   Michael Jones via llvm-commits
• [llvm] 73ed27c - [RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (#129104)   via llvm-commits
• [llvm] IR, CodeGen: Add command line flags for dumping instruction addresses and debug locations. (PR #127944)   Peter Collingbourne via llvm-commits
• [llvm] [RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (PR #129104)   Craig Topper via llvm-commits
• [llvm] [AMDGPU] Add custom MachineValueType entries for buffer fat poiners (PR #127692)   Krzysztof Drewniak via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   Amir Ayupov via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   Amir Ayupov via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   Amir Ayupov via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   Amir Ayupov via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   Amir Ayupov via llvm-commits
• [llvm] insertwaitcnt pass update for true16 (PR #128927)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)   Brox Chen via llvm-commits
• [llvm] True16 Add OpSel when optimizing exec mask (PR #128928)   Brox Chen via llvm-commits
• [llvm] True16 Add OpSel when optimizing exec mask (PR #128928)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] True16 Add OpSel when optimizing exec mask (PR #128928)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][NFC] Move isXDL and isDGEMM to SIInstrInfo. (PR #129103)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] True16 Add OpSel when optimizing exec mask (PR #128928)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)   Brox Chen via llvm-commits
• [llvm] [VectorCombine] Handle shuffle of selects (PR #128032)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)   via llvm-commits
• [clang] [llvm] [Clang][AMDGPU] Use 32-bit index for SWMMAC builtins (PR #129101)   Stanislav Mekhanoshin via llvm-commits
• [llvm] adf0abf - [SandboxVec][BottomUpVec] Add -sbvec-stop-at flag for debugging (#129097)   via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Add -sbvec-stop-at flag for debugging (PR #129097)   via llvm-commits
• [llvm] AMDGPU: Add mir test for agpr constant reg_sequence handling (PR #129058)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [SandboxVec] Add option -sbvec-allow-file for bisection debugging (PR #129127)   via llvm-commits
• [llvm] [SandboxVec] Add option -sbvec-allow-file for bisection debugging (PR #129127)   via llvm-commits
• [llvm] ffecd72 - [llvm-objcopy] Let --change-section-lma change segments wth filesz=0,… (#127724)   via llvm-commits
• [llvm] [llvm-objcopy] Let --change-section-lma change segments wth filesz=0,… (PR #127724)   Jonathon Penix via llvm-commits
• [libcxx] [llvm] [libc++] Diagnose when nullptrs are passed to string APIs (PR #122790)   Nikolas Klauser via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Artem Belevich via llvm-commits
• [llvm] [SandboxVec] Add option -sbvec-allow-file for bisection debugging (PR #129127)   Sriraman Tallam via llvm-commits
• [llvm] [RISCV] Add VL and VTYPE to implicit uses on MC vector instructions t… (PR #129130)   Craig Topper via llvm-commits
• [llvm] [RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (PR #129130)   Craig Topper via llvm-commits
• [llvm] [RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (PR #129130)   Craig Topper via llvm-commits
• [llvm] [RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (PR #129130)   via llvm-commits
• [llvm] [BOLT] Refactor MCInst target symbol lookup. NFCI (PR #129131)   Maksim Panchenko via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Jonathan Thackray via llvm-commits
• [llvm] [BOLT] Refactor MCInst target symbol lookup. NFCI (PR #129131)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Jonathan Thackray via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Jonathan Thackray via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Jonathan Thackray via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Jonathan Thackray via llvm-commits
• [llvm] [BOLT] Refactor MCInst target symbol lookup. NFCI (PR #129131)   Davide Italiano via llvm-commits
• [llvm] [RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (PR #129130)   Philip Reames via llvm-commits
• [llvm] 32bcc9f - [SandboxVec] Add option -sbvec-allow-file for bisection debugging (#129127)   via llvm-commits
• [llvm] [SandboxVec] Add option -sbvec-allow-file for bisection debugging (PR #129127)   via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   via llvm-commits
• [llvm] 72e00d6 - [SystemZ] Handle scalar to vector bitcasts. (#128628)   via llvm-commits
• [llvm] [SystemZ] Handle scalar to vector bitcasts. (PR #128628)   Jonas Paulsson via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Add -sbvec-stop-bndl flag for debugging (PR #129132)   via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Add -sbvec-stop-bndl flag for debugging (PR #129132)   via llvm-commits
• [llvm] [SandboxIR][Region][NFC] Fix windows build issue (PR #129082)   Simon Pilgrim via llvm-commits
• [llvm] [RISCV] Remove non-portable vsetvli instructions from llvm-mca test. NFC (PR #129134)   Craig Topper via llvm-commits
• [llvm] Use Module level target-abi to assign target features for codegenerated functions. (PR #100833)   via llvm-commits
• [llvm] Use Module level target-abi to assign target features for codegenerated functions. (PR #100833)   via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Craig Topper via llvm-commits
• [llvm] 4fcab8a - [SandboxIR][Region][NFC] Fix windows build issue (#129082)   via llvm-commits
• [llvm] [SandboxIR][Region][NFC] Fix windows build issue (PR #129082)   via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Sebastian Pop via llvm-commits
• [lld] [llvm] [LTO] Override TargetABI from module flags if present when creating T… (PR #126497)   Craig Topper via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Artem Belevich via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Artem Belevich via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Artem Belevich via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Artem Belevich via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Artem Belevich via llvm-commits
• [llvm] [VectorCombine] Handle shuffle of selects (PR #128032)   via llvm-commits
• [llvm] [llvm-dwarfdump] Make --verify for .debug_names multithreaded. (PR #127281)   Alexander Yermolovich via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Craig Topper via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Sam Elliott via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Sam Elliott via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Craig Topper via llvm-commits
• [llvm] f3b1849 - [RISCV] Consolidate some DecoderNamespaces for standard extensions. (#128954)   via llvm-commits
• [llvm] [RISCV] Consolidate some DecoderNamespaces for standard extensions. (PR #128954)   Craig Topper via llvm-commits
• [llvm] [docs] Add Included Suites to Test Suite Guide (PR #128937)   Tarun Prabhu via llvm-commits
• [llvm] [docs] Add Included Suites to Test Suite Guide (PR #128937)   Tarun Prabhu via llvm-commits
• [llvm] [docs] Add Included Suites to Test Suite Guide (PR #128937)   Tarun Prabhu via llvm-commits
• [llvm] [llvm-dwarfdump] Make --verify for .debug_names multithreaded. (PR #127281)   Felipe de Azevedo Piovezan via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   Ali Raeisdanaei via llvm-commits
• [llvm] [NVPTX] Combine addressing-mode variants of ld, st, wmma (PR #129102)   Kevin McAfee via llvm-commits
• [llvm] [NVPTX] Combine addressing-mode variants of ld, st, wmma (PR #129102)   Kevin McAfee via llvm-commits
• [llvm] [NVPTX] Combine addressing-mode variants of ld, st, wmma (PR #129102)   Kevin McAfee via llvm-commits
• [llvm] [NVPTX] Combine addressing-mode variants of ld, st, wmma (PR #129102)   Kevin McAfee via llvm-commits
• [clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)   via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [llvm] [flang][runtime] Detect byte order reversal problems (PR #129093)   via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Artem Belevich via llvm-commits
• [llvm] 63ecb01 - [RISCV] Reduce dynamic relocations for RISCVOpcodesList table. NFC   Craig Topper via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [llvm] [NVPTX] Combine addressing-mode variants of ld, st, wmma (PR #129102)   Alex MacLean via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] IR, CodeGen: Add command line flags for dumping instruction addresses and debug locations. (PR #127944)   Reid Kleckner via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Artem Belevich via llvm-commits
• [clang] [llvm] [win][x64] Unwind v2 3/n: Add support for emitting unwind v2 information (equivalent to MSVC /d2epilogunwind) (PR #129142)   Daniel Paoliello via llvm-commits
• [clang] [llvm] [win][x64] Unwind v2 3/n: Add support for emitting unwind v2 information (equivalent to MSVC /d2epilogunwind) (PR #129142)   via llvm-commits
• [clang] [llvm] [win][x64] Unwind v2 3/n: Add support for emitting unwind v2 information (equivalent to MSVC /d2epilogunwind) (PR #129142)   via llvm-commits
• [clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)   Craig Topper via llvm-commits
• [llvm] 0ebf7b4 - IR, CodeGen: Add command line flags for dumping instruction addresses and debug locations.   via llvm-commits
• [llvm] [windows] Always pass libcall fp128 arguments indirectly (PR #128848)   Reid Kleckner via llvm-commits
• [llvm] IR, CodeGen: Add command line flags for dumping instruction addresses and debug locations. (PR #127944)   Peter Collingbourne via llvm-commits
• [llvm] G_Merge value and ICMP GISEL (PR #128913)   Brox Chen via llvm-commits
• [llvm] [NVPTX] Combine addressing-mode variants of ld, st, wmma (PR #129102)   Artem Belevich via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_Merge and ICMP (PR #128913)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_Merge and ICMP (PR #128913)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_Merge and ICMP (PR #128913)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_Merge and ICMP (PR #128913)   via llvm-commits
• [llvm] [llvm-dwarfdump] Make --verify for .debug_names multithreaded. (PR #127281)   Alexander Yermolovich via llvm-commits
• [llvm] [InstCombine] Add support for GEPs in `simplifyNonNullOperand` (PR #128365)   Alexander Kornienko via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   Hubert Tong via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   via llvm-commits
• [lld] [GHC] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [lld] [WASM] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [llvm] [DAGCombiner] Add some very basic folds for ADDRSPACECAST (PR #127733)   Alex MacLean via llvm-commits
• [llvm] [DAGCombiner] Add some very basic folds for ADDRSPACECAST (PR #127733)   Alex MacLean via llvm-commits
• [llvm] 85f8bd1 - [NVPTX] Combine addressing-mode variants of ld, st, wmma (#129102)   via llvm-commits
• [llvm] [NVPTX] Combine addressing-mode variants of ld, st, wmma (PR #129102)   Alex MacLean via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   Hubert Tong via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   Hubert Tong via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   Hubert Tong via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   Hubert Tong via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   Hubert Tong via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [llvm] [AMDGPU] Ensure divergence for v_alignbit (PR #129159)   Jeffrey Byrnes via llvm-commits
• [llvm] [Analysis] Add DebugInfoCache analysis (PR #118629)   Artem Pianykh via llvm-commits
• [llvm] 30d7e21 - [MCA][RISCV] Mark one of the internal CustomBehavior functions static. NFC   Min-Yih Hsu via llvm-commits
• [llvm] [AMDGPU] Ensure divergence for v_alignbit (PR #129159)   via llvm-commits
• [llvm] [BOLT][instr] Avoid WX segment (PR #128982)   YongKang Zhu via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Reid Kleckner via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Reid Kleckner via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Reid Kleckner via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Reid Kleckner via llvm-commits
• [llvm] [flang][runtime] Detect byte order reversal problems (PR #129093)   Peter Klausler via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   Artem Belevich via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   Artem Belevich via llvm-commits
• [compiler-rt] Add cmake option to enable/disable searching PATH for symbolizer (PR #129012)   Hubert Tong via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   Alex MacLean via llvm-commits
• [clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)   via llvm-commits
• [llvm] [libc][bazel] Add py_binary rule to build hdrgen. (PR #129161)   Alexey Samsonov via llvm-commits
• [lld] [WASM] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   Sam Clegg via llvm-commits
• [llvm] [libc][bazel] Add py_binary rule to build hdrgen. (PR #129161)   via llvm-commits
• [llvm] [libc][bazel] Add py_binary rule to build hdrgen. (PR #129161)   Michael Jones via llvm-commits
• [clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)   via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   Greg Clayton via llvm-commits
• [clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)   via llvm-commits
• [clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)   Craig Topper via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   Artem Belevich via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   Artem Belevich via llvm-commits
• [llvm] [Attributor] Treat `byval` arguments as objects (PR #129162)   Johannes Doerfert via llvm-commits
• [llvm] [Attributor] Treat `byval` arguments as objects (PR #129162)   Johannes Doerfert via llvm-commits
• [llvm] [Attributor][NFC] Clang format (PR #129163)   Johannes Doerfert via llvm-commits
• [llvm] [Attributor] Treat `byval` arguments as objects (PR #129162)   via llvm-commits
• [llvm] [Attributor][NFC] Clang format (PR #129163)   via llvm-commits
• [llvm] [Attributor][NFC] Improve test (PR #129165)   Johannes Doerfert via llvm-commits
• [llvm] [Attributor][NFC] Improve test (PR #129165)   via llvm-commits
• [llvm] [RISCV] Intrinsic Support for XCVsimd (PR #118557)   via llvm-commits
• [llvm] [llvm-dwarfdump] Make --verify for .debug_names multithreaded. (PR #127281)   Alexander Yermolovich via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   Alex MacLean via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   Chris Apple via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   Chris Apple via llvm-commits
• [llvm] Modify dwarf verification JSON to include detailed counts by sub-category (PR #128018)   Alexander Yermolovich via llvm-commits
• [llvm] [RISCV] Intrinsic Support for XCVelw (PR #129168)   via llvm-commits
• [llvm] [RISCV] Intrinsic Support for XCVelw (PR #129168)   via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [llvm] 9e257b0 - [RISCV] Move RISCVVInversePseudosTable from RISCVMCTargetDesc.cpp to RISCVBaseInfo.cpp. NFC   Craig Topper via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [llvm] [RISCV] Move RISCV vector load/store searchable tables from RISCVISelDAGToDAG.cpp to RISCVBaseInfo.cpp. NFC (PR #129172)   Craig Topper via llvm-commits
• [llvm] [RISCV] Move RISCV vector load/store searchable tables from RISCVISelDAGToDAG.cpp to RISCVBaseInfo.cpp. NFC (PR #129172)   via llvm-commits
• [llvm] [BPF] support indirect branch (callx) in AsmParser (PR #74988)   Yingchi Long via llvm-commits
• [llvm] IRBuilder: Add NoSignedZeros parameter to CreateMaxNum/CreateMinNum (PR #129173)   YunQiang Su via llvm-commits
• [llvm] [BPF] support indirect branch (callx) in AsmParser (PR #74988)   via llvm-commits
• [llvm] [RISCV] Move RISCV vector load/store searchable tables from RISCVISelDAGToDAG.cpp to RISCVBaseInfo.cpp. NFC (PR #129172)   via llvm-commits
• [llvm] IRBuilder: Add NoSignedZeros parameter to CreateMaxNum/CreateMinNum (PR #129173)   via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Chuanqi Xu via llvm-commits
• [llvm] IRBuilder: Add NoSignedZeros parameter to CreateMaxNum/CreateMinNum (PR #129173)   Matt Arsenault via llvm-commits
• [clang] [llvm] Clang: emit llvm.minnum and llvm.maxnum with nsz always (PR #113133)   YunQiang Su via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Luke Lau via llvm-commits
• [llvm] [DWARFLinker] Adjust DW_AT_LLVM_stmt_sequence for rewritten line tables (PR #128953)   via llvm-commits
• [clang] [llvm] [llvm:ir] Add support for constant data exceeding 4GiB (PR #126481)   via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [clang] [llvm] [llvm:ir] Add support for constant data exceeding 4GiB (PR #126481)   via llvm-commits
• [llvm] [RISCV][TTI] Fix a misuse of the getShuffleCost API [NFC] (PR #129137)   Philip Reames via llvm-commits
• [llvm] 1bd13bc - [RISCV][TTI] Fix a misuse of the getShuffleCost API [NFC] (#129137)   via llvm-commits
• [llvm] [RISCV][TTI] Fix a misuse of the getShuffleCost API [NFC] (PR #129137)   Philip Reames via llvm-commits
• [llvm] 4904728 - [RISCV][TTI] Add shuffle costing for masked slide lowering (#128537)   via llvm-commits
• [llvm] [RISCV][TTI] Add shuffle costing for masked slide lowering (PR #128537)   Philip Reames via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] [X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (PR #128910)   Phoebe Wang via llvm-commits
• [llvm] [RISCV] Move RISCV vector load/store searchable tables from RISCVISelDAGToDAG.cpp to RISCVBaseInfo.cpp. NFC (PR #129172)   Craig Topper via llvm-commits
• [llvm] 8138775 - [RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (#129130)   via llvm-commits
• [llvm] [RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (PR #129130)   Craig Topper via llvm-commits
• [llvm] 0b5bb12 - [RISCV] Move RISCV vector load/store searchable tables from RISCVISelDAGToDAG.cpp to RISCVBaseInfo.cpp. NFC (#129172)   via llvm-commits
• [llvm] [RISCV] Move RISCV vector load/store searchable tables from RISCVISelDAGToDAG.cpp to RISCVBaseInfo.cpp. NFC (PR #129172)   Craig Topper via llvm-commits
• [llvm] [windows] Always pass libcall fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [llvm] [RISCV] Move RISCV vector load/store searchable tables from RISCVISelDAGToDAG.cpp to RISCVBaseInfo.cpp. NFC (PR #129172)   LLVM Continuous Integration via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Chuanqi Xu via llvm-commits
• [polly] fix(polly/**.py): fix comparison to True/False (PR #94042)   Eisuke Kawashima via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   via llvm-commits
• [llvm] [libc][bazel] Add py_binary rule to build hdrgen. (PR #129161)   Alexey Samsonov via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_Merge and ICMP (PR #128913)   Brox Chen via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   Amir Ayupov via llvm-commits
• [llvm] 8493467 - [JITLink][AArch64] Ensure that nulls remain null during ptrauth signing.   Lang Hames via llvm-commits
• [clang] [llvm] [Clang][AMDGPU] Use 32-bit index for SWMMAC builtins (PR #129101)   Shilei Tian via llvm-commits
• [llvm] [NVPTX] Delete `IsSimpleMove` (NFC) (PR #129178)   Justin Fargnoli via llvm-commits
• [llvm] [NVPTX] Delete `IsSimpleMove` (NFC) (PR #129178)   via llvm-commits
• [llvm] [NVPTX] Delete `IsSimpleMove` (NFC) (PR #129178)   Justin Fargnoli via llvm-commits
• [llvm] [NVPTX] Add intrinsics for st.bulk instruction (PR #128856)   Srinivasa Ravi via llvm-commits
• [llvm] [AMDGPU] Ensure divergence for v_alignbit (PR #129159)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Ensure divergence for v_alignbit (PR #129159)   Matt Arsenault via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   Johannes Doerfert via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   Matt Arsenault via llvm-commits
• [llvm] [RISCV] Improve assembler error message for Zcmp stack adjustment. (PR #129180)   Craig Topper via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   via llvm-commits
• [llvm] [RISCV] Improve assembler error message for Zcmp stack adjustment. (PR #129180)   via llvm-commits
• [llvm] [RISCV] Improve assembler error message for Zcmp stack adjustment. (PR #129180)   via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   Matt Arsenault via llvm-commits
• [llvm] [NVPTX] Add intrinsics for st.bulk instruction (PR #128856)   Alex MacLean via llvm-commits
• [llvm] [Attributor][NFC] Clang format (PR #129163)   Shilei Tian via llvm-commits
• [llvm] [Attributor][NFC] Clang format (PR #129163)   Shilei Tian via llvm-commits
• [llvm] 9f28621 - [Attributor][NFC] Clang format (#129163)   via llvm-commits
• [llvm] [Attributor][NFC] Clang format (PR #129163)   Shilei Tian via llvm-commits
• [llvm] [Attributor][NFC] Improve test (PR #129165)   Shilei Tian via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   Johannes Doerfert via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   Johannes Doerfert via llvm-commits
• [llvm] [RISCV] Improve assembler error message for Zcmp stack adjustment. (PR #129180)   via llvm-commits
• [llvm] [Attributor] Treat `byval` arguments as objects (PR #129162)   Shilei Tian via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Craig Topper via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   Shilei Tian via llvm-commits
• [llvm] [RISCV] Intrinsic Support for XCVelw (PR #129168)   via llvm-commits
• [llvm] [windows] Always pass libcall fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [llvm] [windows] Always pass libcall fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [llvm] [windows] Always pass libcall fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   Johannes Doerfert via llvm-commits
• [llvm] [Attributor][NFC] Improve test (PR #129165)   Johannes Doerfert via llvm-commits
• [llvm] [windows] Always pass libcall fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [llvm] [RISCV] Intrinsic Support for XCVelw (PR #129168)   via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   via llvm-commits
• [llvm] IRBuilder: Add FastMathFlags parameter to CreateMaxNum/CreateMinNum (PR #129173)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU] Avoid repeated hash lookups (NFC) (PR #129189)   Kazu Hirata via llvm-commits
• [llvm] [AMDGPU] Avoid repeated hash lookups (NFC) (PR #129189)   via llvm-commits
• [llvm] [CodeGen] Avoid repeated hash lookups (NFC) (PR #129190)   Kazu Hirata via llvm-commits
• [llvm] [ExecutionEngine] Avoid repeated hash lookups (NFC) (PR #129191)   Kazu Hirata via llvm-commits
• [llvm] [AMDGPU] Avoid repeated hash lookups (NFC) (PR #129189)   Matt Arsenault via llvm-commits
• [llvm] [MCA] Avoid repeated hash lookups (NFC) (PR #129192)   Kazu Hirata via llvm-commits
• [llvm] [MCA] Avoid repeated hash lookups (NFC) (PR #129192)   via llvm-commits
• [llvm] [PowerPC] Avoid repeated hash lookups (NFC) (PR #129193)   Kazu Hirata via llvm-commits
• [llvm] [PowerPC] Avoid repeated hash lookups (NFC) (PR #129193)   via llvm-commits
• [llvm] [ProfileData] Avoid repeated hash lookups (NFC) (PR #129194)   Kazu Hirata via llvm-commits
• [llvm] [ProfileData] Avoid repeated hash lookups (NFC) (PR #129194)   via llvm-commits
• [llvm] [ProfileData] Avoid repeated hash lookups (NFC) (PR #129194)   Mingming Liu via llvm-commits
• [llvm] [RFC][BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [llvm] AMDGPU: Add baseline tests for simplify elts of readfirstlane (PR #128645)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Add baseline tests for simplify elts of readfirstlane (PR #128645)   Matt Arsenault via llvm-commits
• [llvm] 2fa6c52 - AMDGPU: Add baseline tests for simplify elts of readfirstlane (#128645)   via llvm-commits
• [llvm] AMDGPU: Add baseline tests for simplify elts of readfirstlane (PR #128645)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Simplify demanded vector elts of readfirstlane sources (PR #128646)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Simplify demanded vector elts of readfirstlane sources (PR #128646)   Matt Arsenault via llvm-commits
• [llvm] [RFC][BPF] Report Unreachable Behavior from IR (PR #126858)   via llvm-commits
• [llvm] d410f09 - AMDGPU: Simplify demanded vector elts of readfirstlane sources (#128646)   via llvm-commits
• [llvm] AMDGPU: Simplify demanded vector elts of readfirstlane sources (PR #128646)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Reduce readfirstlane for single demanded vector element (PR #128647)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Reduce readfirstlane for single demanded vector element (PR #128647)   Matt Arsenault via llvm-commits
• [llvm] b215282 - Revert "[RISCV][TTI] Add shuffle costing for masked slide lowering (#128537)"   Philip Reames via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] True16 Add OpSel when optimizing exec mask (PR #128928)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] True16 Add OpSel when optimizing exec mask (PR #128928)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Add mir test for agpr constant reg_sequence handling (PR #129058)   Matt Arsenault via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   Sushant Gokhale via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   Sushant Gokhale via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   Sushant Gokhale via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   Sushant Gokhale via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   Sushant Gokhale via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   Sushant Gokhale via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   Sushant Gokhale via llvm-commits
• [llvm] 9fefc01 - [GVN/PRE] Remove triple from GVN/PRE tests (#129073)   via llvm-commits
• [llvm] [GVN/PRE] Remove triple from GVN/PRE tests (PR #129073)   Madhur Amilkanthwar via llvm-commits
• [llvm] [GSYM] Use debug line offsets during GSYM creation (PR #129196)   via llvm-commits
• [clang] [llvm] [X86][CodeGen] - Use shift operators instead of built-ins for SSE emulation of MMX intrinsics. (PR #129197)   Pawan Nirpal via llvm-commits
• [lld] [lld][LoongArch] Relax call36/tail36: R_LARCH_CALL36 (PR #123576)   Lu Weining via llvm-commits
• [llvm] [GSYM] Use debug line offsets during GSYM creation (PR #129196)   via llvm-commits
• [clang] [llvm] [X86][CodeGen] - Use shift operators instead of built-ins for SSE emulation of MMX intrinsics. (PR #129197)   Pawan Nirpal via llvm-commits
• [llvm] [GSYM] Use debug line offsets during GSYM creation (PR #129196)   via llvm-commits
• [llvm] [GSYM] Use debug line offsets during GSYM creation (PR #129196)   via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Erik Jensen via llvm-commits
• [llvm] [GSYM] Use debug line offsets during GSYM creation (PR #129196)   via llvm-commits
• [clang] [llvm] [X86][CodeGen] - Use shift operators instead of built-ins for SSE emulation of MMX intrinsics. (PR #129197)   Pawan Nirpal via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Chuanqi Xu via llvm-commits
• [llvm] 97da085 - [PowerPC] Simplify ELFStreamer and XCOFFStreamer   Fangrui Song via llvm-commits
• [clang] [llvm] [X86][CodeGen] - Use shift operators instead of built-ins for SSE emulation of MMX intrinsics. (PR #129197)   Matt Arsenault via llvm-commits
• [llvm] 50064db - [AMDGPU] Avoid repeated hash lookups (NFC) (#129189)   via llvm-commits
• [llvm] [AMDGPU] Avoid repeated hash lookups (NFC) (PR #129189)   Kazu Hirata via llvm-commits
• [llvm] 192b13b - [ProfileData] Avoid repeated hash lookups (NFC) (#129194)   via llvm-commits
• [llvm] [ProfileData] Avoid repeated hash lookups (NFC) (PR #129194)   Kazu Hirata via llvm-commits
• [llvm] [RISCV] Improve assembler error message for Zcmp stack adjustment. (PR #129180)   Sam Elliott via llvm-commits
• [llvm] [PowerPC] Avoid repeated hash lookups (NFC) (PR #129193)   via llvm-commits
• [llvm] [CodeGen] Avoid repeated hash lookups (NFC) (PR #129190)   via llvm-commits
• [llvm] 497d4f1 - [SPIRV] Remove unused variable. NFC   Craig Topper via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   Matt Arsenault via llvm-commits
• [llvm] f4aea13 - [PowerPC] Avoid repeated hash lookups (NFC) (#129193)   via llvm-commits
• [llvm] [PowerPC] Avoid repeated hash lookups (NFC) (PR #129193)   Kazu Hirata via llvm-commits
• [llvm] 44b9f5e - [CodeGen] Avoid repeated hash lookups (NFC) (#129190)   via llvm-commits
• [llvm] [CodeGen] Avoid repeated hash lookups (NFC) (PR #129190)   Kazu Hirata via llvm-commits
• [llvm] Introduce CovMap in ObjectYAML (PR #127432)   Jessica Paquette via llvm-commits
• [lld] [WASM] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] Introduce CovMap in ObjectYAML (PR #127432)   Jessica Paquette via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] Introduce CovMap in ObjectYAML (PR #127432)   Jessica Paquette via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_Merge and ICMP (PR #128913)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_Merge and ICMP (PR #128913)   Matt Arsenault via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_Merge and ICMP (PR #128913)   Matt Arsenault via llvm-commits
• [llvm] Introduce CovMap in ObjectYAML (PR #127432)   Jessica Paquette via llvm-commits
• [lld] [WASM] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [lld] [WASM] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [lld] [WASM] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Jonathan Thackray via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Jonathan Thackray via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   Johannes Doerfert via llvm-commits
• [lld] [WASM] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [clang] [llvm] [X86][CodeGen] - Use shift operators instead of built-ins for SSE emulation of MMX intrinsics. (PR #129197)   Phoebe Wang via llvm-commits
• [lld] [WASM] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Hua Tian via llvm-commits
• [llvm] [SystemZ] Drop regstate of SELRMux operand in selectSLRMux(). (PR #128555)   Ulrich Weigand via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Matt Arsenault via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Hua Tian via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Hua Tian via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   James Henderson via llvm-commits
• [llvm] [llvm-size] Add test for invalid conversion spec on error (PR #128941)   James Henderson via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Matt Arsenault via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Matt Arsenault via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   Matt Arsenault via llvm-commits
• [llvm] Support: Do not check if a file exists before executing (PR #128821)   Marek Sedláček via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Hua Tian via llvm-commits
• [llvm] [MachinePipeliner] Improve loop carried dependence analysis (PR #94185)   Afanasyev Ivan via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Hans Wennborg via llvm-commits
• [llvm] [llvm][ELF]Add Shdr check for getBuildID (PR #126537)   James Henderson via llvm-commits
• [llvm] [llvm][ELF]Add Shdr check for getBuildID (PR #126537)   James Henderson via llvm-commits
• [llvm] [llvm][ELF]Add Shdr check for getBuildID (PR #126537)   James Henderson via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Hans Wennborg via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Jack Styles via llvm-commits
• [llvm] [windows] Always pass libcall fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   Hans Wennborg via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   James Chesterman via llvm-commits
• [llvm] [RISCV] Improve assembler error message for Zcmp stack adjustment. (PR #129180)   Pengcheng Wang via llvm-commits
• [llvm] [RISCV] Improve assembler error message for Zcmp stack adjustment. (PR #129180)   Pengcheng Wang via llvm-commits
• [llvm] [RISCV] Improve assembler error message for Zcmp stack adjustment. (PR #129180)   Pengcheng Wang via llvm-commits
• [clang] [llvm] [Coroutines] Mark parameter allocas with coro.outside.frame metadata (PR #127653)   LLVM Continuous Integration via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   James Chesterman via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   James Chesterman via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   James Chesterman via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   James Chesterman via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   James Chesterman via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   James Henderson via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   James Henderson via llvm-commits
• [lld] [WASM] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [llvm] [llvm][ELF]Add Shdr check for getBuildID (PR #126537)   Ruoyu Qiu via llvm-commits
• [lld] [WASM] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [lld] [WASM] wasm-ld: split up __wasm_apply_data_relocs (PR #129007)   via llvm-commits
• [llvm] [ExecutionEngine] Avoid repeated hash lookups (NFC) (PR #129191)   Nikita Popov via llvm-commits
• [llvm] [MCA] Avoid repeated hash lookups (NFC) (PR #129192)   Nikita Popov via llvm-commits
• [llvm] [RISCV] Add DAG combine to convert (iN reduce.add (zext (vXi1 A to vXiN)) into vcpop.m (PR #127497)   Sergey Kachkov via llvm-commits
• [llvm] [windows] Always pass fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [llvm] [windows] Always pass fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [llvm] [windows] Always pass fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   Virginia Cangelosi via llvm-commits
• [llvm] IRBuilder: Add FMFSource parameter to CreateMaxNum/CreateMinNum (PR #129173)   via llvm-commits
• [clang] [llvm] [X86][CodeGen] - Use shift operators instead of built-ins for SSE emulation of MMX intrinsics. (PR #129197)   Phoebe Wang via llvm-commits
• [llvm] [IPSCCP] Push constant struct params into callees (PR #111805)   Matthew Devereau via llvm-commits
• [llvm] Enable logf128 constant folding for hosts with 128bit long double (PR #106563)   Matthew Devereau via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Hua Tian via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Hua Tian via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Hua Tian via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   David Green via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-multi vectors MOP4{A/S} (PR #128854)   Virginia Cangelosi via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] 0ba4767 - [AMDGPU] Cosmetic tweaks in AMDGPUAtomicOptimizer. NFC. (#129081)   via llvm-commits
• [llvm] [AMDGPU] Cosmetic tweaks in AMDGPUAtomicOptimizer. NFC. (PR #129081)   Jay Foad via llvm-commits
• [llvm] [MCA] Adding missing instructions in AArch64 Neoverse V1 tests (PR #128892)   Julien Villette via llvm-commits
• [llvm] abd97d9 - [CaptureTracking] Take non-willreturn calls into account   Nikita Popov via llvm-commits
• [llvm] [PreISelIntrinsicLowering] Support producing memset_pattern16 when loading from constant global (PR #129220)   Alex Bradbury via llvm-commits
• [llvm] [PreISelIntrinsicLowering] Support producing memset_pattern16 when loading from constant global (PR #129220)   via llvm-commits
• [llvm] AMDGPU/GlobalISel: Restore disabled test (PR #129001)   Petar Avramovic via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] 6a46cf4 - AMDGPU/GlobalISel: Restore disabled test (#129001)   via llvm-commits
• [llvm] AMDGPU/GlobalISel: Restore disabled test (PR #129001)   Matt Arsenault via llvm-commits
• [llvm] FEAT: (PR #129222)   via llvm-commits
• [llvm] FEAT: (PR #129222)   via llvm-commits
• [llvm] FEAT: (PR #129222)   via llvm-commits
• [compiler-rt] [tsan][RISCV] Add Go support for linux/riscv64 (PR #127295)   Pengcheng Wang via llvm-commits
• [compiler-rt] 76910f9 - [tsan][RISCV] Add Go support for linux/riscv64 (#127295)   via llvm-commits
• [llvm] [AMDGPU][NFC] Use a worklist and remember results (PR #129175)   Jay Foad via llvm-commits
• [llvm] 1aea024 - [LLVM][SVE] Add isel for bfloat based select operations. (#128881)   via llvm-commits
• [llvm] [LLVM][SVE] Add isel for bfloat based select operations. (PR #128881)   Paul Walker via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   Ruoyu Qiu via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   Ruoyu Qiu via llvm-commits
• [llvm] [llvm-objdump][ELF]Fix crash when reading strings from .dynstr (PR #125679)   Ruoyu Qiu via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement multi-single vectors MOP4{A/S} (PR #129226)   Jonathan Thackray via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Pengcheng Wang via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [LAA] Consider accessed addrspace when mapping underlying obj to access. (PR #129087)   Michael Kruse via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [clang] [llvm] [WIP] Correct lowering of `fp128` intrinsics (PR #76558)   Trevor Gross via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [AMDGPU] Simplify conditional expressions. NFC. (PR #129228)   Jay Foad via llvm-commits
• [llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)   Paul Walker via llvm-commits
• [llvm] [AMDGPU] Simplify conditional expressions. NFC. (PR #129228)   via llvm-commits
• [llvm] [LLVM][SVE] Improve code generation for i1 based int_to_fp operations. (PR #129229)   Paul Walker via llvm-commits
• [llvm] [LLVM][SVE] Improve code generation for i1 based int_to_fp operations. (PR #129229)   via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [llvm] [LLVM][SVE] Improve code generation for i1 based int_to_fp operations. (PR #129229)   Paul Walker via llvm-commits
• [llvm] [LLVM][SVE] Improve code generation for i1 based int_to_fp operations. (PR #129229)   Paul Walker via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Jay Foad via llvm-commits
• [llvm] [LLVM][SVE] Improve code generation for i1 based int_to_fp operations. (PR #129229)   Paul Walker via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Jay Foad via llvm-commits
• [llvm] [DA] do not handle array accesses of different offsets (PR #123436)   Michael Kruse via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement multi-multi vectors MOP4{A/S} (PR #129230)   Virginia Cangelosi via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] remove extraneous comma in OpLifetimeStart and OpLifetimeStop (PR #129025)   via llvm-commits
• [llvm] [LoopPeel] Peel to make Phis loop inductions (PR #121104)   Ryotaro Kasuga via llvm-commits
• [llvm] [libc++] [ci] Update the Windows toolchains to Clang 19 (PR #129232)   Martin Storsjö via llvm-commits
• [llvm] [libc++] [ci] Update the Windows toolchains to Clang 19 (PR #129232)   via llvm-commits
• [llvm] [libc++] [ci] Update the Windows toolchains to Clang 19 (PR #129232)   via llvm-commits
• [llvm] [libc++] [ci] Update the Windows toolchains to Clang 19 (PR #129232)   Nikolas Klauser via llvm-commits
• [llvm] [cpack][NSIS Installer] Make installer DPI-Aware (PR #128470)   Alexandre Ganea via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)   Ricardo Jesus via llvm-commits
• [llvm] remove extraneous comma in OpLifetimeStart and OpLifetimeStop (PR #129025)   via llvm-commits
• [llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)   Paul Walker via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   via llvm-commits
• [llvm] [CodeGen] Expansion of scalable vector reductions (PR #129214)   via llvm-commits
• [llvm] [LoopPeel] Peel to make Phis loop inductions (PR #121104)   Ryotaro Kasuga via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [Premerge] Add flang-rt (PR #128678)   Michael Kruse via llvm-commits
• [clang] [llvm] [X86][CodeGen] - Use shift operators for const value shifts, instead of built-ins for SSE emulation of MMX intrinsics. (PR #129197)   Pawan Nirpal via llvm-commits
• [flang] [llvm] [Flang] Remove FLANG_INCLUDE_RUNTIME (PR #124126)   Michael Kruse via llvm-commits
• [llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)   Paul Walker via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [flang] [llvm] [Flang] Remove FLANG_INCLUDE_RUNTIME (PR #124126)   Michael Kruse via llvm-commits
• [flang] [llvm] [Flang] Remove FLANG_INCLUDE_RUNTIME (PR #124126)   Michael Kruse via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)   Ana Mihajlovic via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [Premerge] Add flang-rt (PR #128678)   Michael Kruse via llvm-commits
• [llvm] [Premerge] Add flang-rt (PR #128678)   Michael Kruse via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [Premerge] Add flang-rt (PR #128678)   Michael Kruse via llvm-commits
• [llvm] 89e7f4d - [LV] Teach the vectorizer to cost and vectorize modf and sincospi intrinsics (#129064)   via llvm-commits
• [llvm] [LV] Teach the vectorizer to cost and vectorize modf and sincospi intrinsics (PR #129064)   Benjamin Maxwell via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] 26fc3aa - [OpenMP] Missing implicit otherwise clause in metadirective. (#127113)   via llvm-commits
• [clang] [llvm] [OpenMP] Missing implicit otherwise clause in metadirective. (PR #127113)   Zahira Ammarguellat via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] AMDGPU: Remove nocapture attribute from is.shared and is.private intrinsics (PR #129238)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Remove nocapture attribute from is.shared and is.private intrinsics (PR #129238)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Remove nocapture attribute from is.shared and is.private intrinsics (PR #129238)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Remove nocapture attribute from is.shared and is.private intrinsics (PR #129238)   via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [clang] [llvm] [X86][CodeGen] - Use shift operators for const value shifts, instead of built-ins for SSE emulation of MMX intrinsics. (PR #129197)   Evgenii Kudriashov via llvm-commits
• [clang] [llvm] [X86][CodeGen] - Use shift operators for const value shifts, instead of built-ins for SSE emulation of MMX intrinsics. (PR #129197)   Evgenii Kudriashov via llvm-commits
• [llvm] [libc++] [ci] Update the Windows toolchains to Clang 19 (PR #129232)   A. Jiang via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [PreISelIntrinsicLowering] Zext/trunc count parameter as necessary for memset_pattern16 emission (PR #129239)   Alex Bradbury via llvm-commits
• [llvm] [PreISelIntrinsicLowering] Zext/trunc count parameter as necessary for memset_pattern16 emission (PR #129239)   via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   Sebastian Schaller via llvm-commits
• [llvm] [LLVM][SVE] Improve code generation for i1 based int_to_fp operations. (PR #129229)   David Sherwood via llvm-commits
• [llvm] AMDGPU: Remove nocapture attribute from is.shared and is.private intrinsics (PR #129238)   Jay Foad via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   Sebastian Schaller via llvm-commits
• [llvm] Addition of @llvm.lround.* and @llvm.llround.* intrinsic (PR #129240)   Aadesh PremKumar via llvm-commits
• [llvm] Obviously Redundant Assert In AsmWriter (PR #128543)   JP Hafer via llvm-commits
• [llvm] Addition of @llvm.lround.* and @llvm.llround.* intrinsic (PR #129240)   via llvm-commits
• [llvm] Addition of @llvm.lround.* and @llvm.llround.* intrinsic (PR #129240)   via llvm-commits
• [llvm] AMDGPU: Remove nocapture attribute from is.shared and is.private intrinsics (PR #129238)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Remove nocapture attribute from is.shared and is.private intrinsics (PR #129238)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Remove nocapture attribute from is.shared and is.private intrinsics (PR #129238)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen] Expansion of scalable vector reductions (PR #129214)   Matt Arsenault via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   JP Hafer via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   via llvm-commits
• [llvm] 5d89123 - [X86] Add tests for sspstrong with phi nodes (NFC)   Nikita Popov via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   Benjamin Maxwell via llvm-commits
• [llvm] [CodeGen] Expansion of scalable vector reductions (PR #129214)   David Green via llvm-commits
• [llvm] c298f71 - [SystemZ] Fix regstate of SELRMux operand in selectSLRMux(). (#128555)   via llvm-commits
• [llvm] [SystemZ] Drop regstate of SELRMux operand in selectSLRMux(). (PR #128555)   Jonas Paulsson via llvm-commits
• [llvm] [NFC]Make file-local cl::opt global variables static (PR #126486)   Sergei Barannikov via llvm-commits
• [llvm] [llvm-diff] Diff attributes & metadata (PR #129247)   via llvm-commits
• [llvm] [llvm-diff] Diff attributes & metadata (PR #129247)   via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   JP Hafer via llvm-commits
• [llvm] [StackProtector] Fix phi handling in HasAddressTaken() (PR #129248)   Nikita Popov via llvm-commits
• [llvm] [StackProtector] Fix phi handling in HasAddressTaken() (PR #129248)   via llvm-commits
• [llvm] [StackProtector] Fix phi handling in HasAddressTaken() (PR #129248)   via llvm-commits
• [llvm] [SPIR-V] Prevent type change of GEP results in type inference (PR #129250)   Vyacheslav Levytskyy via llvm-commits
• [llvm] [StackProtector] Fix phi handling in HasAddressTaken() (PR #129248)   Nikita Popov via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Frederik Harwath via llvm-commits
• [llvm] [llvm-diff] Diff attributes & metadata (PR #129247)   via llvm-commits
• [llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)   Frederik Harwath via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   Matt Arsenault via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [clang] [lld] [llvm] Integrated Distributed ThinLTO (DTLTO): Initial support (PR #126654)   via llvm-commits
• [clang] [llvm] [Coroutines] Replace coro.outside.frame metadata with an intrinsic (PR #129255)   via llvm-commits
• [clang] [llvm] [Coroutines] Replace coro.outside.frame metadata with an intrinsic (PR #129255)   via llvm-commits
• [clang] [llvm] [Coroutines] Replace coro.outside.frame metadata with an intrinsic (PR #129255)   via llvm-commits
• [llvm] [RISCV] and x (sub 0, y) -> andn x y (PR #129253)   Gábor Spaits via llvm-commits
• [clang] [llvm] [Coroutines] Replace coro.outside.frame metadata with an intrinsic (PR #129255)   via llvm-commits
• [clang] [llvm] [Coroutines] Replace coro.outside.frame metadata with an intrinsic (PR #129255)   Hans Wennborg via llvm-commits
• [clang] [llvm] [Coroutines] Replace coro.outside.frame metadata with an intrinsic (PR #129255)   Hans Wennborg via llvm-commits
• [clang] [llvm] [Coroutines] Replace coro.outside.frame metadata with an intrinsic (PR #129255)   Hans Wennborg via llvm-commits
• [clang] [llvm] [Coroutines] Replace coro.outside.frame metadata with an intrinsic (PR #129255)   Hans Wennborg via llvm-commits
• [clang] [llvm] [Coroutines] Replace coro.outside.frame metadata with an intrinsic (PR #129255)   Hans Wennborg via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   David Green via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   David Green via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   David Green via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [RISCV] and x (sub 0, y) -> andn x y (PR #129253)   Gábor Spaits via llvm-commits
• [llvm] [libc++] [ci] Update the Windows toolchains to Clang 19 (PR #129232)   Louis Dionne via llvm-commits
• [compiler-rt] [flang] [llvm] [AArch64] fix trampoline implementation: use X15 (PR #126743)   Carlos Seo via llvm-commits
• [llvm] [InstCombine] Add support for GEPs in `simplifyNonNullOperand` (PR #128365)   via llvm-commits
• [llvm] [RISCV] and x (sub 0, y) -> andn x y (PR #129253)   Jay Foad via llvm-commits
• [llvm] [Attributor] Do not optimize away externally_initialized loads. (PR #128170)   Nikita Popov via llvm-commits
• [llvm] AMDGPU/GlobalISel: Disable LCSSA pass (PR #124297)   Petar Avramovic via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [CodeGen] Combine two loops in SloIndexes.cpp file (PR #127631)   via llvm-commits
• [llvm] [InstCombine] Add support for GEPs in `simplifyNonNullOperand` (PR #128365)   Nikita Popov via llvm-commits
• [llvm] AMDGPU GlobalISel Add64 support (PR #124763)   Alan Li via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   Tomas Matheson via llvm-commits
• [llvm] [SLP]Fix/improve getSpillCost analysis (PR #129258)   Alexey Bataev via llvm-commits
• [llvm] [SLP]Fix/improve getSpillCost analysis (PR #129258)   via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [SLP]Fix/improve getSpillCost analysis (PR #129258)   via llvm-commits
• [llvm] [RISCV] and x (sub 0, y) -> andn x y (PR #129253)   Gábor Spaits via llvm-commits
• [llvm] AMDGPU GlobalISel Add64 support (PR #124763)   Alan Li via llvm-commits
• [llvm] 94f6b6d - [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (#128800)   via llvm-commits
• [llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)   Jim Lin via llvm-commits
• [llvm] AMDGPU GlobalISel Add64 support (PR #124763)   Alan Li via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)   Ricardo Jesus via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   JP Hafer via llvm-commits
• [llvm] [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (PR #128739)   Lucas Ramirez via llvm-commits
• [llvm] [RISCV] and x (sub 0, y) -> andn x y (PR #129253)   Gábor Spaits via llvm-commits
• [llvm] IRBuilder: Add FMFSource parameter to CreateMaxNum/CreateMinNum (PR #129173)   Matt Arsenault via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   JP Hafer via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [AMDGPU] Add ISel patterns for `v_lshl_add_u64` (PR #124763)   Alan Li via llvm-commits
• [llvm] [AMDGPU] Add ISel patterns for `v_lshl_add_u64` (PR #124763)   Alan Li via llvm-commits
• [llvm] a73e591 - [PowerPC] custom lower v1024i1 load/store (#126969)   via llvm-commits
• [llvm] [PowerPC] custom lower v1024i1 load/store (PR #126969)   via llvm-commits
• [clang] [llvm] [llvm:ir] Add support for constant data exceeding 4GiB (PR #126481)   via llvm-commits
• [llvm] [RISCV] and x (sub 0, y) -> andn x y (PR #129253)   Gábor Spaits via llvm-commits
• [llvm] [PreISelIntrinsicLowering] Support producing memset_pattern16 when loading from constant global (PR #129220)   Nikita Popov via llvm-commits
• [llvm] [SPIR-V] Prevent type change of GEP results in type inference (PR #129250)   Vyacheslav Levytskyy via llvm-commits
• [llvm] [RISCV] and x (sub -1, y) -> andn x y (PR #129253)   Gábor Spaits via llvm-commits
• [llvm] [X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (PR #128910)   Daniel Zabawa via llvm-commits
• [llvm] [SPIR-V] Prevent type change of GEP results in type inference (PR #129250)   via llvm-commits
• [llvm] 2639dea - [gn build] Port 15c49b9db3f6   Nico Weber via llvm-commits
• [clang] [llvm] [llvm:ir] Add support for constant data exceeding 4GiB (PR #126481)   via llvm-commits
• [llvm] [libc++] [ci] Update the Windows toolchains to Clang 19 (PR #129232)   Martin Storsjö via llvm-commits
• [llvm] [SDAG] Add missing float type legalizations for FMODF (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   James Chesterman via llvm-commits
• [clang] [llvm] [clang][CodeGen][AA] Add `!llvm.errno.tbaa` gathering int-compatible TBAA nodes (PR #125258)   Nikita Popov via llvm-commits
• [llvm] [SDAG][X86] Remove hack needed to avoid missing x87 FPU stack pops (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   James Chesterman via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Nikita Popov via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Nikita Popov via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Nikita Popov via llvm-commits
• [libc] [llvm] Add sysexits.h header with BSD exit codes (total-18) (PR #126112)   via llvm-commits
• [llvm] [FunctionAttrs] Add `errno` inference logic (PR #129067)   Nikita Popov via llvm-commits
• [lld] wasm-ld: Implement function pointer alignment (PR #105532)   Sam Clegg via llvm-commits
• [llvm] 248be98 - Reapply "[RISCV][TTI] Add shuffle costing for masked slide lowering (#128537)"   Philip Reames via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   JP Hafer via llvm-commits
• [llvm] [PowerPC] hoist xxspltib out of the loop (PR #127121)   zhijian lin via llvm-commits
• [llvm] [PowerPC] hoist xxspltib out of the loop (PR #127121)   zhijian lin via llvm-commits
• [llvm] [SLP]Fix/improve getSpillCost analysis (PR #129258)   Alexey Bataev via llvm-commits
• [llvm] 9af10e3 - [ExecutionEngine] Avoid repeated hash lookups (NFC) (#129191)   via llvm-commits
• [llvm] [ExecutionEngine] Avoid repeated hash lookups (NFC) (PR #129191)   Kazu Hirata via llvm-commits
• [llvm] b2525dc - [MCA] Avoid repeated hash lookups (NFC) (#129192)   via llvm-commits
• [llvm] [MCA] Avoid repeated hash lookups (NFC) (PR #129192)   Kazu Hirata via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Nikita Popov via llvm-commits
• [llvm] [BOLT] Report flow conservation scores (PR #127954)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [clang] [llvm] [Clang][LLVM] Implement single-single vectors MOP4{A/S} (PR #127797)   via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   JP Hafer via llvm-commits
• [llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)   Benjamin Maxwell via llvm-commits
• [llvm] [InstCombine] Merge consecutive loads of mixed sizes (PR #129263)   Zhenyang Xu via llvm-commits
• [llvm] 3f63e1c - [gn build] Port 7e33bebe7c8c   LLVM GN Syncbot via llvm-commits
• [llvm] [InstCombine] Merge consecutive loads of mixed sizes (PR #129263)   via llvm-commits
• [llvm] [InstCombine] Merge consecutive loads of mixed sizes (PR #129263)   via llvm-commits
• [llvm] [SDAG] Add missing SoftenFloatRes legalization for FMODF (PR #129264)   Benjamin Maxwell via llvm-commits
• [llvm] [SDAG] Add missing SoftenFloatRes legalization for FMODF (PR #129264)   via llvm-commits
• [llvm] [SDAG] Add missing SoftenFloatRes legalization for FMODF (PR #129264)   via llvm-commits
• [llvm] [LoopVectorize] Don't scalarize predicated instruction with optsize (PR #129265)   John Brawn via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   Ali Raeisdanaei via llvm-commits
• [llvm] [LoopVectorize] Don't scalarize predicated instruction with optsize (PR #129265)   via llvm-commits
• [llvm] [RISCV] and x (sub -1, y) -> andn x y (PR #129253)   Craig Topper via llvm-commits
• [llvm] [LoopVectorize] Don't scalarize predicated instruction with optsize (PR #129265)   via llvm-commits
• [llvm] [RISCV] and x (sub -1, y) -> andn x y (PR #129253)   Gábor Spaits via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [llvm] [RISCV] and x (sub -1, y) -> andn x y (PR #129253)   Gábor Spaits via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] [LoopVectorize] Don't discount instructions scalarized due to tail folding (PR #109289)   John Brawn via llvm-commits
• [llvm] [LoopVectorize] Don't discount instructions scalarized due to tail folding (PR #109289)   John Brawn via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [SPIR-V] Prevent type change of GEP results in type inference (PR #129250)   Nathan Gauër via llvm-commits
• [llvm] [RISCV] and x (sub -1, y) -> andn x y (PR #129253)   Sergei Barannikov via llvm-commits
• [llvm] [RISCV] and x (sub -1, y) -> andn x y (PR #129253)   Craig Topper via llvm-commits
• [llvm] [RISCV] Add DAG combine to convert (iN reduce.add (zext (vXi1 A to vXiN)) into vcpop.m (PR #127497)   Philip Reames via llvm-commits
• [llvm] Refactored llvm::UpgradeIntrinsicCall() function in lib/IR/AutoUpgrade.cpp with lookup table based on #30382 (PR #128611)   Ali Raeisdanaei via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Antonio Frighetto via llvm-commits
• [llvm] [SLP]Fix/improve getSpillCost analysis (PR #129258)   Philip Reames via llvm-commits
• [llvm] [RISCV] and x (sub -1, y) -> andn x y (PR #129253)   Gábor Spaits via llvm-commits
• [llvm] [DirectX] Set module-level flag `LowPrecisionPresent` in DXIL Shader Flags Analysis (PR #129109)   Sarah Spall via llvm-commits
• [llvm] [SLP]Fix/improve getSpillCost analysis (PR #129258)   Mikhail R. Gadelha via llvm-commits
• [llvm] [RISCV] and x (sub -1, y) -> andn x y (PR #129253)   Craig Topper via llvm-commits
• [llvm] [DirectX] Set function-level flag Int64Ops in DXIL Shader Flags Analysis (PR #129089)   Sarah Spall via llvm-commits
• [llvm] [SelectionDAG] Do partial reduction lowering using ISD nodes (PR #129268)   James Chesterman via llvm-commits
• [llvm] c0bf4b2 - [VPlan] Remove unneeded VPValue::getLiveInIRValue() const (NFC).   Florian Hahn via llvm-commits
• [llvm] [LLVM][SVE] Implement isel for fptoi half/float/double to i1. (PR #129269)   Paul Walker via llvm-commits
• [llvm] [MachineSink] Extend loop sinking capability (PR #117247)   Philip Reames via llvm-commits
• [llvm] [LLVM][SVE] Implement isel for fptoi half/float/double to i1. (PR #129269)   via llvm-commits
• [llvm] 1b25c0c - [RISCV] Improve assembler error message for Zcmp stack adjustment. (#129180)   via llvm-commits
• [llvm] [RISCV] Improve assembler error message for Zcmp stack adjustment. (PR #129180)   Craig Topper via llvm-commits
• [clang] [llvm] [memprof] Export __memprof_default_options_str on Darwin (PR #128920)   Ellis Hoag via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [RISCV] Remove non-portable vsetvli instructions from llvm-mca test. NFC (PR #129134)   Philip Reames via llvm-commits
• [llvm] [RISCV] and x (sub -1, y) -> andn x y (PR #129253)   Gábor Spaits via llvm-commits
• [llvm] [SelectionDAG] Do partial reduction lowering using ISD nodes (PR #129268)   James Chesterman via llvm-commits
• [llvm] [DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (PR #129272)   Yingwei Zheng via llvm-commits
• [llvm] [DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (PR #129272)   via llvm-commits
• [llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)   Aiden Grossman via llvm-commits
• [llvm] [RISCV] and x (sub -1, y) -> andn x y (PR #129253)   Craig Topper via llvm-commits
• [llvm] [DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (PR #129272)   via llvm-commits
• [llvm] [RISCV] Remove non-portable vsetvli instructions from llvm-mca test. NFC (PR #129134)   Craig Topper via llvm-commits
• [llvm] [SelectionDAG] Do partial reduction lowering using ISD nodes (PR #129268)   James Chesterman via llvm-commits
• [llvm] [X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (PR #128910)   Daniel Zabawa via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   JP Hafer via llvm-commits
• [llvm] [RISCV] Improve assembler error message for Zcmp stack adjustment. (PR #129180)   Craig Topper via llvm-commits
• [llvm] [RISCV] Improve assembler error message for Zcmp stack adjustment. (PR #129180)   Craig Topper via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   JP Hafer via llvm-commits
• [llvm] [TableGen] Inherit properties from the nearest allocatable superclass. (PR #127018)   Pete Chou via llvm-commits
• [clang] [llvm] [AggressiveInstCombine] Shrink loads used in shufflevector rebroadcasts. (PR #128938)   Leon Clark via llvm-commits
• [clang] [llvm] [memprof] Export __memprof_default_options_str on Darwin (PR #128920)   Ellis Hoag via llvm-commits
• [llvm] [MachineSink] Extend loop sinking capability (PR #117247)   Jeffrey Byrnes via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   Fangrui Song via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   Fangrui Song via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Akshay Deodhar via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Akshay Deodhar via llvm-commits
• [llvm] [SelectionDAG] Do partial reduction lowering using ISD nodes (PR #129268)   James Chesterman via llvm-commits
• [llvm] [SandboxIR][Region][NFC] Change visibility of Region::add()/remove() (PR #129277)   via llvm-commits
• [llvm] 7c26356 - [llvm-objdump] Rework .gnu.version_d dumping   via llvm-commits
• [llvm] [llvm-objdump] Rework .gnu.version_d dumping (PR #128434)   Fangrui Song via llvm-commits
• [llvm] [SelectionDAG] Do partial reduction lowering using ISD nodes (PR #129268)   James Chesterman via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   JP Hafer via llvm-commits
• [llvm] Remove unneeded global inits (PR #129245)   JP Hafer via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Akshay Deodhar via llvm-commits
• [llvm] [InferAttrs] Mark errnomem-setting libcalls as such (PR #124742)   Antonio Frighetto via llvm-commits
• [llvm] [InferAttrs] Mark floating-point libcalls as errno-writing (PR #124742)   Antonio Frighetto via llvm-commits
• [llvm] [InferAttrs] Mark floating-point libcalls as errno-writing (PR #124742)   Antonio Frighetto via llvm-commits
• [llvm] Obviously Redundant Assert In AsmWriter (PR #128543)   JP Hafer via llvm-commits
• [llvm] [SelectionDAG] Do partial reduction lowering using ISD nodes (PR #129268)   James Chesterman via llvm-commits
• [llvm] [InferAttrs] Mark floating-point libcalls as errno-writing (PR #124742)   Antonio Frighetto via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Akshay Deodhar via llvm-commits
• [llvm] [SLP]Fix/improve getSpillCost analysis (PR #129258)   Alexey Bataev via llvm-commits
• [llvm] [SelectionDAG] Do partial reduction lowering using ISD nodes (PR #129268)   James Chesterman via llvm-commits
• [llvm] Obviously Redundant Assert In AsmWriter (PR #128543)   JP Hafer via llvm-commits
• [llvm] Obviously Redundant Assert In AsmWriter (PR #128543)   JP Hafer via llvm-commits
• [llvm] [LV][EVL] Support icmp/fcmp instruction with EVL-vectorization (PR #108533)   Philip Reames via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [llvm] [PowerPC] hoist xxspltib out of loop body (PR #127121)   Lei Huang via llvm-commits
• [llvm] [PowerPC] hoist xxspltib out of loop body (PR #127121)   Lei Huang via llvm-commits
• [llvm] [PowerPC] hoist xxspltib out of loop body (PR #127121)   Lei Huang via llvm-commits
• [llvm] [InlineCost] Don't call collectEphemeralValues() if too many assumptions (PR #129279)   via llvm-commits
• [llvm] [InlineCost] Don't call collectEphemeralValues() if too many assumptions (PR #129279)   via llvm-commits
• [llvm] [SLP]Fix/improve getSpillCost analysis (PR #129258)   Mikhail R. Gadelha via llvm-commits
• [llvm] 992b451 - [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (#129179)   via llvm-commits
• [llvm] [Utils][UnifyLoopExits] Avoid costly updates if nothing changed (PR #129179)   Johannes Doerfert via llvm-commits
• [llvm] [RISCV] Simplify getStackAdjBase. NFC (PR #129281)   Craig Topper via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Artem Belevich via llvm-commits
• [llvm] [RISCV] Simplify getStackAdjBase. NFC (PR #129281)   via llvm-commits
• [llvm] [AMDGPU][NFC] Use a worklist and remember results (PR #129175)   Johannes Doerfert via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [clang] [llvm] [win][x64] Unwind v2 3/n: Add support for emitting unwind v2 information (equivalent to MSVC /d2epilogunwind) (PR #129142)   Daniel Paoliello via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [llvm] [SLP]Fix/improve getSpillCost analysis (PR #129258)   Alexey Bataev via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [clang] [llvm] [win][x64] Unwind v2 3/n: Add support for emitting unwind v2 information (equivalent to MSVC /d2epilogunwind) (PR #129142)   Daniel Paoliello via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Sam Clegg via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Sam Clegg via llvm-commits
• [lld] [LLD][COFF] Add support for autoimports on ARM64X (PR #129282)   Jacek Caban via llvm-commits
• [lld] [LLD][COFF] Add support for autoimports on ARM64X (PR #129282)   via llvm-commits
• [llvm] [asan][x86] Abort instrumenting memintrinsics that target registers fs, gs (PR #129284)   Thor Preimesberger via llvm-commits
• [llvm] [asan][x86] Abort instrumenting memintrinsics that target registers fs, gs (PR #129284)   via llvm-commits
• [clang] [llvm] [memprof] Export __memprof_default_options_str on Darwin (PR #128920)   Teresa Johnson via llvm-commits
• [llvm] [RISCV] Simplify getStackAdjBase. NFC (PR #129281)   Sam Elliott via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Hood Chatham via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Hood Chatham via llvm-commits
• [llvm] [asan][x86] Abort instrumenting memintrinsics that target registers fs, gs (PR #129284)   via llvm-commits
• [llvm] [asan][x86] Abort instrumenting memintrinsics that target registers fs, gs (PR #129284)   Thor Preimesberger via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Sam Elliott via llvm-commits
• [clang] [llvm] [win][x64] Unwind v2 3/n: Add support for emitting unwind v2 information (equivalent to MSVC /d2epilogunwind) (PR #129142)   Eli Friedman via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   Sebastian Schaller via llvm-commits
• [clang] [llvm] [win][x64] Unwind v2 3/n: Add support for emitting unwind v2 information (equivalent to MSVC /d2epilogunwind) (PR #129142)   Eli Friedman via llvm-commits
• [clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)   Craig Topper via llvm-commits
• [clang] [llvm] [AggressiveInstCombine] Shrink loads used in shufflevector rebroadcasts. (PR #128938)   Ulrich Weigand via llvm-commits
• [llvm] 9da67e8 - [RISCV] Remove non-portable vsetvli instructions from llvm-mca test. NFC (#129134)   via llvm-commits
• [llvm] [RISCV] Remove non-portable vsetvli instructions from llvm-mca test. NFC (PR #129134)   Craig Topper via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   Sebastian Schaller via llvm-commits
• [llvm] [AMDGPU] Add ISel patterns for `v_lshl_add_u64` (PR #124763)   Alan Li via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Artem Belevich via llvm-commits
• [llvm] [AMDGPU] Add ISel patterns for `v_lshl_add_u64` (PR #124763)   Alan Li via llvm-commits
• [llvm] [asan][x86] Abort instrumenting memintrinsics that target registers fs, gs (PR #129284)   Thor Preimesberger via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Artem Belevich via llvm-commits
• [llvm] [MCA] Avoid repeated hash lookups (NFC) (PR #129192)   Andrea Di Biagio via llvm-commits
• [compiler-rt] [asan] Define mallopt and mallinfo for Fuchsia asan runtime (PR #129105)   Roland McGrath via llvm-commits
• [compiler-rt] [asan] Define mallopt and mallinfo for Fuchsia asan runtime (PR #129105)   Roland McGrath via llvm-commits
• [compiler-rt] [asan] Define mallopt and mallinfo for Fuchsia asan runtime (PR #129105)   Roland McGrath via llvm-commits
• [llvm] [MCA] Avoid repeated hash lookups (NFC) (PR #129192)   Andrea Di Biagio via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_Merge and ICMP (PR #128913)   Brox Chen via llvm-commits
• [lld] 80ea31c - [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (#129050)   via llvm-commits
• [lld] [lld][WebAssembly] Add RUNTIME_PATH support to wasm-ld (PR #129050)   Sam Clegg via llvm-commits
• [llvm] [GSYM] Use debug line offsets during GSYM creation (PR #129196)   Greg Clayton via llvm-commits
• [llvm] [MCA] Avoid repeated hash lookups (NFC) (PR #129192)   Kazu Hirata via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   Artem Belevich via llvm-commits
• [clang] [llvm] [win][x64] Unwind v2 3/n: Add support for emitting unwind v2 information (equivalent to MSVC /d2epilogunwind) (PR #129142)   Eli Friedman via llvm-commits
• [compiler-rt] [asan] Define mallopt and mallinfo for Fuchsia asan runtime (PR #129105)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_Merge and ICMP (PR #128913)   Brox Chen via llvm-commits
• [compiler-rt] fcc571e - [asan] Define mallopt and mallinfo for Fuchsia asan runtime (#129105)   via llvm-commits
• [compiler-rt] [asan] Define mallopt and mallinfo for Fuchsia asan runtime (PR #129105)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_Merge and ICMP (PR #128913)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for ICMP (PR #128913)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for ICMP (PR #128913)   Brox Chen via llvm-commits
• [llvm] [MCA] Avoid repeated hash lookups (NFC) (PR #129192)   Andrea Di Biagio via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Add -sbvec-stop-bndl flag for debugging (PR #129132)   Sriraman Tallam via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_MERGE (PR #129287)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_MERGE (PR #129287)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][GISel] Add 64bit pattern to emit `v_lshl_add_u64` (PR #124763)   Alan Li via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for ICMP (PR #128913)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_MERGE (PR #129287)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_MERGE (PR #129287)   via llvm-commits
• [llvm] c752924 - [SandboxVec][BottomUpVec] Add -sbvec-stop-bndl flag for debugging (#129132)   via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Add -sbvec-stop-bndl flag for debugging (PR #129132)   via llvm-commits
• [llvm] Redundant Assert In AsmWriter (PR #129288)   JP Hafer via llvm-commits
• [llvm] Redundant Assert In AsmWriter (PR #129288)   via llvm-commits
• [llvm] Redundant Assert In AsmWriter (PR #129288)   via llvm-commits
• [llvm] c253e5c - [Exegesis][RISCV] Add initial RVV support (#128767)   via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [AMDGPU] Extend ComputePGMRSrc3 to gfx10+. NFCI. (PR #129289)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Fix vectorization of vector constants (PR #129290)   via llvm-commits
• [llvm] [AMDGPU] Extend ComputePGMRSrc3 to gfx10+. NFCI. (PR #129289)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [AMDGPU] Extend ComputePGMRSrc3 to gfx10+. NFCI. (PR #129289)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Fix vectorization of vector constants (PR #129290)   via llvm-commits
• [llvm] 9869f84 - [SLP][NFC]Add a test with the incorrect analysis for UITOFP for signed operand   Alexey Bataev via llvm-commits
• [llvm] [AMDGPU] Extend ComputePGMRSrc3 to gfx10+. NFCI. (PR #129289)   via llvm-commits
• [llvm] [AMDGPU] Extend ComputePGMRSrc3 to gfx10+. NFCI. (PR #129289)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Fix vectorization of vector constants (PR #129290)   Sriraman Tallam via llvm-commits
• [llvm] [SandboxIR][Region][NFC] Change visibility of Region::add()/remove() (PR #129277)   Jorge Gorbe Moya via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   Sebastian Schaller via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Artem Belevich via llvm-commits
• [llvm] [asan][x86] Abort instrumenting memintrinsics that target fs, gs (PR #129291)   Thor Preimesberger via llvm-commits
• [llvm] a1fdcfa - [AArch64] Protect against scalar types in isNVCastToHalfWidthElements.   David Green via llvm-commits
• [llvm] [SandboxIR][Region][NFC] Change visibility of Region::add()/remove() (PR #129277)   via llvm-commits
• [llvm] [AMDGPU][GISel] Add 64bit pattern to emit `v_lshl_add_u64` (PR #124763)   Alan Li via llvm-commits
• [llvm] [AMDGPU][GISel] Add 64bit pattern to emit `v_lshl_add_u64` (PR #124763)   Alan Li via llvm-commits
• [llvm] [AMDGPU][GISel] Add 64bit pattern to emit `v_lshl_add_u64` (PR #124763)   Alan Li via llvm-commits
• [llvm] e1e20c0 - [SLP]Fix bitwidth analysis for signed nodes, incoming into UITOFP nodes   Alexey Bataev via llvm-commits
• [lld] [LLD][COFF] Mark personality functions as live in both symbol tables on ARM64X (PR #129295)   Jacek Caban via llvm-commits
• [llvm] [SPIR-V] Prevent type change of GEP results in type inference (PR #129250)   Vyacheslav Levytskyy via llvm-commits
• [llvm] 494f672 - [SPIR-V] Prevent type change of GEP results in type inference (#129250)   via llvm-commits
• [lld] [LLD][COFF] Mark personality functions as live in both symbol tables on ARM64X (PR #129295)   via llvm-commits
• [llvm] b8337bc - [llvm-size] Add test for invalid conversion spec on error (#128941)   via llvm-commits
• [llvm] [llvm-size] Add test for invalid conversion spec on error (PR #128941)   Vitaly Buka via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Artem Belevich via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Artem Belevich via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Artem Belevich via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Artem Belevich via llvm-commits
• [llvm] [RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (PR #129296)   Philip Reames via llvm-commits
• [llvm] [RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (PR #129296)   via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Min-Yih Hsu via llvm-commits
• [llvm] [RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (PR #129296)   via llvm-commits
• [llvm] [RISCV] Remove the offset numbers from the FixedCSRFIMap. NFC (PR #129297)   Craig Topper via llvm-commits
• [llvm] [NVPTX] Delete `IsSimpleMove` (NFC) (PR #129178)   Artem Belevich via llvm-commits
• [llvm] [RISCV] Remove the offset numbers from the FixedCSRFIMap. NFC (PR #129297)   via llvm-commits
• [llvm] [RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (PR #129296)   Philip Reames via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Akshay Deodhar via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Akshay Deodhar via llvm-commits
• [llvm] [ci] Add ids workflow for checking llvm apis have been annotated with LLVM_ABI (PR #128370)   via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Akshay Deodhar via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Min-Yih Hsu via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [llvm] Remove unneeded global inits (PR #129299)   JP Hafer via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Min-Yih Hsu via llvm-commits
• [llvm] Remove unneeded global inits (PR #129299)   via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Artem Belevich via llvm-commits
• [clang] [llvm] [RISCV] Remove Last Traces of User Interrupts (PR #129300)   Sam Elliott via llvm-commits
• [clang] [llvm] [RISCV] Remove Last Traces of User Interrupts (PR #129300)   via llvm-commits
• [clang] [llvm] [RISCV] Remove Last Traces of User Interrupts (PR #129300)   via llvm-commits
• [llvm] [libc++] [ci] Update the Windows toolchains to Clang 19 (PR #129232)   Martin Storsjö via llvm-commits
• [llvm] [RISCV] Remove the offset numbers from the FixedCSRFIMap. NFC (PR #129297)   Sam Elliott via llvm-commits
• [llvm] [JSON][NFC] Support `print` and `dump` methods in `json::Value` (PR #129302)   Nikolay Panchenko via llvm-commits
• [llvm] [JSON][NFC] Support `print` and `dump` methods in `json::Value` (PR #129302)   via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [llvm] [libc++] [ci] Update the Windows toolchains to Clang 19 (PR #129232)   via llvm-commits
• [llvm] c13be8f - [NVPTX] Add some basic folds for ADDRSPACECAST (#129157)   via llvm-commits
• [llvm] [NVPTX] Add some basic folds for ADDRSPACECAST (PR #129157)   Alex MacLean via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Alex MacLean via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Alex MacLean via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Alex MacLean via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   LLVM Continuous Integration via llvm-commits
• [llvm] [InferAttrs] Mark floating-point libcalls as errno-writing (PR #124742)   Nikita Popov via llvm-commits
• [llvm] [AggressiveInstCombine] Merge consecutive loads of mixed sizes (PR #129263)   Nikita Popov via llvm-commits
• [llvm] f9b2497 - [VPlan] Use const for VPBasicBlock* in key in VPBB2IRBB (NFC).   Florian Hahn via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [llvm] 88ae5bd - [PAC] Make ValueMapper handle ConstantPtrAuth values (#129088)   via llvm-commits
• [llvm] [PAC] Make ValueMapper handle ConstantPtrAuth values (PR #129088)   Anton Korobeynikov via llvm-commits
• [llvm] [DirectX] Set function-level flag Int64Ops in DXIL Shader Flags Analysis (PR #129089)   S. Bharadwaj Yadavalli via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [compiler-rt] [flang] [llvm] [AArch64] fix trampoline implementation: use X15 (PR #126743)   Eli Friedman via llvm-commits
• [compiler-rt] [flang] [llvm] [AArch64] fix trampoline implementation: use X15 (PR #126743)   Eli Friedman via llvm-commits
• [compiler-rt] [flang] [llvm] [AArch64] fix trampoline implementation: use X15 (PR #126743)   Eli Friedman via llvm-commits
• [compiler-rt] [flang] [llvm] [AArch64] fix trampoline implementation: use X15 (PR #126743)   Eli Friedman via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [llvm] 275baed - [LAA] Consider accessed addrspace when mapping underlying obj to access. (#129087)   via llvm-commits
• [llvm] [LAA] Consider accessed addrspace when mapping underlying obj to access. (PR #129087)   Florian Hahn via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)   Brox Chen via llvm-commits
• [llvm] [DirectX] Set function-level flag Int64Ops in DXIL Shader Flags Analysis (PR #129089)   Deric Cheung via llvm-commits
• [llvm] [DirectX] Set function-level flag Int64Ops in DXIL Shader Flags Analysis (PR #129089)   Deric Cheung via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)   Brox Chen via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)   Brox Chen via llvm-commits
• [llvm] [DirectX] Set module-level flag `LowPrecisionPresent` in DXIL Shader Flags Analysis (PR #129109)   Deric Cheung via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)   Brox Chen via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Brian Cain via llvm-commits
• [llvm] [ci] Add ids workflow for checking llvm apis have been annotated with LLVM_ABI (PR #128370)   via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [llvm] [LV] Optionally preserve uniform branches when vectorizing (PR #128187)   Florian Hahn via llvm-commits
• [llvm] Support: Do not check if a file exists before executing (PR #128821)   David Tenty via llvm-commits
• [llvm] 8c5cd77 - [Exegesis][RISCV] Add missing linked components   Min Hsu via llvm-commits
• [llvm] [SDAG][X86] Remove hack needed to avoid missing x87 FPU stack pops (PR #128055)   Eli Friedman via llvm-commits
• [llvm] [SDAG][X86] Remove hack needed to avoid missing x87 FPU stack pops (PR #128055)   Eli Friedman via llvm-commits
• [llvm] [SDAG][X86] Remove hack needed to avoid missing x87 FPU stack pops (PR #128055)   Eli Friedman via llvm-commits
• [llvm] [LV] Strip redundant casts (NFC) (PR #128177)   Florian Hahn via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [compiler-rt] [RTSan][Apple] Disable AccessingALargeAtomicVariableDiesWhenRealtime (PR #129309)   via llvm-commits
• [compiler-rt] [RTSan][Apple] Disable AccessingALargeAtomicVariableDiesWhenRealtime (PR #129309)   via llvm-commits
• [compiler-rt] [RTSan][Apple] Disable AccessingALargeAtomicVariableDiesWhenRealtime (PR #129309)   via llvm-commits
• [llvm] [ci] Add ids workflow for checking llvm apis have been annotated with LLVM_ABI (PR #128370)   Tom Stellard via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   LLVM Continuous Integration via llvm-commits
• [compiler-rt] [RTSan][Apple] Disable AccessingALargeAtomicVariableDiesWhenRealtime (PR #129309)   via llvm-commits
• [compiler-rt] [RTSan][Apple] Disable AccessingALargeAtomicVariableDiesWhenRealtime (PR #129309)   via llvm-commits
• [llvm] a36a67c - [SLP]Fix the analysis of the user buildvector nodes for minbitwidth   Alexey Bataev via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   LLVM Continuous Integration via llvm-commits
• [llvm] Redundant Assert In AsmWriter (PR #129288)   Nikita Popov via llvm-commits
• [llvm] [CodeGen][StaticDataPartitioning]Place local-linkage global variables in hot or unlikely prefixed sections based on profile information (PR #125756)   Mingming Liu via llvm-commits
• [llvm] [InlineCost] Don't call collectEphemeralValues() if too many assumptions (PR #129279)   Nikita Popov via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [llvm] [Offload][AMDGPU] Enable SPIRV target in build conf (PR #129323)   Jan Patrick Lehr via llvm-commits
• [llvm] [Offload][AMDGPU] Enable SPIRV target in build conf (PR #129323)   via llvm-commits
• [llvm] [Offload][AMDGPU] Enable SPIRV target in build conf (PR #129323)   Jan Patrick Lehr via llvm-commits
• [compiler-rt] [flang] [llvm] [AArch64] fix trampoline implementation: use X15 (PR #126743)   Jameson Nash via llvm-commits
• [llvm] [ci] Add ids workflow for checking llvm apis have been annotated with LLVM_ABI (PR #128370)   via llvm-commits
• [compiler-rt] [RTSan][Apple] Disable AccessingALargeAtomicVariableDiesWhenRealtime (PR #129309)   Chris Apple via llvm-commits
• [llvm] [ci] Add ids workflow for checking llvm apis have been annotated with LLVM_ABI (PR #128370)   Tom Stellard via llvm-commits
• [llvm] [ci] Add ids workflow for checking llvm apis have been annotated with LLVM_ABI (PR #128370)   via llvm-commits
• [llvm] [AMDGPU][True16][CodeGen] gisel true16 for G_MERGE (PR #129287)   Brox Chen via llvm-commits
• [llvm] [Offload][AMDGPU] Enable SPIRV target in build conf (PR #129323)   Joseph Huber via llvm-commits
• [llvm] [InlineCost] Don't call collectEphemeralValues() if too many assumptions (PR #129279)   via llvm-commits
• [compiler-rt] [flang] [llvm] [AArch64] fix trampoline implementation: use X15 (PR #126743)   Jameson Nash via llvm-commits
• [compiler-rt] [flang] [llvm] [AArch64] fix trampoline implementation: use X15 (PR #126743)   Jameson Nash via llvm-commits
• [llvm] [DirectX] Set function-level flag Int64Ops in DXIL Shader Flags Analysis (PR #129089)   S. Bharadwaj Yadavalli via llvm-commits
• [compiler-rt] [RTSan][Apple] Disable AccessingALargeAtomicVariableDiesWhenRealtime (PR #129309)   via llvm-commits
• [llvm] d2cbd5f - [SandboxIR][Region][NFC] Change visibility of Region::add()/remove() (#129277)   via llvm-commits
• [llvm] [SandboxIR][Region][NFC] Change visibility of Region::add()/remove() (PR #129277)   via llvm-commits
• [llvm] [NVPTX] Delete `IsSimpleMove` (NFC) (PR #129178)   Justin Fargnoli via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [llvm] [NVPTX] Delete `IsSimpleMove` (NFC) (PR #129178)   Alex MacLean via llvm-commits
• [llvm] 0065343 - [NVPTX] Improve device function byval parameter lowering (#129188)   via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   Alex MacLean via llvm-commits
• [llvm] [asan][x86] Abort instrumenting memintrinsics that target fs, gs (PR #129291)   Thor Preimesberger via llvm-commits
• [llvm] [asan][x86] Abort instrumenting memintrinsics that target fs, gs (PR #129291)   via llvm-commits
• [llvm] [asan][x86] Abort instrumenting memintrinsics that target fs, gs (PR #129291)   via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] Do not intercept [f]truncate64 for musl (PR #129331)   via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] Do not intercept [f]truncate64 for musl (PR #129331)   via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Sam Clegg via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   LLVM Continuous Integration via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] Do not intercept [f]truncate64 for musl (PR #129331)   David CARLIER via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [llvm] 6ff0f69 - [SandboxVec][BottomUpVec] Fix vectorization of vector constants (#129290)   via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Fix vectorization of vector constants (PR #129290)   via llvm-commits
• [llvm] [SLP]Reduce number of alternate instruction, where possible (PR #128907)   Alexey Bataev via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   LLVM Continuous Integration via llvm-commits
• [llvm] [flang][cuda] Fix descriptor sync in data transfer (PR #129333)   Valentin Clement バレンタイン クレメン via llvm-commits
• [llvm] [flang][cuda] Fix descriptor sync in data transfer (PR #129333)   Zhen Wang via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] [DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) (PR #127749)   Teresa Johnson via llvm-commits
• [llvm] 22965dc - [RISCV] Simplify getStackAdjBase. NFC (#129281)   via llvm-commits
• [llvm] [RISCV] Simplify getStackAdjBase. NFC (PR #129281)   Craig Topper via llvm-commits
• [llvm] [SandboxVec][BottomUpVec] Fix vectorization of vector constants (PR #129290)   LLVM Continuous Integration via llvm-commits
• [llvm] [flang][cuda] Fix descriptor sync in data transfer (PR #129333)   Valentin Clement バレンタイン クレメン via llvm-commits
• [llvm] [Offload][AMDGPU] Enable SPIRV target in build conf (PR #129323)   Alex Voicu via llvm-commits
• [llvm] b697bf3 - [Exegesis][RISCV] Skip some of the tests under expensive checks   Min Hsu via llvm-commits
• [llvm] b2cc28c - [Exegesis][RISCV] Only check if vd and vs2 are alias in rvv/reduction.test   Min Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [SandboxVec][NFC] Add LLVM_DEBUG dumps (PR #129335)   via llvm-commits
• [llvm] [SandboxVec][NFC] Add LLVM_DEBUG dumps (PR #129335)   via llvm-commits
• [llvm] [llvm][CodeGen] Fix the empty interval issue in Window Scheduler(#128714) (PR #129204)   Brian Cain via llvm-commits
• [compiler-rt] 5cf9435 - [compiler-rt][rtsan] Do not intercept [f]truncate64 for musl (#129331)   via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] Do not intercept [f]truncate64 for musl (PR #129331)   via llvm-commits
• [llvm] [CMake] Use shm_open, not clock_gettime, to detect librt (PR #120727)   LLVM Continuous Integration via llvm-commits
• [llvm] Redundant Assert In AsmWriter (PR #129288)   JP Hafer via llvm-commits
• [llvm] Redundant Assert In AsmWriter (PR #129288)   JP Hafer via llvm-commits
• [llvm] 743571b - [RISCV] Remove unused argument. NFC   Craig Topper via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [llvm] [Offload][AMDGPU] Enable SPIRV target in build conf (PR #129323)   Jan Patrick Lehr via llvm-commits
• [llvm] [NVPTX][NVPTXLowerArgs] Add NewPM interface for NVPTXLowerArgs (PR #128960)   Akshay Deodhar via llvm-commits
• [lld] [llvm] [lld][WebAssembly] Support for the custom-page-sizes WebAssembly proposal (PR #128942)   Nick Fitzgerald via llvm-commits
• [llvm] a085da6 - [RISCV] Remove X26 from encodeRlist. NFC   Craig Topper via llvm-commits
• [llvm] [SandboxVec][NFC] Add LLVM_DEBUG dumps (PR #129335)   Sriraman Tallam via llvm-commits
• [llvm] [SandboxVec][NFC] Add LLVM_DEBUG dumps (PR #129335)   Sriraman Tallam via llvm-commits
• [llvm] [SandboxVec][NFC] Add LLVM_DEBUG dumps (PR #129335)   via llvm-commits
• [compiler-rt] [RTSan][Apple] Disable AccessingALargeAtomicVariableDiesWhenRealtime (PR #129309)   Chris Apple via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   LLVM Continuous Integration via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] 45d0180 - [SandboxVec][NFC] Add LLVM_DEBUG dumps (#129335)   via llvm-commits
• [llvm] [SandboxVec][NFC] Add LLVM_DEBUG dumps (PR #129335)   via llvm-commits
• [llvm] 23c41bf - [Exegesis][RISCV] Allow rvv/filter.test to retry   Min Hsu via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Min-Yih Hsu via llvm-commits
• [llvm] [SandboxVec][NFC] Add LLVM_DEBUG dumps (PR #129335)   LLVM Continuous Integration via llvm-commits
• [llvm] [SandboxVec][NFC] Add LLVM_DEBUG dumps (PR #129335)   LLVM Continuous Integration via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   LLVM Continuous Integration via llvm-commits
• [llvm] [windows] Always pass fp128 arguments indirectly (PR #128848)   Reid Kleckner via llvm-commits
• [llvm] [RISCV] Simplify tracking of tracking and encoding of push/pop in RISCVFrameLowering. NFC (PR #129343)   Craig Topper via llvm-commits
• [llvm] [RISCV] Simplify tracking of tracking and encoding of push/pop in RISCVFrameLowering. NFC (PR #129343)   via llvm-commits
• [llvm] [windows] Always pass fp128 arguments indirectly (PR #128848)   Trevor Gross via llvm-commits
• [llvm] 1f27ff9 - [NVPTX] Delete `IsSimpleMove` (NFC) (#129178)   via llvm-commits
• [llvm] [NVPTX] Delete `IsSimpleMove` (NFC) (PR #129178)   Justin Fargnoli via llvm-commits
• [llvm] 32dffdc - [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (#128978)   via llvm-commits
• [llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)   Min-Yih Hsu via llvm-commits
• [llvm] [NVPTX] (PR #129344)   Justin Fargnoli via llvm-commits
• [llvm] [NVPTX] (PR #129344)   Justin Fargnoli via llvm-commits
• [llvm] [NVPTX] cleanup & canonicalize `mov` (PR #129344)   Justin Fargnoli via llvm-commits
• [llvm] [NVPTX] cleanup & canonicalize `mov` (PR #129344)   Justin Fargnoli via llvm-commits
• [llvm] [NVPTX] cleanup & canonicalize `mov` (PR #129344)   Justin Fargnoli via llvm-commits
• [llvm] [NVPTX] cleanup & canonicalize `mov` (PR #129344)   via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   LLVM Continuous Integration via llvm-commits
• [llvm] [NVPTX] cleanup & canonicalize `mov` (PR #129344)   Artem Belevich via llvm-commits
• [llvm] Remove unneeded global inits (PR #129299)   via llvm-commits
• [llvm] 7cf2f60 - [Vectorize] Fix unused variable warnings (NFC)   Jie Fu via llvm-commits
• [lld] [lld][Wasm] Do not emit relocs against dead symbols (PR #129346)   Derek Schuff via llvm-commits
• [lld] [lld][Wasm] Do not emit relocs against dead symbols (PR #129346)   via llvm-commits
• [lld] [lld][Wasm] Do not emit relocs against dead symbols (PR #129346)   via llvm-commits
• [lld] [lld][Wasm] Do not emit relocs against dead symbols (PR #129346)   via llvm-commits
• [lld] [lld][Wasm] Do not emit relocs against dead symbols (PR #129346)   Derek Schuff via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   Nico Weber via llvm-commits
• [llvm] [BOLT] Refactor MCInst target symbol lookup. NFCI (PR #129131)   Maksim Panchenko via llvm-commits
• [llvm] [BOLT] Add symbolizer for AArch64 disassembler. NFCI (PR #127969)   Maksim Panchenko via llvm-commits
• [llvm] 4ab9c13 - [gn] port c253e5c9917b (RISCV llvm-exegesis)   Nico Weber via llvm-commits
• [lld] [lld][Wasm] Do not emit relocs against dead symbols (PR #129346)   Derek Schuff via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] 0a0775e - [gn] port 32dffdce0511 (more RISCV depedency things)   Nico Weber via llvm-commits
• [llvm] 9421e17 - [gn build] Port 006534315972   LLVM GN Syncbot via llvm-commits
• [llvm] [X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (PR #128910)   Phoebe Wang via llvm-commits
• [llvm] Support: Do not check if a file exists before executing (PR #128821)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Sort an instruction definition by opcode (PR #129350)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Sort an instruction definition by opcode (PR #129350)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Sort an instruction definition by opcode (PR #129350)   Matt Arsenault via llvm-commits
• [llvm] AMDGPU: Sort an instruction definition by opcode (PR #129350)   via llvm-commits
• [llvm] [LangRef] Correct documentation for `roundeven` (PR #125452)   Trevor Gross via llvm-commits
• [llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)   LLVM Continuous Integration via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   João Gouveia via llvm-commits
• [llvm] [LangRef] Correct documentation for `roundeven` (PR #125452)   Matt Arsenault via llvm-commits
• [llvm] 84b365c - [LangRef] Correct documentation for `roundeven` (#125452)   via llvm-commits
• [llvm] [LangRef] Correct documentation for `roundeven` (PR #125452)   Matt Arsenault via llvm-commits
• [llvm] [LangRef] Correct documentation for `roundeven` (PR #125452)   via llvm-commits
• [llvm] AMDGPU: Sort an instruction definition by opcode (PR #129350)   Shilei Tian via llvm-commits
• [llvm] [LangRef] Correct documentation for `roundeven` (PR #125452)   Trevor Gross via llvm-commits
• [llvm] [SDAG][X86] Remove hack needed to avoid missing x87 FPU stack pops (PR #128055)   Phoebe Wang via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   LLVM Continuous Integration via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   via llvm-commits
• [llvm] workflows/release-binaries: Run tests on same machine as build (PR #129353)   Tom Stellard via llvm-commits
• [llvm] [SimplifyLibCalls][NFC] Fix Typo in Header Comment (PR #114314)   via llvm-commits
• [llvm] dfca4f9 - [SimplifyLibCalls][NFC] Fix Typo in Header Comment (#114314)   via llvm-commits
• [llvm] [SimplifyLibCalls][NFC] Fix Typo in Header Comment (PR #114314)   via llvm-commits
• [llvm] [SimplifyLibCalls][NFC] Fix Typo in Header Comment (PR #114314)   via llvm-commits
• [llvm] 810150b - [RISCV] Remove the offset numbers from the FixedCSRFIMap. NFC (#129297)   via llvm-commits
• [llvm] [RISCV] Remove the offset numbers from the FixedCSRFIMap. NFC (PR #129297)   Craig Topper via llvm-commits
• [llvm] ef1128b - AMDGPU: Sort an instruction definition by opcode (#129350)   via llvm-commits
• [llvm] AMDGPU: Sort an instruction definition by opcode (PR #129350)   Matt Arsenault via llvm-commits
• [llvm] [ADT] Avoid repeated hash lookups (NFC) (PR #129355)   Kazu Hirata via llvm-commits
• [llvm] [ExecutionEngine] Avoid repeated hash lookups (NFC) (PR #129356)   Kazu Hirata via llvm-commits
• [llvm] [ADT] Avoid repeated hash lookups (NFC) (PR #129355)   via llvm-commits
• [llvm] [Hexagon] Avoid repeated hash lookups (NFC) (PR #129357)   Kazu Hirata via llvm-commits
• [llvm] [SPIRV] Avoid repeated hash lookups (NFC) (PR #129358)   Kazu Hirata via llvm-commits
• [llvm] [Hexagon] Avoid repeated hash lookups (NFC) (PR #129357)   via llvm-commits
• [llvm] [Transforms] Avoid repeated hash lookups (NFC) (PR #129359)   Kazu Hirata via llvm-commits
• [llvm] [SPIRV] Avoid repeated hash lookups (NFC) (PR #129358)   via llvm-commits
• [llvm] [X86] Avoid repeated hash lookups (NFC) (PR #129360)   Kazu Hirata via llvm-commits
• [llvm] [Transforms] Avoid repeated hash lookups (NFC) (PR #129359)   via llvm-commits
• [llvm] [X86] Avoid repeated hash lookups (NFC) (PR #129360)   via llvm-commits
• [libc] [llvm] Add sysexits.h header with BSD exit codes (total-18) (PR #126112)   Ajay Raj via llvm-commits
• [llvm] [NVPTX] cleanup & canonicalize `mov` (PR #129344)   Justin Fargnoli via llvm-commits
• [llvm] [ADT] Avoid repeated hash lookups (NFC) (PR #129355)   Jakub Kuderski via llvm-commits
• [llvm] 8d1f385 - [ADT] Avoid repeated hash lookups (NFC) (#129355)   via llvm-commits
• [llvm] [ADT] Avoid repeated hash lookups (NFC) (PR #129355)   Kazu Hirata via llvm-commits
• [llvm] [SPIRV] Stop using Register to represent target specific virtual registers. (PR #129362)   Craig Topper via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] [SPIRV] Stop using Register to represent target specific virtual registers. (PR #129362)   via llvm-commits
• [llvm] [NVPTX] Add Intrinsics for discard.* (PR #128404)   Abhilash Majumder via llvm-commits
• [llvm] 83d2c68 - Prune a redundant include "RISCVISelDAGToDAG.h" (fixup for #128978)   NAKAMURA Takumi via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   LLVM Continuous Integration via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++][ranges] P2542R8: Implement `views::concat` (PR #120920)   Nhat Nguyen via llvm-commits
• [clang] [llvm] [win][x64] Unwind v2 3/n: Add support for emitting unwind v2 information (equivalent to MSVC /d2epilogunwind) (PR #129142)   Pedro Miguel Justo via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++][ranges] P2542R8: Implement `views::concat` (PR #120920)   Nhat Nguyen via llvm-commits
• [llvm] [InstCombine] recognize missed i128 split optimization (PR #129363)   Muhammad Bassiouni via llvm-commits
• [llvm] [InstCombine] recognize missed i128 split optimization (PR #129363)   via llvm-commits
• [llvm] [InstCombine] recognize missed i128 split optimization (PR #129363)   via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++][ranges] P2542R8: Implement `views::concat` (PR #120920)   Nhat Nguyen via llvm-commits
• [clang] [llvm] [win][x64] Unwind v2 3/n: Add support for emitting unwind v2 information (equivalent to MSVC /d2epilogunwind) (PR #129142)   Eli Friedman via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++][ranges] P2542R8: Implement `views::concat` (PR #120920)   Nhat Nguyen via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++] constexpr deque (PR #129367)   Nhat Nguyen via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++] constexpr deque (PR #129367)   Nhat Nguyen via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++] constexpr deque (PR #129367)   via llvm-commits
• [clang] [llvm] [win][x64] Unwind v2 3/n: Add support for emitting unwind v2 information (equivalent to MSVC /d2epilogunwind) (PR #129142)   Pedro Miguel Justo via llvm-commits
• [llvm] [AggressiveInstCombine] Merge consecutive loads of mixed sizes (PR #129263)   Zhenyang Xu via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [lld] [AArch64][GCS][LLD] Introduce -zgcs-report-dynamic Command Line Option (PR #127787)   Fangrui Song via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [lld] 7e8a06c - [ELF] Make -z *-report=unknown error message conventional   Fangrui Song via llvm-commits
• [clang] [llvm] [libclang/python] Enable packaging libclang bindings (PR #125806)   Jannick Kremer via llvm-commits
• [llvm] [X86] Avoid repeated hash lookups (NFC) (PR #129360)   via llvm-commits
• [llvm] [memprof] Use llvm::equal in stackFrameIncludesInlinedCallStack (NFC) (PR #129372)   Kazu Hirata via llvm-commits
• [llvm] [memprof] Use llvm::equal in stackFrameIncludesInlinedCallStack (NFC) (PR #129372)   via llvm-commits
• [clang] [llvm] [MC/DC] Nested decision (PR #125403)   NAKAMURA Takumi via llvm-commits
• [llvm] [SPIRV] Stop using Register to represent target specific virtual registers. (PR #129362)   Matt Arsenault via llvm-commits
• [compiler-rt] [RTSan][Apple] Disable AccessingALargeAtomicVariableDiesWhenRealtime (PR #129309)   Chris Apple via llvm-commits
• [clang] [llvm] [MC/DC] Nested decision (PR #125403)   NAKAMURA Takumi via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   Chris Apple via llvm-commits
• [clang] [llvm] [libclang/python] Enable packaging libclang bindings (PR #125806)   Cristian Le via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   Yingwei Zheng via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   Yingwei Zheng via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   Yingwei Zheng via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   Yingwei Zheng via llvm-commits
• [clang] [llvm] [libclang/python] Enable packaging libclang bindings (PR #125806)   Cristian Le via llvm-commits
• [llvm] [Hexagon] Avoid repeated hash lookups (NFC) (PR #129357)   Nikita Popov via llvm-commits
• [llvm] [SPIRV] Avoid repeated hash lookups (NFC) (PR #129358)   Nikita Popov via llvm-commits
• [llvm] [Transforms] Avoid repeated hash lookups (NFC) (PR #129359)   Nikita Popov via llvm-commits
• [llvm] [SDAG][X86] Remove hack needed to avoid missing x87 FPU stack pops (PR #128055)   Benjamin Maxwell via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   David CARLIER via llvm-commits
• [llvm] [AggressiveInstCombine] Merge consecutive loads of mixed sizes (PR #129263)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] recognize missed i128 split optimization (PR #129363)   Yingwei Zheng via llvm-commits
• [llvm] [AggressiveInstCombine] Merge consecutive loads of mixed sizes (PR #129263)   Yingwei Zheng via llvm-commits
• [llvm] [AggressiveInstCombine] Merge consecutive loads of mixed sizes (PR #129263)   Zhenyang Xu via llvm-commits
• [llvm] [InstCombine] recognize missed i128 split optimization (PR #129363)   Simon Pilgrim via llvm-commits
• [llvm] 8f4d2e0 - [VectorCombine] scalarizeLoadExtract - add debug message for match + cost-comparison   Simon Pilgrim via llvm-commits
• [llvm] [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (PR #129375)   Simon Pilgrim via llvm-commits
• [llvm] [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (PR #129375)   via llvm-commits
• [llvm] [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (PR #129375)   via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] 0751418 - [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (#128435)   via llvm-commits
• [llvm] [X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (PR #128435)   Phoebe Wang via llvm-commits
• [llvm] [SDAG][X86] Remove hack needed to avoid missing x87 FPU stack pops (PR #128055)   Phoebe Wang via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   Nikita Popov via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   David CARLIER via llvm-commits
• [compiler-rt] [compiler-rt][rtsan] copy_file_range interception for Linux. (PR #129026)   David CARLIER via llvm-commits
• [llvm] [SDAG][X86] Remove hack needed to avoid missing x87 FPU stack pops (PR #128055)   Benjamin Maxwell via llvm-commits
• [llvm] [AMDGPU] Extend ComputePGMRSrc3 to gfx10+. NFCI. (PR #129289)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [AMDGPU] Allow lane-op lowering for some illegal types (PR #114887)   Stanislav Mekhanoshin via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   Yingwei Zheng via llvm-commits
• [llvm] [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (PR #129375)   Yingwei Zheng via llvm-commits
• [llvm] [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (PR #129375)   Yingwei Zheng via llvm-commits
• [llvm] [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (PR #129375)   Yingwei Zheng via llvm-commits
• [llvm] [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (PR #129375)   Yingwei Zheng via llvm-commits
• [llvm] [InstCombine] Simplify nonnull phi nodes (PR #128466)   Nikita Popov via llvm-commits
• [llvm] [ValueTracking] Refactor `isKnownNonEqualFromContext` (PR #127388)   Nikita Popov via llvm-commits
• [llvm] [DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (PR #129272)   Simon Pilgrim via llvm-commits
• [llvm] [SimplifyCFG] Switch to use `paramHasNonNullAttr` (PR #125383)   Nikita Popov via llvm-commits
• [llvm] [BOLT] fix THP check in bolt --hugify (PR #129380)   Eric Wang via llvm-commits
• [llvm] [BOLT] fix THP check in bolt --hugify (PR #129380)   via llvm-commits
• [llvm] 2709366 - [DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (#129272)   via llvm-commits
• [llvm] [DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (PR #129272)   Yingwei Zheng via llvm-commits
• [llvm] [DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (PR #129272)   Yingwei Zheng via llvm-commits
• [llvm] [DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (PR #129272)   Yingwei Zheng via llvm-commits
• [llvm] [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (PR #129375)   Simon Pilgrim via llvm-commits
• [llvm] [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (PR #129375)   Simon Pilgrim via llvm-commits
• [llvm] [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (PR #129375)   Simon Pilgrim via llvm-commits
• [llvm] [BOLT] fix THP check in bolt --hugify (PR #129380)   via llvm-commits
• [llvm] [DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (PR #129272)   via llvm-commits
• [clang] [llvm] [libclang/python] Enable packaging libclang bindings (PR #125806)   Vlad Serebrennikov via llvm-commits
• [llvm] [DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (PR #129272)   LLVM Continuous Integration via llvm-commits
• [llvm] 9f37cdc - [VPlan] Update VPTransformState accessors to take const VPValue (NFC).   Florian Hahn via llvm-commits
• [llvm] [NVPTX] Improve device function byval parameter lowering (PR #129188)   LLVM Continuous Integration via llvm-commits
• [llvm] [SimplifyCFG] Switch to use `paramHasNonNullAttr` (PR #125383)   Yingwei Zheng via llvm-commits
• [llvm] [memprof] Use llvm::equal in stackFrameIncludesInlinedCallStack (NFC) (PR #129372)   Teresa Johnson via llvm-commits
• [llvm] 37374fb - [InstCombine] Simplify nonnull phi nodes (#128466)   via llvm-commits
• [llvm] [InstCombine] Simplify nonnull phi nodes (PR #128466)   Yingwei Zheng via llvm-commits
• [llvm] [VPlan] Add new VPIRPhi overlay for VPIRInsts wrapping phi nodes (NFC). (PR #129387)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add new VPIRPhi overlay for VPIRInsts wrapping phi nodes (NFC). (PR #129387)   via llvm-commits
• [llvm] [VPlan] Add new VPIRPhi overlay for VPIRInsts wrapping phi nodes (NFC). (PR #129387)   via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   David Green via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   David Green via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   David Green via llvm-commits
• [llvm] [AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (PR #123552)   David Green via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   David Green via llvm-commits
• [llvm] cc5d8a4 - [AArch64] fall back to SDAG for instructions with emulated TLS variables (#129215)   via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   David Green via llvm-commits
• [llvm] [AArch64] fall back to SDAG for instructions with emulated TLS variables (PR #129215)   via llvm-commits
• [llvm] [VPlan] Add VPPhiAccessors to provide interface for phi recipes (NFC) (PR #129388)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Add VPPhiAccessors to provide interface for phi recipes (NFC) (PR #129388)   via llvm-commits
• [llvm] [ExecutionEngine] Avoid repeated hash lookups (NFC) (PR #129356)   Kazu Hirata via llvm-commits
• [llvm] [VPlan] Use VPPhiAccessors for VPIRPhi. (PR #129389)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Use VPPhiAccessors for VPIRPhi. (PR #129389)   via llvm-commits
• [llvm] [VPlan] Use VPPhiAccessors for VPIRPhi. (PR #129389)   via llvm-commits
• [llvm] [ExecutionEngine] Avoid repeated hash lookups (NFC) (PR #129356)   Nikita Popov via llvm-commits
• [llvm] 00414c3 - [Hexagon] Avoid repeated hash lookups (NFC) (#129357)   via llvm-commits
• [llvm] [Hexagon] Avoid repeated hash lookups (NFC) (PR #129357)   Kazu Hirata via llvm-commits
• [llvm] 0bcc37c - [SPIRV] Avoid repeated hash lookups (NFC) (#129358)   via llvm-commits
• [llvm] [SPIRV] Avoid repeated hash lookups (NFC) (PR #129358)   Kazu Hirata via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] f892dc7 - [Transforms] Avoid repeated hash lookups (NFC) (#129359)   via llvm-commits
• [llvm] [Transforms] Avoid repeated hash lookups (NFC) (PR #129359)   Kazu Hirata via llvm-commits
• [llvm] 70af83f - [X86] Avoid repeated hash lookups (NFC) (#129360)   via llvm-commits
• [llvm] [X86] Avoid repeated hash lookups (NFC) (PR #129360)   Kazu Hirata via llvm-commits
• [llvm] 70f4e6a - [ExecutionEngine] Avoid repeated hash lookups (NFC) (#129356)   via llvm-commits
• [llvm] [ExecutionEngine] Avoid repeated hash lookups (NFC) (PR #129356)   Kazu Hirata via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] 8846013 - [memprof] Use llvm::equal in stackFrameIncludesInlinedCallStack (NFC) (#129372)   via llvm-commits
• [llvm] [memprof] Use llvm::equal in stackFrameIncludesInlinedCallStack (NFC) (PR #129372)   Kazu Hirata via llvm-commits
• [llvm] [VPlan] Use VPPhiAccessors for VPIRPhi. (PR #129389)   via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Verify dominance for incoming values of phi-like recipes. (PR #124838)   via llvm-commits
• [llvm] [InstCombine] Support trunc to i1 in foldSelectICmpAnd (PR #127905)   Andreas Jonson via llvm-commits
• [llvm] 5ddf40f - [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (#129375)   via llvm-commits
• [llvm] [VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (PR #129375)   Simon Pilgrim via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] bc35510 - [InstSimplify] Fold `X * C >= X` to `true` (#129352)   via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   via llvm-commits
• [llvm] [InstSimplify] Fold `X * C >= X` to `true` (PR #129352)   LLVM Continuous Integration via llvm-commits
• [llvm] [RISCV] Emitting proper atomic ABI tag when Zalasr is enabled (PR #121017)   Philip Reames via llvm-commits
• [llvm] [RISCV] Emitting proper atomic ABI tag when Zalasr is enabled (PR #121017)   Philip Reames via llvm-commits
• [lld] [lld][Wasm] Do not emit relocs against dead symbols (PR #129346)   Sam Clegg via llvm-commits
• [lld] [lld][Wasm] Do not emit relocs against dead symbols (PR #129346)   Sam Clegg via llvm-commits
• [lld] [lld][WebAssembly] Do not emit relocs against dead symbols (PR #129346)   Sam Clegg via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [llvm] b356a30 - [Mips] Format some MCTargetDesc files. NFC   Fangrui Song via llvm-commits
• [lldb] [llvm] [lldb-dap] Add: show return value on step out (PR #106907)   Adrian Vogelsgesang via llvm-commits
• [llvm] [Mips] Allow expressions in some immediate operands (PR #127581)   Fangrui Song via llvm-commits
• [lldb] [llvm] [lldb-dap] Add: show return value on step out (PR #106907)   Adrian Vogelsgesang via llvm-commits
• [llvm] b65e094 - [Mips] Allow expressions in some immediate operands   via llvm-commits
• [llvm] [Mips] Allow expressions in some immediate operands (PR #127581)   Fangrui Song via llvm-commits
• [llvm] llvm-rc: Relax error message checked in test (PR #129243)   Fangrui Song via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [clang] [llvm] [HLSL][RootSignature] Implement Parsing of Descriptor Tables (PR #122982)   Chris B via llvm-commits
• [clang] [llvm] [HLSL][RootSignature] Implement Parsing of Descriptor Tables (PR #122982)   Chris B via llvm-commits
• [llvm] [PartiallyInlineLibCalls] Emit missed- and passed-optimization remarks when partially inlining sqrt (PR #123966)   via llvm-commits
• [clang] [llvm] [WIP] Correct lowering of `fp128` intrinsics (PR #76558)   Trevor Gross via llvm-commits
• [llvm] [LiveRegUnits] Enhanced the register liveness check (PR #66061)   Jonathan Thackray via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [llvm] [llvm-objcopy] Let --change-section-lma change segments wth filesz=0,… (PR #127724)   Fangrui Song via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Csanád Hajdú via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [lld] 9b7b7d6 - [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (#128883)   via llvm-commits
• [lld] [LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (PR #128883)   Fangrui Song via llvm-commits
• [llvm] [BOLT][AArch64] Refactor ADR to ADRP+ADD conversion pass. NFCI (PR #129399)   Maksim Panchenko via llvm-commits
• [llvm] [BOLT][AArch64] Refactor ADR to ADRP+ADD conversion pass. NFCI (PR #129399)   via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++][ranges] P2542R8: Implement `views::concat` (PR #120920)   Nhat Nguyen via llvm-commits
• [llvm] [RISCV] Emitting proper atomic ABI tag when Zalasr is enabled (PR #121017)   Craig Topper via llvm-commits
• [llvm] [Offload][AMDGPU] Enable SPIRV target in build conf (PR #129323)   Jan Patrick Lehr via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++][ranges] P2542R8: Implement `views::concat` (PR #120920)   Nhat Nguyen via llvm-commits
• [lld] [LLD][COFF] Mark personality functions as live in both symbol tables on ARM64X (PR #129295)   Martin Storsjö via llvm-commits
• [lld] [LLD][COFF] Add support for autoimports on ARM64X (PR #129282)   Martin Storsjö via llvm-commits
• [lld] [LLD][COFF] Add support for autoimports on ARM64X (PR #129282)   Martin Storsjö via llvm-commits
• [lld] [LLD][COFF] Add support for autoimports on ARM64X (PR #129282)   Martin Storsjö via llvm-commits
• [lld] [LLD][COFF] Add support for autoimports on ARM64X (PR #129282)   Martin Storsjö via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [clang] [clang-tools-extra] [libcxx] [llvm] [libc++][ranges] P2542R8: Implement `views::concat` (PR #120920)   Nhat Nguyen via llvm-commits
• [llvm] [NVPTX] cleanup & canonicalize `mov` (PR #129344)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] cleanup & canonicalize `mov` (PR #129344)   Alex MacLean via llvm-commits
• [llvm] [NVPTX] cleanup & canonicalize `mov` (PR #129344)   Alex MacLean via llvm-commits
• [llvm] 75270e3 - [VPlan] Don't print VPlan DT after VPlan construction. (NFC)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Refactor VPlan creation, add transform introducing region (NFC). (PR #128419)   Florian Hahn via llvm-commits
• [llvm] 872e4a3 - [X86] Replace reloc_global_offset_table8 with R_X86_64_GOTPC64   Fangrui Song via llvm-commits
• [llvm] [VPlan] Introduce child regions as VPlan transform. (PR #129402)   Florian Hahn via llvm-commits
• [llvm] [VPlan] Introduce child regions as VPlan transform. (PR #129402)   via llvm-commits
• [lld] [LLD][COFF] Add support for autoimports on ARM64X (PR #129282)   Jacek Caban via llvm-commits
• [lld] [LLD][COFF] Add support for autoimports on ARM64X (PR #129282)   Jacek Caban via llvm-commits
• [lld] [LLD][COFF] Correct relocation size comments in autoimport tests (NFC) (PR #129403)   Jacek Caban via llvm-commits
• [lld] [LLD][COFF] Correct relocation size comments in autoimport tests (NFC) (PR #129403)   via llvm-commits
• [llvm] [BOLT][AArch64] Refactor ADR to ADRP+ADD conversion pass. NFCI (PR #129399)   Davide Italiano via llvm-commits
• [llvm] [BOLT][AArch64] Refactor ADR to ADRP+ADD conversion pass. NFCI (PR #129399)   Maksim Panchenko via llvm-commits
• [llvm] [BOLT] Refactor interface for creating instruction patches. NFCI (PR #129404)   Maksim Panchenko via llvm-commits
• [llvm] [BOLT] Refactor interface for creating instruction patches. NFCI (PR #129404)   via llvm-commits
• [llvm] [BOLT] Refactor interface for creating instruction patches. NFCI (PR #129404)   via llvm-commits
• [lld] [LLD][COFF] Correct relocation size comments in autoimport tests (NFC) (PR #129403)   Martin Storsjö via llvm-commits
• [lldb] [llvm] [lldb-dap] Add: show return value on step out (PR #106907)   via llvm-commits
• [llvm] [InstCombine] recognize missed i128 split optimization (PR #129363)   Muhammad Bassiouni via llvm-commits
• [llvm] [InstCombine] recognize missed i128 split optimization (PR #129363)   Muhammad Bassiouni via llvm-commits
• [llvm] e3e9c5c - [MC] Remove unneeded onLabelParsed and onLabelParsed from HLASM   Fangrui Song via llvm-commits
• [lldb] [llvm] [lldb-dap] Add: show return value on step out (PR #106907)   via llvm-commits
• [llvm] 5e6c085 - [MCParser] Clean up onEndOfFile   Fangrui Song via llvm-commits
• [llvm] 8ec0d60 - [lldb-dap] Add: show return value on step out (#106907)   via llvm-commits
• [llvm] 077497d - [MCParser] Remove parseParenExprOfDepth   Fangrui Song via llvm-commits
• [llvm] 43c3014 - [llvm-ml] Remove unused parser functions   Fangrui Song via llvm-commits
• [llvm] b6d5fa0 - [llvm-ml] Remove unused DWARF/Mach-O/ARM If-Then functions   Fangrui Song via llvm-commits
• [llvm] 8394157 - llvm-rc: Relax error message checked in test (#129243)   via llvm-commits
• [llvm] a0540e6 - unittests: Use EXPECT_ instead of ASSERT_ in a few tests (#129251)   via llvm-commits
• [llvm] 1b1dc50 - [MCParser] Improve parseIntToken error message   Fangrui Song via llvm-commits
• [llvm] 99ff3d0 - [MCParser] Remove some section directive not supported by gas   Fangrui Song via llvm-commits
• [llvm] 81a8b5c - [MachineSink] Use Register and MCRegUnit. NFC   Craig Topper via llvm-commits
• [llvm] 69c7336 - [Analysis] Avoid repeated hash lookups (NFC) (#129417)   via llvm-commits
• [llvm] 2bbb394 - [CodeGen] Avoid repeated hash lookups (NFC) (#129418)   via llvm-commits
• [llvm] c1211d5 - [IPO] Avoid repeated hash lookups (NFC) (#129419)   via llvm-commits
• [llvm] 4eef3de - [Mips] Avoid repeated hash lookups (NFC) (#129420)   via llvm-commits
• [llvm] 1fd014c - [SPIRV] Avoid repeated hash lookups (NFC) (#129421)   via llvm-commits
• [llvm] 4b3f0fa - [llvm-jitlink] Avoid repeated hash lookups (NFC) (#129422)   via llvm-commits
• [llvm] f937b17 - [LV] Don't query SCEV for non-invariant values in cost model.   Florian Hahn via llvm-commits
• [llvm] 416c7b3 - [ARM] Remove unneeded global inits (NFCI) (#129299)   via llvm-commits
• [llvm] ba7e273 - [VPlan] Use VP_CLASSOF_IMPL in VPWidenRecipe. (NFC)   Florian Hahn via llvm-commits
• [lld] f858ac7 - [LLD][COFF] Correct relocation size comments in autoimport tests (NFC) (#129403)   via llvm-commits
• [lld] c6598f6 - [LLD][COFF] Add support for autoimports on ARM64X (#129282)   via llvm-commits
• [llvm] 8eba022 - [CodeGen][ARM64EC] Mangle EH personality handler names (#121652)   via llvm-commits
• [lld] d403f33 - [LLD][COFF] Mark personality functions as live in both symbol tables on ARM64X (#129295)   via llvm-commits
• [llvm] 6d847b1 - [FastISel] Use Register. NFC   Craig Topper via llvm-commits
• [llvm] 18e09da - [Mips] Rework relocation expression parsing   Fangrui Song via llvm-commits
• [llvm] a9f02a4 - [CFIInstrInserter] Don't store Dwarf register number in Register. NFC   Craig Topper via llvm-commits
• [llvm] 20362c5 - [TwoAddressInstructionPass] Use Register. NFC   Craig Topper via llvm-commits
• [llvm] 2fb7f09 - [FastISel] Use Register. NFC   Craig Topper via llvm-commits
• [llvm] 1d9207f - [TailDuplicator] Use Register. NFC   Craig Topper via llvm-commits
• [llvm] fd3326b - [AggressiveAntiDepBreaker] Use MCRegister. NFC   Craig Topper via llvm-commits
• [llvm] dcca3f4 - Revert "[AggressiveAntiDepBreaker] Use MCRegister. NFC"   Craig Topper via llvm-commits
• [llvm] 31bf16a - [MC] Add MCTargetStreamer::getContext to simplify code   Fangrui Song via llvm-commits
• [llvm] 6048629 - [MC] Move MIPS-specific gprel/tprel/dtprel from MCStreamer to MipsTargetStreamer   Fangrui Song via llvm-commits
• [llvm] f745cb6 - [AggressiveAntiDepBreaker] Use MCRegister. NFC   Craig Topper via llvm-commits
• [llvm] 0c5d709 - Move MIPS-specific GPRel32Directive and EK_GPRel32BlockAddress from generic code to Mips/   Fangrui Song via llvm-commits
• [llvm] b02cfbd - [llvm-ml] Remove unused VariantKind parsing code   Fangrui Song via llvm-commits
• [llvm] 3c80d9b - [Instruction] Set metadata to `poison` on deletion (#129449)   via llvm-commits
• [llvm] 8c7c791 - [MCParser] Use getVariantKindForName and move PPC specific VariantKind to PowerPC/   Fangrui Song via llvm-commits
• [llvm] 14951a5 - [MCParser] Extract some VariantKind from getVariantKindForName   Fangrui Song via llvm-commits
• [llvm] cb7030d - [LoongArch] use TypeWidenVector for most illegal vector types (#126456)   via llvm-commits
• [llvm] e42ab4c - [RISCV] Handle zvbb instructions in getVectorLowDemandedScalarBits. (#129011)   via llvm-commits
• [llvm] cf00ac8 - [Hexagon] Call MCExpr::print with valid MAI   Fangrui Song via llvm-commits
• [llvm] 98a640a - [MC] Move VariantKind info to MCAsmInfo   Fangrui Song via llvm-commits
• [llvm] c804e86 - [RISCV][VLS] Support RISCV VLS calling convention (#100346)   via llvm-commits
• [llvm] f244b8e - [MC] Port initializeVariantKinds to a few targets   Fangrui Song via llvm-commits
• [llvm] aa1fe57 - [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (#120557)   via llvm-commits
• [llvm] e118670 - [test] Replace tlsldo with TLSLDO to be consistent with most TLS*   Fangrui Song via llvm-commits
• [llvm] 69c8312 - [CodeGen][NewPM] Port MachineCycleInfo to NPM (#114745)   via llvm-commits
• [llvm] 04b49b1 - [MCExpr] Remove generic getVariantKindName and getVariantKindForName   Fangrui Song via llvm-commits
• [llvm] 0301580 - [PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD   Fangrui Song via llvm-commits
• [llvm] 7bd2be4 - [SelectionDAG] Use Register and MCRegister. NFC   Craig Topper via llvm-commits
• [llvm] e56215d - [RegAllocFast] Use Register and MCRegister. NFC   Craig Topper via llvm-commits
• [llvm] 13cce8c - [CodeGen] Use Register::id() to avoid implicit cast. NFC   Craig Topper via llvm-commits
• [llvm] a70175a - [CodeGen] Use MCRegister and Register. NFC   Craig Topper via llvm-commits
• [llvm] dd9bb32 - [MachineCSE] Const correct some function arguments. NFC   Craig Topper via llvm-commits
• [llvm] aaaaa4d - [MachineLICM] Use Register. NFC   Craig Topper via llvm-commits
• [llvm] 1b043c2 - [RISCV] Simplify RISCVMCExpr::evaluateAsConstant   Fangrui Song via llvm-commits
• [llvm] 71f4c7d - [NFC]Make file-local cl::opt global variables static (#126486)   via llvm-commits
• [llvm] 59138a6 - [DAGCombiner] Cleanup MatchFunnelPosNeg by using SDPatternMatch matchers (#129482)   via llvm-commits
• [llvm] 8a9a363 - [MIRCanonicalizerPass] Use MCRegister. NFC   Craig Topper via llvm-commits
• [llvm] 49ba565 - [IfConversion] Use MCRegister. NFC   Craig Topper via llvm-commits
• [llvm] 3fe2255 - [InlineSpiller] Use Register. NFC   Craig Topper via llvm-commits
• [llvm] 9f8e148 - [CalcSpillWeights] Use Register. NFC   Craig Topper via llvm-commits
• [llvm] 7cee4c7 - [CallingConvLower] Use MCRegister. NFC   Craig Topper via llvm-commits
• [llvm] caa798c - [GlobalISel] Use Register. NFC   Craig Topper via llvm-commits
• [llvm] 5387a77 - [CodeGen] Use MCRegister in CalleeSavedInfo. NFC   Craig Topper via llvm-commits