[llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)

[Craig Topper via llvm-commits]

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@@ -2750,6 +2750,46 @@ MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
       .setMIFlags(MemI.getFlags());
 }
 
+bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) {
+  switch (Opc) {
+  default:
+    return false;
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topperc wrote:

I don't understand the contents of this list. It has more than what Mips supports, but it is not all load and store opcodes. LB, LBU, and LWU are missing.

https://github.com/llvm/llvm-project/pull/124717