[llvm] e8379ea - [SLP]Add a test with incorrect bitwidth after minbitwidth analysis, NFC

Thu Feb 27 08:29:30 PST 2025

Author: Alexey Bataev
Date: 2025-02-27T08:29:20-08:00
New Revision: e8379ea46469b7f8bfec1d9610d967967a62848f

URL: https://github.com/llvm/llvm-project/commit/e8379ea46469b7f8bfec1d9610d967967a62848f
DIFF: https://github.com/llvm/llvm-project/commit/e8379ea46469b7f8bfec1d9610d967967a62848f.diff

LOG: [SLP]Add a test with incorrect bitwidth after minbitwidth analysis, NFC

Added: 
    llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-different-bitwidth.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-
diff erent-bitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-
diff erent-bitwidth.ll
new file mode 100644
index 0000000000000..227c237826c6c

--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-
diff erent-bitwidth.ll
@@ -0,0 +1,92 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-100 < %s | FileCheck %s
+
+ at f = global i32 zeroinitializer
+
+define i32 @test() {
+; CHECK-LABEL: define i32 @test() {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    store i32 152, ptr @f, align 4
+; CHECK-NEXT:    [[AGG_TMP_SROA_0_0_COPYLOAD_I:%.*]] = load i32, ptr @f, align 4
+; CHECK-NEXT:    [[ADD_I_I:%.*]] = shl i32 [[AGG_TMP_SROA_0_0_COPYLOAD_I]], 24
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <8 x i32> <i32 poison, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080>, i32 [[ADD_I_I]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = add <8 x i32> <i32 83886080, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, [[TMP0]]
+; CHECK-NEXT:    [[TMP2:%.*]] = ashr <8 x i32> [[TMP1]], splat (i32 24)
+; CHECK-NEXT:    [[TMP3:%.*]] = trunc <8 x i32> [[TMP2]] to <8 x i8>
+; CHECK-NEXT:    [[TMP4:%.*]] = and <8 x i8> [[TMP3]], <i8 -65, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+; CHECK-NEXT:    [[TMP5:%.*]] = zext <8 x i8> [[TMP4]] to <8 x i32>
+; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <8 x i32> [[TMP5]], <8 x i32> poison, <2 x i32> <i32 0, i32 poison>
+; CHECK-NEXT:    [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> <i32 poison, i32 0>, <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[TMP8:%.*]] = icmp ugt <2 x i32> [[TMP7]], <i32 33554431, i32 0>
+; CHECK-NEXT:    [[TMP9:%.*]] = call <8 x i1> @llvm.vector.insert.v8i1.v2i1(<8 x i1> <i1 poison, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <2 x i1> [[TMP8]], i64 0)
+; CHECK-NEXT:    [[TMP10:%.*]] = select <8 x i1> [[TMP9]], <8 x i8> zeroinitializer, <8 x i8> <i8 6, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+; CHECK-NEXT:    [[TMP11:%.*]] = shl <8 x i8> [[TMP4]], [[TMP10]]
+; CHECK-NEXT:    [[TMP12:%.*]] = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> [[TMP11]])
+; CHECK-NEXT:    [[CONV:%.*]] = zext i8 [[TMP12]] to i32
+; CHECK-NEXT:    ret i32 [[CONV]]
+;
+entry:
+  store i32 152, ptr @f, align 4
+  %agg.tmp.sroa.0.0.copyload.i = load i32, ptr @f, align 4
+  %add.i.i = shl i32 %agg.tmp.sroa.0.0.copyload.i, 24
+  %sext.i = add i32 %add.i.i, 83886080
+  %conv2.i = ashr i32 %sext.i, 24
+  %and.i = and i32 %conv2.i, 66440127
+  %cmp3.i.i = icmp ugt i32 %and.i, 33554431
+  %shl.i.i = select i1 %cmp3.i.i, i32 0, i32 6
+  %cond.i.i = shl i32 %and.i, %shl.i.i
+  %0 = trunc i32 %cond.i.i to i8
+  %sext.1.i = add i32 0, 83886080
+  %conv2.1.i = ashr i32 %sext.1.i, 24
+  %and.1.i = and i32 %conv2.1.i, 1
+  %cmp3.i.1.i = icmp ugt i32 0, 0
+  %shl.i.1.i = select i1 %cmp3.i.1.i, i32 0, i32 0
+  %cond.i.1.i = shl i32 %and.1.i, %shl.i.1.i
+  %1 = trunc i32 %cond.i.1.i to i8
+  %conv17.1.i = and i8 %0, %1
+  %sext.2.i = add i32 0, 83886080
+  %conv2.2.i = ashr i32 %sext.2.i, 24
+  %and.2.i = and i32 %conv2.2.i, 1
+  %shl.i.2.i = select i1 false, i32 0, i32 0
+  %cond.i.2.i = shl i32 %and.2.i, %shl.i.2.i
+  %2 = trunc i32 %cond.i.2.i to i8
+  %conv17.2.i = and i8 %conv17.1.i, %2
+  %sext.3.i = add i32 0, 83886080
+  %conv2.3.i = ashr i32 %sext.3.i, 24
+  %and.3.i = and i32 %conv2.3.i, 1
+  %shl.i.3.i = select i1 false, i32 0, i32 0
+  %cond.i.3.i = shl i32 %and.3.i, %shl.i.3.i
+  %3 = trunc i32 %cond.i.3.i to i8
+  %conv17.3.i = and i8 %conv17.2.i, %3
+  %sext.4.i = add i32 0, 83886080
+  %conv2.4.i = ashr i32 %sext.4.i, 24
+  %and.4.i = and i32 %conv2.4.i, 1
+  %shl.i.4.i = select i1 false, i32 0, i32 0
+  %cond.i.4.i = shl i32 %and.4.i, %shl.i.4.i
+  %4 = trunc i32 %cond.i.4.i to i8
+  %conv17.4.i = and i8 %conv17.3.i, %4
+  %sext.5.i = add i32 0, 83886080
+  %conv2.5.i = ashr i32 %sext.5.i, 24
+  %and.5.i = and i32 %conv2.5.i, 1
+  %shl.i.5.i = select i1 false, i32 0, i32 0
+  %cond.i.5.i = shl i32 %and.5.i, %shl.i.5.i
+  %5 = trunc i32 %cond.i.5.i to i8
+  %conv17.5.i = and i8 %conv17.4.i, %5
+  %sext.6.i = add i32 0, 83886080
+  %conv2.6.i = ashr i32 %sext.6.i, 24
+  %and.6.i = and i32 %conv2.6.i, 1
+  %shl.i.6.i = select i1 false, i32 0, i32 0
+  %cond.i.6.i = shl i32 %and.6.i, %shl.i.6.i
+  %6 = trunc i32 %cond.i.6.i to i8
+  %conv17.6.i = and i8 %conv17.5.i, %6
+  %sext.7.i = add i32 0, 83886080
+  %conv2.7.i = ashr i32 %sext.7.i, 24
+  %and.7.i = and i32 %conv2.7.i, 1
+  %shl.i.7.i = select i1 false, i32 0, i32 0
+  %cond.i.7.i = shl i32 %and.7.i, %shl.i.7.i
+  %7 = trunc i32 %cond.i.7.i to i8
+  %conv17.7.i = and i8 %conv17.6.i, %7
+  %conv = zext i8 %conv17.7.i to i32
+  ret i32 %conv
+}
+


        
