[llvm] [RISCV] Use addiw for or_is_add when or input is sign extended. (PR #128635)

[Craig Topper via llvm-commits]

topperc wrote:

> LGTM.
> 
> This feels a bit like fixing a symptom instead of the true cause. A worthwhile thing to do, but should we go further than this and extend the reasoning in the sext.w removal pas too?

Probably, but that's a big change to the pass. We'll need to implement the equivalent of computeKnownBits for every instruction inside of it.

https://github.com/llvm/llvm-project/pull/128635