[llvm] 49ba565 - [IfConversion] Use MCRegister. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-03-02T23:46:16-08:00
New Revision: 49ba565913e189f45e0822f475b0f61f50670c55

URL: https://github.com/llvm/llvm-project/commit/49ba565913e189f45e0822f475b0f61f50670c55
DIFF: https://github.com/llvm/llvm-project/commit/49ba565913e189f45e0822f475b0f61f50670c55.diff

LOG: [IfConversion] Use MCRegister. NFC

Added: 
    

Modified: 
    llvm/lib/CodeGen/IfConversion.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp
index fa817097029aa..2ea086e53a5df 100644
--- a/llvm/lib/CodeGen/IfConversion.cpp
+++ b/llvm/lib/CodeGen/IfConversion.cpp
@@ -269,10 +269,9 @@ namespace {
     bool IfConvertForkedDiamond(BBInfo &BBI, IfcvtKind Kind,
                               unsigned NumDups1, unsigned NumDups2,
                               bool TClobbers, bool FClobbers);
-    void PredicateBlock(BBInfo &BBI,
-                        MachineBasicBlock::iterator E,
+    void PredicateBlock(BBInfo &BBI, MachineBasicBlock::iterator E,
                         SmallVectorImpl<MachineOperand> &Cond,
-                        SmallSet<MCPhysReg, 4> *LaterRedefs = nullptr);
+                        SmallSet<MCRegister, 4> *LaterRedefs = nullptr);
     void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
                                SmallVectorImpl<MachineOperand> &Cond,
                                bool IgnoreBr = false);
@@ -1926,13 +1925,13 @@ bool IfConverter::IfConvertDiamondCommon(
   // generate:
   //   sub    r0, r1, #1
   //   addne  r0, r1, #1
-  SmallSet<MCPhysReg, 4> RedefsByFalse;
-  SmallSet<MCPhysReg, 4> ExtUses;
+  SmallSet<MCRegister, 4> RedefsByFalse;
+  SmallSet<MCRegister, 4> ExtUses;
   if (TII->isProfitableToUnpredicate(MBB1, MBB2)) {
     for (const MachineInstr &FI : make_range(MBB2.begin(), DI2)) {
       if (FI.isDebugInstr())
         continue;
-      SmallVector<MCPhysReg, 4> Defs;
+      SmallVector<MCRegister, 4> Defs;
       for (const MachineOperand &MO : FI.operands()) {
         if (!MO.isReg())
           continue;
@@ -1949,7 +1948,7 @@ bool IfConverter::IfConvertDiamondCommon(
         }
       }
 
-      for (MCPhysReg Reg : Defs) {
+      for (MCRegister Reg : Defs) {
         if (!ExtUses.count(Reg)) {
           for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
             RedefsByFalse.insert(SubReg);
@@ -2094,7 +2093,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
 }
 
 static bool MaySpeculate(const MachineInstr &MI,
-                         SmallSet<MCPhysReg, 4> &LaterRedefs) {
+                         SmallSet<MCRegister, 4> &LaterRedefs) {
   bool SawStore = true;
   if (!MI.isSafeToMove(SawStore))
     return false;
@@ -2114,10 +2113,9 @@ static bool MaySpeculate(const MachineInstr &MI,
 
 /// Predicate instructions from the start of the block to the specified end with
 /// the specified condition.
-void IfConverter::PredicateBlock(BBInfo &BBI,
-                                 MachineBasicBlock::iterator E,
+void IfConverter::PredicateBlock(BBInfo &BBI, MachineBasicBlock::iterator E,
                                  SmallVectorImpl<MachineOperand> &Cond,
-                                 SmallSet<MCPhysReg, 4> *LaterRedefs) {
+                                 SmallSet<MCRegister, 4> *LaterRedefs) {
   bool AnyUnpred = false;
   bool MaySpec = LaterRedefs != nullptr;
   for (MachineInstr &I : make_range(BBI.BB->begin(), E)) {