[llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)

[Jay Foad via llvm-commits]

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@@ -362,6 +397,26 @@ class AMDGPUWaitSGPRHazards {
           Mask = AMDGPU::DepCtr::encodeFieldVaSdst(Mask, 0);
         }
         if (Emit) {
+          MachineInstr *PrevWaitAlu = nullptr;
+          if (MI != MI->getParent()->begin()) {
+            PrevWaitAlu = getPreviousWaitAlu(MI);
+          } else {
+            auto Preds = MBB.predecessors();
+            if (MBB.pred_size() == 1) {
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jayfoad wrote:

I guess here you are relying on the fact that if the predecessor block ends with s_wait_alu then it must fall through into MBB, i.e. it only has a single successor. But does the single-successor --> single predecessor case really occur often enough to be worth handling here?

https://github.com/llvm/llvm-project/pull/128916