[llvm] dcca3f4 - Revert "[AggressiveAntiDepBreaker] Use MCRegister. NFC"
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 2 13:01:50 PST 2025
Author: Craig Topper
Date: 2025-03-02T13:01:26-08:00
New Revision: dcca3f407cf138eee8d935fdbe24b4ccd1970968
URL: https://github.com/llvm/llvm-project/commit/dcca3f407cf138eee8d935fdbe24b4ccd1970968
DIFF: https://github.com/llvm/llvm-project/commit/dcca3f407cf138eee8d935fdbe24b4ccd1970968.diff
LOG: Revert "[AggressiveAntiDepBreaker] Use MCRegister. NFC"
This reverts commit fd3326b65f83968541d7df32c07c12892bd2dc04.
Getting a failure on the buildbots
Added:
Modified:
llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
index caa616c6b6b05..2f123c22b330e 100644
--- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -67,7 +67,7 @@ AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
}
}
-unsigned AggressiveAntiDepState::GetGroup(MCRegister Reg) {
+unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
unsigned Node = GroupNodeIndices[Reg];
while (GroupNodes[Node] != Node)
Node = GroupNodes[Node];
@@ -76,16 +76,17 @@ unsigned AggressiveAntiDepState::GetGroup(MCRegister Reg) {
}
void AggressiveAntiDepState::GetGroupRegs(
- unsigned Group, std::vector<MCRegister> &Regs,
- std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
- *RegRefs) {
+ unsigned Group,
+ std::vector<unsigned> &Regs,
+ std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
+{
for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
Regs.push_back(Reg);
}
}
-unsigned AggressiveAntiDepState::UnionGroups(MCRegister Reg1, MCRegister Reg2) {
+unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) {
assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
@@ -100,7 +101,7 @@ unsigned AggressiveAntiDepState::UnionGroups(MCRegister Reg1, MCRegister Reg2) {
return Parent;
}
-unsigned AggressiveAntiDepState::LeaveGroup(MCRegister Reg) {
+unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) {
// Create a new GroupNode for Reg. Reg's existing GroupNode must
// stay as is because there could be other GroupNodes referring to
// it.
@@ -110,7 +111,7 @@ unsigned AggressiveAntiDepState::LeaveGroup(MCRegister Reg) {
return idx;
}
-bool AggressiveAntiDepState::IsLive(MCRegister Reg) {
+bool AggressiveAntiDepState::IsLive(unsigned Reg) {
// KillIndex must be defined and DefIndex not defined for a register
// to be live.
return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
@@ -172,7 +173,7 @@ void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
if (!IsReturnBlock && !Pristine.test(Reg))
continue;
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
- MCRegister AliasReg = *AI;
+ unsigned AliasReg = *AI;
State->UnionGroups(AliasReg, 0);
KillIndices[AliasReg] = BB->size();
DefIndices[AliasReg] = ~0u;
@@ -189,7 +190,7 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
unsigned InsertPosIndex) {
assert(Count < InsertPosIndex && "Instruction index out of expected range!");
- std::set<MCRegister> PassthruRegs;
+ std::set<unsigned> PassthruRegs;
GetPassthruRegs(MI, PassthruRegs);
PrescanInstruction(MI, Count, PassthruRegs);
ScanInstruction(MI, Count);
@@ -238,7 +239,7 @@ bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI,
}
void AggressiveAntiDepBreaker::GetPassthruRegs(
- MachineInstr &MI, std::set<MCRegister> &PassthruRegs) {
+ MachineInstr &MI, std::set<unsigned> &PassthruRegs) {
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg()) continue;
@@ -287,14 +288,14 @@ static const SUnit *CriticalPathStep(const SUnit *SU) {
return (Next) ? Next->getSUnit() : nullptr;
}
-void AggressiveAntiDepBreaker::HandleLastUse(MCRegister Reg, unsigned KillIdx,
+void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
const char *tag,
const char *header,
const char *footer) {
std::vector<unsigned> &KillIndices = State->GetKillIndices();
std::vector<unsigned> &DefIndices = State->GetDefIndices();
- std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
- &RegRefs = State->GetRegRefs();
+ std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
+ RegRefs = State->GetRegRefs();
// FIXME: We must leave subregisters of live super registers as live, so that
// we don't clear out the register tracking information for subregisters of
@@ -340,11 +341,10 @@ void AggressiveAntiDepBreaker::HandleLastUse(MCRegister Reg, unsigned KillIdx,
}
void AggressiveAntiDepBreaker::PrescanInstruction(
- MachineInstr &MI, unsigned Count,
- const std::set<MCRegister> &PassthruRegs) {
+ MachineInstr &MI, unsigned Count, std::set<unsigned> &PassthruRegs) {
std::vector<unsigned> &DefIndices = State->GetDefIndices();
- std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
- &RegRefs = State->GetRegRefs();
+ std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
+ RegRefs = State->GetRegRefs();
// Handle dead defs by simulating a last-use of the register just
// after the def. A dead def can occur because the def is truly
@@ -353,10 +353,9 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
// previous def.
for (const MachineOperand &MO : MI.all_defs()) {
Register Reg = MO.getReg();
- if (!Reg)
- continue;
+ if (Reg == 0) continue;
- HandleLastUse(Reg.asMCReg(), Count + 1, "", "\tDead Def: ", "\n");
+ HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
}
LLVM_DEBUG(dbgs() << "\tDef Groups:");
@@ -364,8 +363,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isDef()) continue;
Register Reg = MO.getReg();
- if (!Reg)
- continue;
+ if (Reg == 0) continue;
LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
<< State->GetGroup(Reg));
@@ -384,7 +382,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
// Any aliased that are live at this point are completely or
// partially defined here, so group those aliases with Reg.
for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
- MCRegister AliasReg = *AI;
+ unsigned AliasReg = *AI;
if (State->IsLive(AliasReg)) {
State->UnionGroups(Reg, AliasReg);
LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via "
@@ -406,8 +404,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
// live-ranges.
for (const MachineOperand &MO : MI.all_defs()) {
Register Reg = MO.getReg();
- if (!Reg)
- continue;
+ if (Reg == 0) continue;
// Ignore KILLs and passthru registers for liveness...
if (MI.isKill() || (PassthruRegs.count(Reg) != 0))
continue;
@@ -431,8 +428,8 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
unsigned Count) {
LLVM_DEBUG(dbgs() << "\tUse Groups:");
- std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
- &RegRefs = State->GetRegRefs();
+ std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
+ RegRefs = State->GetRegRefs();
// If MI's uses have special allocation requirement, don't allow
// any use registers to be changed. Also assume all registers
@@ -460,8 +457,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isUse()) continue;
Register Reg = MO.getReg();
- if (!Reg)
- continue;
+ if (Reg == 0) continue;
LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
<< State->GetGroup(Reg));
@@ -469,7 +465,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
// It wasn't previously live but now it is, this is a kill. Forget
// the previous live-range information and start a new live-range
// for the register.
- HandleLastUse(Reg.asMCReg(), Count, "(last-use)");
+ HandleLastUse(Reg, Count, "(last-use)");
if (Special) {
LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
@@ -491,14 +487,13 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
if (MI.isKill()) {
LLVM_DEBUG(dbgs() << "\tKill Group:");
- Register FirstReg;
+ unsigned FirstReg = 0;
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg()) continue;
Register Reg = MO.getReg();
- if (!Reg)
- continue;
+ if (Reg == 0) continue;
- if (FirstReg) {
+ if (FirstReg != 0) {
LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI));
State->UnionGroups(FirstReg, Reg);
} else {
@@ -511,7 +506,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
}
}
-BitVector AggressiveAntiDepBreaker::GetRenameRegisters(MCRegister Reg) {
+BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
BitVector BV(TRI->getNumRegs(), false);
bool first = true;
@@ -537,17 +532,17 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(MCRegister Reg) {
}
bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
- MCRegister SuperReg, unsigned AntiDepGroupIndex,
- RenameOrderType &RenameOrder, std::map<MCRegister, MCRegister> &RenameMap) {
+ unsigned SuperReg, unsigned AntiDepGroupIndex, RenameOrderType &RenameOrder,
+ std::map<unsigned, unsigned> &RenameMap) {
std::vector<unsigned> &KillIndices = State->GetKillIndices();
std::vector<unsigned> &DefIndices = State->GetDefIndices();
- std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
- &RegRefs = State->GetRegRefs();
+ std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
+ RegRefs = State->GetRegRefs();
// Collect all referenced registers in the same group as
// AntiDepReg. These all need to be renamed together if we are to
// break the anti-dependence.
- std::vector<MCRegister> Regs;
+ std::vector<unsigned> Regs;
State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
assert(!Regs.empty() && "Empty register group!");
if (Regs.empty())
@@ -557,8 +552,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
// each register.
LLVM_DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
<< ":\n");
- std::map<MCRegister, BitVector> RenameRegisterMap;
- for (MCRegister Reg : Regs) {
+ std::map<unsigned, BitVector> RenameRegisterMap;
+ for (unsigned Reg : Regs) {
// If Reg has any references, then collect possible rename regs
if (RegRefs.count(Reg) > 0) {
LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
@@ -577,7 +572,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
}
// All group registers should be a subreg of SuperReg.
- for (MCRegister Reg : Regs) {
+ for (unsigned Reg : Regs) {
if (Reg == SuperReg) continue;
bool IsSub = TRI->isSubRegister(SuperReg, Reg);
// FIXME: remove this once PR18663 has been properly fixed. For now,
@@ -626,7 +621,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
do {
if (R == 0) R = Order.size();
--R;
- const MCRegister NewSuperReg = Order[R];
+ const unsigned NewSuperReg = Order[R];
// Don't consider non-allocatable registers
if (!MRI.isAllocatable(NewSuperReg)) continue;
// Don't replace a register with itself.
@@ -638,8 +633,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
// For each referenced group register (which must be a SuperReg or
// a subregister of SuperReg), find the corresponding subregister
// of NewSuperReg and make sure it is free to be renamed.
- for (MCRegister Reg : Regs) {
- MCRegister NewReg;
+ for (unsigned Reg : Regs) {
+ unsigned NewReg = 0;
if (Reg == SuperReg) {
NewReg = NewSuperReg;
} else {
@@ -666,7 +661,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
} else {
bool found = false;
for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
- MCRegister AliasReg = *AI;
+ unsigned AliasReg = *AI;
if (State->IsLive(AliasReg) ||
(KillIndices[Reg] > DefIndices[AliasReg])) {
LLVM_DEBUG(dbgs()
@@ -708,7 +703,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
}
// Record that 'Reg' can be renamed to 'NewReg'.
- RenameMap.insert(std::make_pair(Reg, NewReg));
+ RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
}
// If we fall-out here, then every register in the group can be
@@ -738,8 +733,8 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
DbgValueVector &DbgValues) {
std::vector<unsigned> &KillIndices = State->GetKillIndices();
std::vector<unsigned> &DefIndices = State->GetDefIndices();
- std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
- &RegRefs = State->GetRegRefs();
+ std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
+ RegRefs = State->GetRegRefs();
// The code below assumes that there is at least one instruction,
// so just duck out immediately if the block is empty.
@@ -797,7 +792,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
LLVM_DEBUG(dbgs() << "Anti: ");
LLVM_DEBUG(MI.dump());
- std::set<MCRegister> PassthruRegs;
+ std::set<unsigned> PassthruRegs;
GetPassthruRegs(MI, PassthruRegs);
// Process the defs in MI...
@@ -829,15 +824,15 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
if ((Edge->getKind() != SDep::Anti) &&
(Edge->getKind() != SDep::Output)) continue;
- MCRegister AntiDepReg = MCRegister::from(Edge->getReg());
+ unsigned AntiDepReg = Edge->getReg();
LLVM_DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
- assert(AntiDepReg && "Anti-dependence on reg0?");
+ assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
if (!MRI.isAllocatable(AntiDepReg)) {
// Don't break anti-dependencies on non-allocatable registers.
LLVM_DEBUG(dbgs() << " (non-allocatable)\n");
continue;
- } else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg.id())) {
+ } else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
// Don't break anti-dependencies for critical path registers
// if not on the critical path
LLVM_DEBUG(dbgs() << " (not critical-path)\n");
@@ -872,7 +867,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
Pred.getReg() != AntiDepReg)
: (Pred.getKind() == SDep::Data &&
Pred.getReg() == AntiDepReg)) {
- AntiDepReg = MCRegister();
+ AntiDepReg = 0;
break;
}
}
@@ -880,22 +875,22 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
if ((Pred.getSUnit() == NextSU) && (Pred.getKind() != SDep::Anti) &&
(Pred.getKind() != SDep::Output)) {
LLVM_DEBUG(dbgs() << " (real dependency)\n");
- AntiDepReg = MCRegister();
+ AntiDepReg = 0;
break;
} else if ((Pred.getSUnit() != NextSU) &&
(Pred.getKind() == SDep::Data) &&
(Pred.getReg() == AntiDepReg)) {
LLVM_DEBUG(dbgs() << " (other dependency)\n");
- AntiDepReg = MCRegister();
+ AntiDepReg = 0;
break;
}
}
- if (!AntiDepReg)
+ if (AntiDepReg == 0)
continue;
}
- assert(AntiDepReg);
+ assert(AntiDepReg != 0);
// Determine AntiDepReg's register group.
const unsigned GroupIndex = State->GetGroup(AntiDepReg);
@@ -907,7 +902,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
LLVM_DEBUG(dbgs() << '\n');
// Look for a suitable register to use to break the anti-dependence.
- std::map<MCRegister, MCRegister> RenameMap;
+ std::map<unsigned, unsigned> RenameMap;
if (FindSuitableFreeRegisters(AntiDepReg, GroupIndex, RenameOrder,
RenameMap)) {
LLVM_DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
@@ -915,8 +910,8 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
// Handle each group register...
for (const auto &P : RenameMap) {
- MCRegister CurrReg = P.first;
- MCRegister NewReg = P.second;
+ unsigned CurrReg = P.first;
+ unsigned NewReg = P.second;
LLVM_DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
<< printReg(NewReg, TRI) << "("
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
index 8726cdef2bfc4..06c4c6957ba04 100644
--- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
+++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
@@ -66,7 +66,7 @@ class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
std::vector<unsigned> GroupNodeIndices;
/// Map registers to all their references within a live range.
- std::multimap<MCRegister, RegisterReference> RegRefs;
+ std::multimap<unsigned, RegisterReference> RegRefs;
/// The index of the most recent kill (proceeding bottom-up),
/// or ~0u if the register is not live.
@@ -86,32 +86,31 @@ class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
std::vector<unsigned> &GetDefIndices() { return DefIndices; }
/// Return the RegRefs map.
- std::multimap<MCRegister, RegisterReference> &GetRegRefs() {
- return RegRefs;
- }
+ std::multimap<unsigned, RegisterReference>& GetRegRefs() { return RegRefs; }
// Get the group for a register. The returned value is
// the index of the GroupNode representing the group.
- unsigned GetGroup(MCRegister Reg);
+ unsigned GetGroup(unsigned Reg);
// Return a vector of the registers belonging to a group.
// If RegRefs is non-NULL then only included referenced registers.
void GetGroupRegs(
- unsigned Group, std::vector<MCRegister> &Regs,
- std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
- *RegRefs);
+ unsigned Group,
+ std::vector<unsigned> &Regs,
+ std::multimap<unsigned,
+ AggressiveAntiDepState::RegisterReference> *RegRefs);
// Union Reg1's and Reg2's groups to form a new group.
// Return the index of the GroupNode representing the group.
- unsigned UnionGroups(MCRegister Reg1, MCRegister Reg2);
+ unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
// Remove a register from its current group and place
// it alone in its own group. Return the index of the GroupNode
// representing the registers new group.
- unsigned LeaveGroup(MCRegister Reg);
+ unsigned LeaveGroup(unsigned Reg);
/// Return true if Reg is live.
- bool IsLive(MCRegister Reg);
+ bool IsLive(unsigned Reg);
};
class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepBreaker
@@ -167,20 +166,20 @@ class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
/// If MI implicitly def/uses a register, then
/// return that register and all subregisters.
- void GetPassthruRegs(MachineInstr &MI, std::set<MCRegister> &PassthruRegs);
+ void GetPassthruRegs(MachineInstr &MI, std::set<unsigned> &PassthruRegs);
- void HandleLastUse(MCRegister Reg, unsigned KillIdx, const char *tag,
+ void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag,
const char *header = nullptr,
const char *footer = nullptr);
void PrescanInstruction(MachineInstr &MI, unsigned Count,
- const std::set<MCRegister> &PassthruRegs);
+ std::set<unsigned> &PassthruRegs);
void ScanInstruction(MachineInstr &MI, unsigned Count);
- BitVector GetRenameRegisters(MCRegister Reg);
- bool FindSuitableFreeRegisters(MCRegister SuperReg,
+ BitVector GetRenameRegisters(unsigned Reg);
+ bool FindSuitableFreeRegisters(unsigned SuperReg,
unsigned AntiDepGroupIndex,
RenameOrderType &RenameOrder,
- std::map<MCRegister, MCRegister> &RenameMap);
+ std::map<unsigned, unsigned> &RenameMap);
};
} // end namespace llvm
More information about the llvm-commits
mailing list