[llvm] [AMDGPU] Add custom MachineValueType entries for buffer fat poiners (PR #127692)

[Krzysztof Drewniak via llvm-commits]

================
@@ -331,6 +331,10 @@ def i64x8     : ValueType<512,  231>;  // 8 Consecutive GPRs (AArch64)
 def aarch64svcount
               : ValueType<16,  232>;  // AArch64 predicate-as-counter
 def spirvbuiltin : ValueType<0, 233>; // SPIR-V's builtin type
+// AMDGPU buffer fat pointer, buffer rsrc + offset, rewritten before MIR translation
+def amdgpuBufferFatPointer : ValueType<160, 234>;
+// AMDGPU buffer strided pointer, buffer rsrc + index + offset, doesn't reach MIR
+def amdgpuBufferStridedPointer : ValueType<192, 235>;
----------------
krzysz00 wrote:

To put out one more point, from what I can tell, it's an invariant of SelectionDAG that all the `MVT::i*` are powers of two - see also the lack of an `MVT::i96` even though we actually have instructions that that could meaningfully apply to.

https://github.com/llvm/llvm-project/pull/127692