[lld] 301fe47 - [AArch64][ELF] Section alignment of 4 for AArch64 instruction (#114031)

[via llvm-commits]

Author: Florin Popa
Date: 2025-02-24T09:17:04Z
New Revision: 301fe4797191e528d23dcaf52b8e47649d2bf555

URL: https://github.com/llvm/llvm-project/commit/301fe4797191e528d23dcaf52b8e47649d2bf555
DIFF: https://github.com/llvm/llvm-project/commit/301fe4797191e528d23dcaf52b8e47649d2bf555.diff

LOG: [AArch64][ELF] Section alignment of 4 for AArch64 instruction (#114031)

The integrated assembler sets a minimum alignment for the .text section
of 4. However user defined sections get an alignment of 1. Unlike the
GNU assembler which raises the section alignment to 4 if an AArch64
instruction is used, the integrated assembler leaves the alignment at 1

---------

Co-authored-by: Florin Popa <florin.popa at arm.com>

Added: 
    llvm/test/MC/AArch64/align-code.s

Modified: 
    lld/test/ELF/aarch64-relocs.s
    llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp

Removed: 
    


################################################################################
diff  --git a/lld/test/ELF/aarch64-relocs.s b/lld/test/ELF/aarch64-relocs.s
index 39cfcdd38661d..143b0fc56bf29 100644
--- a/lld/test/ELF/aarch64-relocs.s
+++ b/lld/test/ELF/aarch64-relocs.s
@@ -42,7 +42,7 @@ mystr:
 # CHECK: Disassembly of section .R_AARCH64_ADD_ABS_LO12_NC:
 # CHECK-EMPTY:
 # CHECK-NEXT: <.R_AARCH64_ADD_ABS_LO12_NC>:
-# CHECK-NEXT:   21013b:       9104fc00        add     x0, x0, #319
+# CHECK-NEXT:   210140: 91051000 add x0, x0, #324
 
 .section .R_AARCH64_LDST64_ABS_LO12_NC,"ax", at progbits
   ldr x28, [x27, :lo12:foo]
@@ -56,7 +56,7 @@ foo:
 # CHECK: Disassembly of section .R_AARCH64_LDST64_ABS_LO12_NC:
 # CHECK-EMPTY:
 # CHECK-NEXT: <.R_AARCH64_LDST64_ABS_LO12_NC>:
-# CHECK-NEXT:   210144:       f940a77c        ldr     x28, [x27, #328]
+# CHECK-NEXT:   21014c:       f940ab7c        ldr     x28, [x27, #336]
 
 .section .SUB,"ax", at progbits
   nop
@@ -86,7 +86,7 @@ foo32:
 # CHECK: Disassembly of section .R_AARCH64_LDST32_ABS_LO12_NC:
 # CHECK-EMPTY:
 # CHECK-NEXT: <ldst32>:
-# CHECK-NEXT:   21015c:       bd4160a4        ldr s4, [x5, #352]
+# CHECK-NEXT:   210164:       bd4168a4     	  ldr	s4, [x5, #360]
 
 .section .R_AARCH64_LDST8_ABS_LO12_NC,"ax", at progbits
 ldst8:
@@ -101,24 +101,26 @@ foo8:
 # CHECK: Disassembly of section .R_AARCH64_LDST8_ABS_LO12_NC:
 # CHECK-EMPTY:
 # CHECK-NEXT: <ldst8>:
-# CHECK-NEXT:   210164:       3985a1ab        ldrsb x11, [x13, #360]
+# CHECK-NEXT:   21016c:       3985c1ab     	  ldrsb	x11, [x13, #368]
 
 .section .R_AARCH64_LDST128_ABS_LO12_NC,"ax", at progbits
 ldst128:
   ldr q20, [x19, #:lo12:foo128]
+  .balign 16
 foo128:
   .asciz "foo"
   .size mystr, 3
 
-# S = 0x21016c, A = 0x4
-# R = ((S + A) & 0xFF8) << 6 = 0x00005c00
-# 0x00005c00 | 0x3dc00274 = 0x3dc05e74
+# S = 210180, A = 0x4
+# R = ((S + A) & 0xFF8) << 6 = 0x00006000
+# 0x00006000 | 0x3dc00274 = 0x3dc06274
 # CHECK: Disassembly of section .R_AARCH64_LDST128_ABS_LO12_NC:
 # CHECK-EMPTY:
 # CHECK: <ldst128>:
-# CHECK:   21016c:       3dc05e74        ldr     q20, [x19, #368]
+# CHECK:   210180:       3dc06674     	 ldr	   q20, [x19, #400]
 #foo128:
-#   210170:       66 6f 6f 00     .word
+# CHECK: <foo128>:
+# CHECK-NEXT:  210190:       66 6f 6f 00     .word
 
 .section .R_AARCH64_LDST16_ABS_LO12_NC,"ax", at progbits
 ldst16:
@@ -135,9 +137,9 @@ foo16:
 # CHECK: Disassembly of section .R_AARCH64_LDST16_ABS_LO12_NC:
 # CHECK-EMPTY:
 # CHECK-NEXT: <ldst16>:
-# CHECK-NEXT:   210174:       7d430271        ldr     h17, [x19, #384]
-# CHECK-NEXT:   210178:       79430261        ldrh    w1, [x19, #384]
-# CHECK-NEXT:   21017c:       79430662        ldrh    w2, [x19, #386]
+# CHECK-NEXT:   210194:       7d434271     	  ldr	    h17, [x19, #416]
+# CHECK-NEXT:   210198:       79434261     	  ldrh	  w1, [x19, #416]
+# CHECK-NEXT:   21019c:       79434662     	  ldrh	  w2, [x19, #418]
 
 .section .R_AARCH64_MOVW_UABS,"ax", at progbits
 movz1:

diff  --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
index d29d383bc2312..af64fceaa507e 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
@@ -325,6 +325,10 @@ class AArch64ELFStreamer : public MCELFStreamer {
       LastEMS = EMS_None;
 
     MCELFStreamer::changeSection(Section, Subsection);
+
+    // Section alignment of 4 to match GNU Assembler
+    if (Section->isText())
+      Section->ensureMinAlignment(Align(4));
   }
 
   // Reset state between object emissions

diff  --git a/llvm/test/MC/AArch64/align-code.s b/llvm/test/MC/AArch64/align-code.s
new file mode 100644
index 0000000000000..d9bbb268d2242
--- /dev/null
+++ b/llvm/test/MC/AArch64/align-code.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -o %t.o %s
+// RUN: llvm-readobj -S --sd %t.o | FileCheck %s
+.section sec00, "ax"
+.byte 1
+.section sec01, "ax"
+nop
+nop
+.section sec02, "ax"
+.balign 4
+nop
+nop
+.section sec03, "ax"
+.balign 8
+nop
+nop
+.section sec04, "ax"
+.byte 0
+.section sec05, "aw"
+nop
+nop
+// CHECK: Name: sec00
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec01
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec02
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec03
+// CHECK: AddressAlignment: 8
+// CHECK: Name: sec04
+// CHECK: AddressAlignment: 4
+// CHECK: Name: sec05
+// CHECK: AddressAlignment: 1
\ No newline at end of file