[llvm] [PPC] Implement `areInlineCompatible` (PR #126562)
Henry Jiang via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 24 14:17:54 PST 2025
https://github.com/mustartt updated https://github.com/llvm/llvm-project/pull/126562
>From db41712e1f507ba8559a0472e92a2a1a4517f327 Mon Sep 17 00:00:00 2001
From: Henry Jiang <henry.jiang1 at ibm.com>
Date: Mon, 10 Feb 2025 13:03:59 -0500
Subject: [PATCH 1/4] Implement areInlineCompatible for PPC
---
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 14 ++++++++++++++
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index c308ec332e844..26e9b4b9facec 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -895,6 +895,20 @@ PPCTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
return BaseT::getIntrinsicInstrCost(ICA, CostKind);
}
+bool PPCTTIImpl::areInlineCompatible(const Function *Caller,
+ const Function *Callee) const {
+ const TargetMachine &TM = getTLI()->getTargetMachine();
+
+ const FeatureBitset &CallerBits =
+ TM.getSubtargetImpl(*Caller)->getFeatureBits();
+ const FeatureBitset &CalleeBits =
+ TM.getSubtargetImpl(*Callee)->getFeatureBits();
+
+ // Check that targets features are exactly the same. We can revisit to see if
+ // we can improve this.
+ return CallerBits == CalleeBits;
+}
+
bool PPCTTIImpl::areTypesABICompatible(const Function *Caller,
const Function *Callee,
const ArrayRef<Type *> &Types) const {
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
index 3cb60d7a1785a..bf3ddad134e14 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -139,6 +139,8 @@ class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> {
bool UseMaskForCond = false, bool UseMaskForGaps = false);
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind);
+ bool areInlineCompatible(const Function *Caller,
+ const Function *Callee) const;
bool areTypesABICompatible(const Function *Caller, const Function *Callee,
const ArrayRef<Type *> &Types) const;
bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
>From ad6127b6517bb403896de80a5cc540440f653d50 Mon Sep 17 00:00:00 2001
From: Henry Jiang <henry.jiang1 at ibm.com>
Date: Mon, 10 Feb 2025 15:27:00 -0500
Subject: [PATCH 2/4] add inline attr test
---
.../Inline/PowerPC/inline-target-attr.ll | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
diff --git a/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
new file mode 100644
index 0000000000000..ff11ca827023f
--- /dev/null
+++ b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
@@ -0,0 +1,37 @@
+; RUN: opt < %s -mtriple=powerpc64le-ibm-linux-gnu -S -passes=inline | FileCheck %s
+; RUN: opt < %s -mtriple=powerpc64le-ibm-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s
+
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64le-ibm-linux-gnu"
+
+declare i32 @inlined()
+
+define i32 @foo() #0 {
+; CHECK-LABEL: foo
+; CHECK: entry
+; CHECK-NEXT: call i32 @bar()
+; CHECK-NEXT: call i32 @inlined()
+entry:
+ %1 = call i32 @bar()
+ %2 = call i32 @baz()
+ %3 = add i32 %1, %2
+ ret i32 %3
+}
+
+define i32 @bar() #1 {
+entry:
+ %1 = call i32 @inlined()
+ ret i32 %1
+}
+
+define i32 @baz() #0 {
+entry:
+ %1 = call i32 @inlined()
+ ret i32 %1
+}
+
+attributes #0 = { "target-cpu"="pwr7" "target-features"="+allow-unaligned-fp-access" }
+
+; We explictly disable -power8-vector to avoid emitting those instructions
+; so we should not inline them into +power8-vector
+attributes #1 = { "target-cpu"="pwr7" "target-features"="-allow-unaligned-fp-access" }
>From 1cb4c8f25fd3651b9d753dece691e65eb012636e Mon Sep 17 00:00:00 2001
From: Henry Jiang <henry.jiang1 at ibm.com>
Date: Mon, 10 Feb 2025 16:18:02 -0500
Subject: [PATCH 3/4] remove test comments
---
llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll | 3 ---
1 file changed, 3 deletions(-)
diff --git a/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
index ff11ca827023f..821ef4bbd9fc9 100644
--- a/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
+++ b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
@@ -31,7 +31,4 @@ entry:
}
attributes #0 = { "target-cpu"="pwr7" "target-features"="+allow-unaligned-fp-access" }
-
-; We explictly disable -power8-vector to avoid emitting those instructions
-; so we should not inline them into +power8-vector
attributes #1 = { "target-cpu"="pwr7" "target-features"="-allow-unaligned-fp-access" }
>From ebe7d942073423c6d324d4b26df907190c36db6f Mon Sep 17 00:00:00 2001
From: Henry Jiang <henry.jiang1 at ibm.com>
Date: Mon, 24 Feb 2025 17:17:21 -0500
Subject: [PATCH 4/4] add default testcase
---
.../Inline/PowerPC/inline-target-attr.ll | 59 ++++++++++++++-----
1 file changed, 44 insertions(+), 15 deletions(-)
diff --git a/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
index 821ef4bbd9fc9..b7086199e6f7d 100644
--- a/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
+++ b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
@@ -4,31 +4,60 @@
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64le-ibm-linux-gnu"
-declare i32 @inlined()
+declare void @inlined()
-define i32 @foo() #0 {
-; CHECK-LABEL: foo
+define void @explicit() #0 {
+; CHECK-LABEL: explicit
; CHECK: entry
-; CHECK-NEXT: call i32 @bar()
-; CHECK-NEXT: call i32 @inlined()
+; CHECK-NEXT: call void @not_compatible1()
+; CHECK-NEXT: call void @inlined()
entry:
- %1 = call i32 @bar()
- %2 = call i32 @baz()
- %3 = add i32 %1, %2
- ret i32 %3
+ call void @not_compatible1()
+ call void @compatible1()
+ ret void
}
-define i32 @bar() #1 {
+define void @not_compatible1() #1 {
entry:
- %1 = call i32 @inlined()
- ret i32 %1
+ call i32 @inlined()
+ ret void
}
-define i32 @baz() #0 {
+define void @compatible1() #0 {
entry:
- %1 = call i32 @inlined()
- ret i32 %1
+ call void @inlined()
+ ret void
}
+define void @default() #3 {
+; CHECK-LABEL: default
+; CHECK: entry
+; CHECK-NEXT: call void @not_compatible2()
+; CHECK-NEXT: call void @inlined()
+entry:
+ call void @not_compatible2()
+ call void @compatible2()
+ ret void
+}
+
+define void @not_compatible2() #4 {
+entry:
+ call void @inlined()
+ ret void
+}
+
+define void @compatible2() #5 {
+entry:
+ call void @inlined()
+ ret void
+}
+
+; explicit
attributes #0 = { "target-cpu"="pwr7" "target-features"="+allow-unaligned-fp-access" }
attributes #1 = { "target-cpu"="pwr7" "target-features"="-allow-unaligned-fp-access" }
+
+; pwr7 by default implies +vsx
+attributes #3 = { "target-cpu"="pwr7" }
+attributes #4 = { "target-cpu"="pwr7" "target-features"="-vsx" }
+attributes #5 = { "target-cpu"="pwr7" "target-features"="+vsx" }
+
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