[llvm] 81a8b5c - [MachineSink] Use Register and MCRegUnit. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 1 22:04:16 PST 2025
Author: Craig Topper
Date: 2025-03-01T21:57:04-08:00
New Revision: 81a8b5c579acc7597fdb1069355e733aaa7466d4
URL: https://github.com/llvm/llvm-project/commit/81a8b5c579acc7597fdb1069355e733aaa7466d4
DIFF: https://github.com/llvm/llvm-project/commit/81a8b5c579acc7597fdb1069355e733aaa7466d4.diff
LOG: [MachineSink] Use Register and MCRegUnit. NFC
Added:
Modified:
llvm/lib/CodeGen/MachineSink.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 82acb780cfb72..0dbf5605d0567 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -169,7 +169,7 @@ class MachineSinking : public MachineFunctionPass {
/// Record of DBG_VALUE uses of vregs in a block, so that we can identify
/// debug instructions to sink.
- SmallDenseMap<unsigned, TinyPtrVector<SeenDbgUser>> SeenDbgUsers;
+ SmallDenseMap<Register, TinyPtrVector<SeenDbgUser>> SeenDbgUsers;
/// Record of debug variables that have had their locations set in the
/// current block.
@@ -1518,7 +1518,7 @@ static bool attemptDebugCopyProp(MachineInstr &SinkInst, MachineInstr &DbgMI,
return true;
}
-using MIRegs = std::pair<MachineInstr *, SmallVector<unsigned, 2>>;
+using MIRegs = std::pair<MachineInstr *, SmallVector<Register, 2>>;
/// Sink an instruction and its associated debug instructions.
static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo,
MachineBasicBlock::iterator InsertPos,
@@ -1547,7 +1547,7 @@ static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo,
SuccToSinkTo.insert(InsertPos, NewDbgMI);
bool PropagatedAllSunkOps = true;
- for (unsigned Reg : DbgValueToSink.second) {
+ for (Register Reg : DbgValueToSink.second) {
if (DbgMI->hasDebugOperandForReg(Reg)) {
if (!attemptDebugCopyProp(MI, *DbgMI, Reg)) {
PropagatedAllSunkOps = false;
@@ -1883,7 +1883,7 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
DbgMI->setDebugValueUndef();
} else {
DbgUsersToSink.push_back(
- {DbgMI, SmallVector<unsigned, 2>(1, MO.getReg())});
+ {DbgMI, SmallVector<Register, 2>(1, MO.getReg())});
}
}
}
@@ -2010,7 +2010,7 @@ class PostRAMachineSinking : public MachineFunctionPass {
/// entry in this map for each unit it touches. The DBG_VALUE's entry
/// consists of a pointer to the instruction itself, and a vector of registers
/// referred to by the instruction that overlap the key register unit.
- DenseMap<unsigned, SmallVector<MIRegs, 2>> SeenDbgInstrs;
+ DenseMap<MCRegUnit, SmallVector<MIRegs, 2>> SeenDbgInstrs;
/// Sink Copy instructions unused in the same block close to their uses in
/// successors.
@@ -2025,7 +2025,7 @@ char &llvm::PostRAMachineSinkingID = PostRAMachineSinking::ID;
INITIALIZE_PASS(PostRAMachineSinking, "postra-machine-sink",
"PostRA Machine Sink", false, false)
-static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB, unsigned Reg,
+static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB, Register Reg,
const TargetRegisterInfo *TRI) {
LiveRegUnits LiveInRegUnits(*TRI);
LiveInRegUnits.addLiveIns(MBB);
@@ -2035,7 +2035,7 @@ static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB, unsigned Reg,
static MachineBasicBlock *
getSingleLiveInSuccBB(MachineBasicBlock &CurBB,
const SmallPtrSetImpl<MachineBasicBlock *> &SinkableBBs,
- unsigned Reg, const TargetRegisterInfo *TRI) {
+ Register Reg, const TargetRegisterInfo *TRI) {
// Try to find a single sinkable successor in which Reg is live-in.
MachineBasicBlock *BB = nullptr;
for (auto *SI : SinkableBBs) {
@@ -2062,7 +2062,7 @@ getSingleLiveInSuccBB(MachineBasicBlock &CurBB,
static MachineBasicBlock *
getSingleLiveInSuccBB(MachineBasicBlock &CurBB,
const SmallPtrSetImpl<MachineBasicBlock *> &SinkableBBs,
- ArrayRef<unsigned> DefedRegsInCopy,
+ ArrayRef<Register> DefedRegsInCopy,
const TargetRegisterInfo *TRI) {
MachineBasicBlock *SingleBB = nullptr;
for (auto DefReg : DefedRegsInCopy) {
@@ -2076,8 +2076,8 @@ getSingleLiveInSuccBB(MachineBasicBlock &CurBB,
}
static void clearKillFlags(MachineInstr *MI, MachineBasicBlock &CurBB,
- SmallVectorImpl<unsigned> &UsedOpsInCopy,
- LiveRegUnits &UsedRegUnits,
+ const SmallVectorImpl<unsigned> &UsedOpsInCopy,
+ const LiveRegUnits &UsedRegUnits,
const TargetRegisterInfo *TRI) {
for (auto U : UsedOpsInCopy) {
MachineOperand &MO = MI->getOperand(U);
@@ -2096,11 +2096,11 @@ static void clearKillFlags(MachineInstr *MI, MachineBasicBlock &CurBB,
}
static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB,
- SmallVectorImpl<unsigned> &UsedOpsInCopy,
- SmallVectorImpl<unsigned> &DefedRegsInCopy) {
+ const SmallVectorImpl<unsigned> &UsedOpsInCopy,
+ const SmallVectorImpl<Register> &DefedRegsInCopy) {
MachineFunction &MF = *SuccBB->getParent();
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- for (unsigned DefReg : DefedRegsInCopy)
+ for (Register DefReg : DefedRegsInCopy)
for (MCPhysReg S : TRI->subregs_inclusive(DefReg))
SuccBB->removeLiveIn(S);
for (auto U : UsedOpsInCopy)
@@ -2110,7 +2110,7 @@ static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB,
static bool hasRegisterDependency(MachineInstr *MI,
SmallVectorImpl<unsigned> &UsedOpsInCopy,
- SmallVectorImpl<unsigned> &DefedRegsInCopy,
+ SmallVectorImpl<Register> &DefedRegsInCopy,
LiveRegUnits &ModifiedRegUnits,
LiveRegUnits &UsedRegUnits) {
bool HasRegDependency = false;
@@ -2170,12 +2170,12 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
// Track the operand index for use in Copy.
SmallVector<unsigned, 2> UsedOpsInCopy;
// Track the register number defed in Copy.
- SmallVector<unsigned, 2> DefedRegsInCopy;
+ SmallVector<Register, 2> DefedRegsInCopy;
// We must sink this DBG_VALUE if its operand is sunk. To avoid searching
// for DBG_VALUEs later, record them when they're encountered.
if (MI.isDebugValue() && !MI.isDebugRef()) {
- SmallDenseMap<MCRegister, SmallVector<unsigned, 2>, 4> MIUnits;
+ SmallDenseMap<MCRegUnit, SmallVector<Register, 2>, 4> MIUnits;
bool IsValid = true;
for (MachineOperand &MO : MI.debug_operands()) {
if (MO.isReg() && MO.getReg().isPhysical()) {
@@ -2242,7 +2242,7 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
for (MCRegUnit Unit : TRI->regunits(MO.getReg())) {
for (const auto &MIRegs : SeenDbgInstrs.lookup(Unit)) {
auto &Regs = DbgValsToSinkMap[MIRegs.first];
- for (unsigned Reg : MIRegs.second)
+ for (Register Reg : MIRegs.second)
Regs.push_back(Reg);
}
}
More information about the llvm-commits
mailing list