[llvm] [DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (PR #127083)
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 24 13:34:36 PST 2025
================
@@ -12497,6 +12501,54 @@ SDValue DAGCombiner::visitMHISTOGRAM(SDNode *N) {
return SDValue();
}
+SDValue DAGCombiner::visitPARTIAL_REDUCE_MLA(SDNode *N) {
+ // Makes PARTIAL_REDUCE_*MLA(Acc, MUL(ZEXT(MulOpLHS), ZEXT(MulOpRHS)),
+ // Splat(1)) into
+ // PARTIAL_REDUCE_UMLA(Acc, MulOpLHS, MulOpRHS).
+ // Makes PARTIAL_REDUCE_*MLA(Acc, MUL(SEXT(MulOpLHS), SEXT(MulOpRHS)),
+ // Splat(1)) into
+ // PARTIAL_REDUCE_SMLA(Acc, MulOpLHS, MulOpRHS).
+ SDLoc DL(N);
+
+ SDValue Op0 = N->getOperand(0);
+ SDValue Op1 = N->getOperand(1);
+
+ if (Op1->getOpcode() != ISD::MUL)
+ return SDValue();
+
+ APInt ConstantOne;
+ if (!ISD::isConstantSplatVector(N->getOperand(2).getNode(), ConstantOne) ||
+ !ConstantOne.isOne())
+ return SDValue();
----------------
sdesmalen-arm wrote:
This is not the same, `AllOnes` in this case means `~0`, not `1`.
https://github.com/llvm/llvm-project/pull/127083
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