[llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)

[Min-Yih Hsu via llvm-commits]

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@@ -157,20 +772,7 @@ std::vector<MCInst> ExegesisRISCVTarget::setRegTo(const MCSubtargetInfo &STI,
       return loadFPRegBits(STI, Reg, Value, RISCV::FMV_D_X);
     return loadFP64RegBits32(STI, Reg, Value);
   }
-  if (Reg == RISCV::FRM || Reg == RISCV::VL || Reg == RISCV::VLENB ||
-      Reg == RISCV::VTYPE || RISCV::GPRPairRegClass.contains(Reg) ||
-      RISCV::VRRegClass.contains(Reg) || isVectorRegList(Reg)) {
-    // Don't initialize:
-    // - FRM
-    // - VL, VLENB, VTYPE
-    // - vector registers (and vector register lists)
-    // - Zfinx registers
-    // Generate 'NOP' so that exegesis treats such registers as initialized
-    // (it tries to initialize them with '0' anyway).
-    return {nop()};
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mshockwave wrote:

The problem of using NOPs here is that if these registers are considered initialized, Exegesis would start to track liveness on the MachineFunction. But we don't have proper code to actually initialize these registers, so MachineVerifier would complain about using uninitialized registers.

It's a lot easier to just leave these registers uninitialized for now.

https://github.com/llvm/llvm-project/pull/128767