[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

Hi @paulwalker-arm, it seems that doing this in AArch64LoadStoreOpt won't be a walk in the park as by the time we reach the pass, when compiling with `-msve-vector-bits=128`, it's likely the loads/stores will consist of a mix of LDRs+LD1s/STRs+ST1s as seen [here](https://godbolt.org/z/f3eY9jhGs). We could potentially lower the LD1s/ST1s into LDR/STR before combining them into LDP/STP. Do you think this would be preferable to the current implementation?

https://github.com/llvm/llvm-project/pull/127500