[llvm] [AMDGPU] Merge consecutive wait_alu instruction (PR #128916)

[Carl Ritson via llvm-commits]

================
@@ -164,6 +164,21 @@ class AMDGPUWaitSGPRHazards {
       BuildMI(MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::DS_NOP));
   }
 
+  unsigned mergeMasks(unsigned Mask1, unsigned Mask2) {
+    unsigned Mask = Mask1 & Mask2;
----------------
perlfu wrote:

Need a comment to document why an AND operation here is appropriate.
I can reason that it is safe; however, I think using this method is embedded an implicit assumption that SaSdst and VaVcc are single bits when these should be handled like other fields below (i.e. using encode and decode).
Specifically comment needs to explain why the AND is safe for any undefined/undocumented bits in the mask.
Alternatively this function should fail gracefully for bits it doesn't explicit handle.

https://github.com/llvm/llvm-project/pull/128916