[llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (NFCI) (PR #113903)

[Elvis Wang via llvm-commits]

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@@ -1204,10 +1234,17 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
            "opcode of underlying cast doesn't match");
   }
 
-  VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy)
-      : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op), Opcode(Opcode),
+  VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
+                    DebugLoc DL = {})
+      : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op, DL), Opcode(Opcode),
         ResultTy(ResultTy) {}
 
+  VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
+                    bool IsNonNeg, DebugLoc DL = {})
+      : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op, NonNegFlagsTy(IsNonNeg),
+                            DL),
+        Opcode(Opcode), ResultTy(ResultTy) {}
+
----------------
ElvisWang123 wrote:

It could be split off but it's hard to test it through input IR with `nneg` flags.

Currently all the VPWidenCastRecipes  contains `nneg` flags are directly constructed from the scalar IR.
When constructing VPWidenCastRecipe with input IR, `VPRecipeWithIRFlags` will automatically assign the corresponding flags. 

But when expanding VPMulAccReductionRecipe and VPExtendedReductionRecipes, we already drop the underlying IR for the cast instructions. So we need to pass `nneg` flags to the VPWIdenCastRecipe.


https://github.com/llvm/llvm-project/pull/113903