[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

> I think it would be worth "uplifting" these offsets back into multiples of VL, such that they could be folded into immediate-VL-based loads/stores, though I'm not sure where would be the best place to do this. Do you think this is worth trying, probably independently from this PR?

I've thought the same but it always felt tricky to pull off properly.  The last time I looked at it I wondered whether it could be handling entirely during isel via complex patterns.  I hesitated because I worried it could cause significant noise and make it harder for machine passes that attempt to analyse/merge offsets.  This could be ill founded but with no performance based motivation I figured I'll just ignore it for now.  Feel free to investigate this yourself but for my money I think you'll be better off just pushing this PR through and moving on until analysis shows a genuine need to look deeper.

I'll caveat this by saying despite implementing the feature the whole `-msve-vector-bits` has never sat well with me, although I do appreciate that when maximum performance is required the ideals of scalable vectors becomes secondary :) 


https://github.com/llvm/llvm-project/pull/127500