[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

> I haven't tried this yet as I wanted to limit this to the cases we knew we could fold to Neon LDR/STR to promote LDP/STP merging, though I think we could accomplish the same thing with an extra hook that would inspect the vector type and decide accordingly. Is that what you had in mind?

Oh sorry, for some reason I had it in head that the source of the loads/store would all be SVE intrinsics and thus you could extend `instCombineSVELD1`, but that's not always going to be the case.  Please ignore my suggestion.

https://github.com/llvm/llvm-project/pull/127500