[llvm] [PowerPC] custom lower v1024i1 load/store (PR #126969)

[Lei Huang via llvm-commits]

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@@ -1363,6 +1363,11 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
     setOperationAction(ISD::STORE, MVT::v512i1, Custom);
     setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom);
   }
+  if (Subtarget.isISAFuture()) {
+    setOperationAction(ISD::LOAD, MVT::v1024i1, Custom);
+    setOperationAction(ISD::STORE, MVT::v1024i1, Custom);
+    addRegisterClass(MVT::v1024i1, &PPC::DMRRCRegClass);
+  }
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lei137 wrote:

Yes Power11 implies hasMMA.  I was more thinking of issues where users manually turn on/off features on a specific CPU.  This patch uses `lxvp|stvp`, so if user explicitly turn off `mma` or  `paired-vector-memops` we shouldn't be generating these code. 

https://github.com/llvm/llvm-project/pull/126969