[llvm] [InstCombine] recognize missed i128 split optimization (PR #129363)

[Muhammad Bassiouni via llvm-commits]

https://github.com/bassiounix updated https://github.com/llvm/llvm-project/pull/129363

>From eb3a1f15d0ffee624ed87d9f496c0c3ed2f8e27f Mon Sep 17 00:00:00 2001
From: bassiounix <muhammad.m.bassiouni at gmail.com>
Date: Sat, 1 Mar 2025 07:24:38 +0200
Subject: [PATCH 1/3] [InstCombine] recognize missed i128 split optimization

---
 llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 175c653f17f07..cff95338650f2 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -3119,6 +3119,13 @@ static Value *matchOrConcat(Instruction &Or, InstCombiner::BuilderTy &Builder) {
       match(UpperSrc, m_BitReverse(m_Value(UpperBRev))))
     return ConcatIntrinsicCalls(Intrinsic::bitreverse, UpperBRev, LowerBRev);
 
+  Value *X;
+  if (match(LowerSrc, m_SExt(m_Value(X))) &&
+      match(UpperSrc,
+            m_SExt(m_AShr(m_Specific(X), m_SpecificInt(HalfWidth / 2 - 1))))) {
+    return Builder.CreateSExt(X, Ty);
+  }
+
   return nullptr;
 }
 

>From 5e37f325ec097084868450d92285dcf2f252291a Mon Sep 17 00:00:00 2001
From: bassiounix <muhammad.m.bassiouni at gmail.com>
Date: Sun, 2 Mar 2025 00:26:51 +0200
Subject: [PATCH 2/3] fix: update pattern constant source

---
 llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index cff95338650f2..b5a2c5df7b4ce 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -3122,7 +3122,9 @@ static Value *matchOrConcat(Instruction &Or, InstCombiner::BuilderTy &Builder) {
   Value *X;
   if (match(LowerSrc, m_SExt(m_Value(X))) &&
       match(UpperSrc,
-            m_SExt(m_AShr(m_Specific(X), m_SpecificInt(HalfWidth / 2 - 1))))) {
+            m_SExt(m_AShr(
+                m_Specific(X),
+                m_SpecificInt(X->getType()->getScalarSizeInBits() - 1))))) {
     return Builder.CreateSExt(X, Ty);
   }
 

>From 899c8d559a388b6034bbbf3eb109516bcfc6863b Mon Sep 17 00:00:00 2001
From: bassiounix <muhammad.m.bassiouni at gmail.com>
Date: Sun, 2 Mar 2025 01:20:03 +0200
Subject: [PATCH 3/3] add(InstCombine): tests for the ext optimization

---
 .../Transforms/InstCombine/i128-ext-split.ll  | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 llvm/test/Transforms/InstCombine/i128-ext-split.ll

diff --git a/llvm/test/Transforms/InstCombine/i128-ext-split.ll b/llvm/test/Transforms/InstCombine/i128-ext-split.ll
new file mode 100644
index 0000000000000..05d5deb8f7eb9
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/i128-ext-split.ll
@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+; PR129363
+
+define i128 @i128_ext_split(i32 noundef %x) {
+; CHECK-LABEL: define i128 @i128_ext_split(
+; CHECK-SAME: i32 noundef [[X:%.*]]) {
+; CHECK-NEXT:    [[XX:%.*]] = sext i32 [[X]] to i128
+; CHECK-NEXT:    ret i128 [[XX]]
+;
+  %coerce.sroa.0.0.extract.trunc = sext i32 %x to i64
+  %ashr = ashr i32 %x, 31
+  %coerce.sroa.2.0.extract.trunc = sext i32 %ashr to i64
+  %x.sroa.2.0.insert.ext.i = zext i64 %coerce.sroa.2.0.extract.trunc to i128
+  %x.sroa.2.0.insert.shift.i = shl nuw i128 %x.sroa.2.0.insert.ext.i, 64
+  %x.sroa.0.0.insert.ext.i = zext i64 %coerce.sroa.0.0.extract.trunc to i128
+  %x.sroa.0.0.insert.insert.i = or disjoint i128 %x.sroa.2.0.insert.shift.i, %x.sroa.0.0.insert.ext.i
+  ret i128 %x.sroa.0.0.insert.insert.i
+}
+
+define void @i128_ext_split_store(i32 %x, ptr %out)  {
+; CHECK-LABEL: define void @i128_ext_split_store(
+; CHECK-SAME: i32 [[X:%.*]], ptr [[OUT:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[RES:%.*]] = sext i32 [[X]] to i128
+; CHECK-NEXT:    store i128 [[RES]], ptr [[OUT]], align 16
+; CHECK-NEXT:    ret void
+;
+entry:
+  %LowerSrc = sext i32 %x to i64
+  %lo = zext i64 %LowerSrc to i128
+
+  %sign = ashr i32 %x, 31
+  %UpperSrc = sext i32 %sign to i64
+  %widen = zext i64 %UpperSrc to i128
+  %hi = shl nuw i128 %widen, 64
+
+  %res = or disjoint i128 %hi, %lo
+  store i128 %res, ptr %out, align 16
+  ret void
+}