[llvm] 6f2345a - [LLVM][AArch64] Change SVE CodeGen tests to use splat().
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 26 03:14:40 PST 2025
Author: Paul Walker
Date: 2025-02-26T11:11:02Z
New Revision: 6f2345a20e361c7748578b0c3bae37589989e3b8
URL: https://github.com/llvm/llvm-project/commit/6f2345a20e361c7748578b0c3bae37589989e3b8
DIFF: https://github.com/llvm/llvm-project/commit/6f2345a20e361c7748578b0c3bae37589989e3b8.diff
LOG: [LLVM][AArch64] Change SVE CodeGen tests to use splat().
The affected tests were using the longwinded syntax for constant
splats. By using the splat() syntax the tests get simplified whilst
also removing the need for "undef".
Added:
Modified:
llvm/test/CodeGen/AArch64/pr49781.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
llvm/test/CodeGen/AArch64/sve-gep.ll
llvm/test/CodeGen/AArch64/sve-int-log.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/pr49781.ll b/llvm/test/CodeGen/AArch64/pr49781.ll
index 066feda599d2e..ae950f0d279c5 100644
--- a/llvm/test/CodeGen/AArch64/pr49781.ll
+++ b/llvm/test/CodeGen/AArch64/pr49781.ll
@@ -6,8 +6,7 @@ define <vscale x 2 x i64> @foo(<vscale x 2 x i64> %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.d, z0.d, #2 // =0x2
; CHECK-NEXT: ret
- %idx = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %b = sub <vscale x 2 x i64> %a, %idx
- %c = sub <vscale x 2 x i64> %b, %idx
+ %b = sub <vscale x 2 x i64> %a, splat (i64 1)
+ %c = sub <vscale x 2 x i64> %b, splat (i64 1)
ret <vscale x 2 x i64> %c
}
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
index 53b56d6430b60..572759211fc1c 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
@@ -20,9 +20,7 @@ define void @add_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = add <64 x i8> %op1, %op2
+ %res = add <64 x i8> %op1, splat (i8 7)
store <64 x i8> %res, ptr %a
ret void
}
@@ -36,9 +34,7 @@ define void @add_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = add <32 x i16> %op1, %op2
+ %res = add <32 x i16> %op1, splat (i16 15)
store <32 x i16> %res, ptr %a
ret void
}
@@ -52,9 +48,7 @@ define void @add_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = add <16 x i32> %op1, %op2
+ %res = add <16 x i32> %op1, splat (i32 31)
store <16 x i32> %res, ptr %a
ret void
}
@@ -68,9 +62,7 @@ define void @add_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = add <8 x i64> %op1, %op2
+ %res = add <8 x i64> %op1, splat (i64 63)
store <8 x i64> %res, ptr %a
ret void
}
@@ -88,9 +80,7 @@ define void @and_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = and <64 x i8> %op1, %op2
+ %res = and <64 x i8> %op1, splat (i8 7)
store <64 x i8> %res, ptr %a
ret void
}
@@ -104,9 +94,7 @@ define void @and_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = and <32 x i16> %op1, %op2
+ %res = and <32 x i16> %op1, splat (i16 15)
store <32 x i16> %res, ptr %a
ret void
}
@@ -120,9 +108,7 @@ define void @and_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = and <16 x i32> %op1, %op2
+ %res = and <16 x i32> %op1, splat (i32 31)
store <16 x i32> %res, ptr %a
ret void
}
@@ -136,9 +122,7 @@ define void @and_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = and <8 x i64> %op1, %op2
+ %res = and <8 x i64> %op1, splat (i64 63)
store <8 x i64> %res, ptr %a
ret void
}
@@ -156,9 +140,7 @@ define void @ashr_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = ashr <64 x i8> %op1, %op2
+ %res = ashr <64 x i8> %op1, splat (i8 7)
store <64 x i8> %res, ptr %a
ret void
}
@@ -172,9 +154,7 @@ define void @ashr_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = ashr <32 x i16> %op1, %op2
+ %res = ashr <32 x i16> %op1, splat (i16 15)
store <32 x i16> %res, ptr %a
ret void
}
@@ -188,9 +168,7 @@ define void @ashr_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = ashr <16 x i32> %op1, %op2
+ %res = ashr <16 x i32> %op1, splat (i32 31)
store <16 x i32> %res, ptr %a
ret void
}
@@ -204,9 +182,7 @@ define void @ashr_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = ashr <8 x i64> %op1, %op2
+ %res = ashr <8 x i64> %op1, splat (i64 63)
store <8 x i64> %res, ptr %a
ret void
}
@@ -225,9 +201,7 @@ define void @icmp_eq_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %cmp = icmp eq <64 x i8> %op1, %op2
+ %cmp = icmp eq <64 x i8> %op1, splat (i8 7)
%res = sext <64 x i1> %cmp to <64 x i8>
store <64 x i8> %res, ptr %a
ret void
@@ -243,9 +217,7 @@ define void @icmp_sge_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %cmp = icmp sge <32 x i16> %op1, %op2
+ %cmp = icmp sge <32 x i16> %op1, splat (i16 15)
%res = sext <32 x i1> %cmp to <32 x i16>
store <32 x i16> %res, ptr %a
ret void
@@ -261,9 +233,7 @@ define void @icmp_sgt_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 -16, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %cmp = icmp sgt <16 x i32> %op1, %op2
+ %cmp = icmp sgt <16 x i32> %op1, splat (i32 -16)
%res = sext <16 x i1> %cmp to <16 x i32>
store <16 x i32> %res, ptr %a
ret void
@@ -279,9 +249,7 @@ define void @icmp_ult_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %cmp = icmp ult <8 x i64> %op1, %op2
+ %cmp = icmp ult <8 x i64> %op1, splat (i64 63)
%res = sext <8 x i1> %cmp to <8 x i64>
store <8 x i64> %res, ptr %a
ret void
@@ -300,9 +268,7 @@ define void @lshr_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = lshr <64 x i8> %op1, %op2
+ %res = lshr <64 x i8> %op1, splat (i8 7)
store <64 x i8> %res, ptr %a
ret void
}
@@ -316,9 +282,7 @@ define void @lshr_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = lshr <32 x i16> %op1, %op2
+ %res = lshr <32 x i16> %op1, splat (i16 15)
store <32 x i16> %res, ptr %a
ret void
}
@@ -332,9 +296,7 @@ define void @lshr_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = lshr <16 x i32> %op1, %op2
+ %res = lshr <16 x i32> %op1, splat (i32 31)
store <16 x i32> %res, ptr %a
ret void
}
@@ -348,9 +310,7 @@ define void @lshr_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = lshr <8 x i64> %op1, %op2
+ %res = lshr <8 x i64> %op1, splat (i64 63)
store <8 x i64> %res, ptr %a
ret void
}
@@ -368,9 +328,7 @@ define void @mul_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = mul <64 x i8> %op1, %op2
+ %res = mul <64 x i8> %op1, splat (i8 7)
store <64 x i8> %res, ptr %a
ret void
}
@@ -384,9 +342,7 @@ define void @mul_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = mul <32 x i16> %op1, %op2
+ %res = mul <32 x i16> %op1, splat (i16 15)
store <32 x i16> %res, ptr %a
ret void
}
@@ -400,9 +356,7 @@ define void @mul_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = mul <16 x i32> %op1, %op2
+ %res = mul <16 x i32> %op1, splat (i32 31)
store <16 x i32> %res, ptr %a
ret void
}
@@ -416,9 +370,7 @@ define void @mul_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = mul <8 x i64> %op1, %op2
+ %res = mul <8 x i64> %op1, splat (i64 63)
store <8 x i64> %res, ptr %a
ret void
}
@@ -436,9 +388,7 @@ define void @or_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = or <64 x i8> %op1, %op2
+ %res = or <64 x i8> %op1, splat (i8 7)
store <64 x i8> %res, ptr %a
ret void
}
@@ -452,9 +402,7 @@ define void @or_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = or <32 x i16> %op1, %op2
+ %res = or <32 x i16> %op1, splat (i16 15)
store <32 x i16> %res, ptr %a
ret void
}
@@ -468,9 +416,7 @@ define void @or_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = or <16 x i32> %op1, %op2
+ %res = or <16 x i32> %op1, splat (i32 31)
store <16 x i32> %res, ptr %a
ret void
}
@@ -484,9 +430,7 @@ define void @or_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = or <8 x i64> %op1, %op2
+ %res = or <8 x i64> %op1, splat (i64 63)
store <8 x i64> %res, ptr %a
ret void
}
@@ -504,9 +448,7 @@ define void @shl_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = shl <64 x i8> %op1, %op2
+ %res = shl <64 x i8> %op1, splat (i8 7)
store <64 x i8> %res, ptr %a
ret void
}
@@ -520,9 +462,7 @@ define void @shl_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = shl <32 x i16> %op1, %op2
+ %res = shl <32 x i16> %op1, splat (i16 15)
store <32 x i16> %res, ptr %a
ret void
}
@@ -536,9 +476,7 @@ define void @shl_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = shl <16 x i32> %op1, %op2
+ %res = shl <16 x i32> %op1, splat (i32 31)
store <16 x i32> %res, ptr %a
ret void
}
@@ -552,9 +490,7 @@ define void @shl_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = shl <8 x i64> %op1, %op2
+ %res = shl <8 x i64> %op1, splat (i64 63)
store <8 x i64> %res, ptr %a
ret void
}
@@ -572,9 +508,7 @@ define void @smax_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = call <64 x i8> @llvm.smax.v64i8(<64 x i8> %op1, <64 x i8> %op2)
+ %res = call <64 x i8> @llvm.smax.v64i8(<64 x i8> %op1, <64 x i8> splat (i8 7))
store <64 x i8> %res, ptr %a
ret void
}
@@ -588,9 +522,7 @@ define void @smax_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = call <32 x i16> @llvm.smax.v32i16(<32 x i16> %op1, <32 x i16> %op2)
+ %res = call <32 x i16> @llvm.smax.v32i16(<32 x i16> %op1, <32 x i16> splat (i16 15))
store <32 x i16> %res, ptr %a
ret void
}
@@ -604,9 +536,7 @@ define void @smax_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %op1, <16 x i32> %op2)
+ %res = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %op1, <16 x i32> splat (i32 31))
store <16 x i32> %res, ptr %a
ret void
}
@@ -620,9 +550,7 @@ define void @smax_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = call <8 x i64> @llvm.smax.v8i64(<8 x i64> %op1, <8 x i64> %op2)
+ %res = call <8 x i64> @llvm.smax.v8i64(<8 x i64> %op1, <8 x i64> splat (i64 63))
store <8 x i64> %res, ptr %a
ret void
}
@@ -640,9 +568,7 @@ define void @smin_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = call <64 x i8> @llvm.smin.v64i8(<64 x i8> %op1, <64 x i8> %op2)
+ %res = call <64 x i8> @llvm.smin.v64i8(<64 x i8> %op1, <64 x i8> splat (i8 7))
store <64 x i8> %res, ptr %a
ret void
}
@@ -656,9 +582,7 @@ define void @smin_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = call <32 x i16> @llvm.smin.v32i16(<32 x i16> %op1, <32 x i16> %op2)
+ %res = call <32 x i16> @llvm.smin.v32i16(<32 x i16> %op1, <32 x i16> splat (i16 15))
store <32 x i16> %res, ptr %a
ret void
}
@@ -672,9 +596,7 @@ define void @smin_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = call <16 x i32> @llvm.smin.v16i32(<16 x i32> %op1, <16 x i32> %op2)
+ %res = call <16 x i32> @llvm.smin.v16i32(<16 x i32> %op1, <16 x i32> splat (i32 31))
store <16 x i32> %res, ptr %a
ret void
}
@@ -688,9 +610,7 @@ define void @smin_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = call <8 x i64> @llvm.smin.v8i64(<8 x i64> %op1, <8 x i64> %op2)
+ %res = call <8 x i64> @llvm.smin.v8i64(<8 x i64> %op1, <8 x i64> splat (i64 63))
store <8 x i64> %res, ptr %a
ret void
}
@@ -708,9 +628,7 @@ define void @sub_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = sub <64 x i8> %op1, %op2
+ %res = sub <64 x i8> %op1, splat (i8 7)
store <64 x i8> %res, ptr %a
ret void
}
@@ -724,9 +642,7 @@ define void @sub_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = sub <32 x i16> %op1, %op2
+ %res = sub <32 x i16> %op1, splat (i16 15)
store <32 x i16> %res, ptr %a
ret void
}
@@ -740,9 +656,7 @@ define void @sub_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = sub <16 x i32> %op1, %op2
+ %res = sub <16 x i32> %op1, splat (i32 31)
store <16 x i32> %res, ptr %a
ret void
}
@@ -756,9 +670,7 @@ define void @sub_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = sub <8 x i64> %op1, %op2
+ %res = sub <8 x i64> %op1, splat (i64 63)
store <8 x i64> %res, ptr %a
ret void
}
@@ -776,9 +688,7 @@ define void @umax_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = call <64 x i8> @llvm.umax.v64i8(<64 x i8> %op1, <64 x i8> %op2)
+ %res = call <64 x i8> @llvm.umax.v64i8(<64 x i8> %op1, <64 x i8> splat (i8 7))
store <64 x i8> %res, ptr %a
ret void
}
@@ -792,9 +702,7 @@ define void @umax_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = call <32 x i16> @llvm.umax.v32i16(<32 x i16> %op1, <32 x i16> %op2)
+ %res = call <32 x i16> @llvm.umax.v32i16(<32 x i16> %op1, <32 x i16> splat (i16 15))
store <32 x i16> %res, ptr %a
ret void
}
@@ -808,9 +716,7 @@ define void @umax_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = call <16 x i32> @llvm.umax.v16i32(<16 x i32> %op1, <16 x i32> %op2)
+ %res = call <16 x i32> @llvm.umax.v16i32(<16 x i32> %op1, <16 x i32> splat (i32 31))
store <16 x i32> %res, ptr %a
ret void
}
@@ -824,9 +730,7 @@ define void @umax_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = call <8 x i64> @llvm.umax.v8i64(<8 x i64> %op1, <8 x i64> %op2)
+ %res = call <8 x i64> @llvm.umax.v8i64(<8 x i64> %op1, <8 x i64> splat (i64 63))
store <8 x i64> %res, ptr %a
ret void
}
@@ -844,9 +748,7 @@ define void @umin_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = call <64 x i8> @llvm.umin.v64i8(<64 x i8> %op1, <64 x i8> %op2)
+ %res = call <64 x i8> @llvm.umin.v64i8(<64 x i8> %op1, <64 x i8> splat (i8 7))
store <64 x i8> %res, ptr %a
ret void
}
@@ -860,9 +762,7 @@ define void @umin_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = call <32 x i16> @llvm.umin.v32i16(<32 x i16> %op1, <32 x i16> %op2)
+ %res = call <32 x i16> @llvm.umin.v32i16(<32 x i16> %op1, <32 x i16> splat (i16 15))
store <32 x i16> %res, ptr %a
ret void
}
@@ -876,9 +776,7 @@ define void @umin_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = call <16 x i32> @llvm.umin.v16i32(<16 x i32> %op1, <16 x i32> %op2)
+ %res = call <16 x i32> @llvm.umin.v16i32(<16 x i32> %op1, <16 x i32> splat (i32 31))
store <16 x i32> %res, ptr %a
ret void
}
@@ -892,9 +790,7 @@ define void @umin_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = call <8 x i64> @llvm.umin.v8i64(<8 x i64> %op1, <8 x i64> %op2)
+ %res = call <8 x i64> @llvm.umin.v8i64(<8 x i64> %op1, <8 x i64> splat (i64 63))
store <8 x i64> %res, ptr %a
ret void
}
@@ -912,9 +808,7 @@ define void @xor_v64i8(ptr %a) #0 {
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <64 x i8>, ptr %a
- %ins = insertelement <64 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <64 x i8> %ins, <64 x i8> undef, <64 x i32> zeroinitializer
- %res = xor <64 x i8> %op1, %op2
+ %res = xor <64 x i8> %op1, splat (i8 7)
store <64 x i8> %res, ptr %a
ret void
}
@@ -928,9 +822,7 @@ define void @xor_v32i16(ptr %a) #0 {
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i16>, ptr %a
- %ins = insertelement <32 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <32 x i16> %ins, <32 x i16> undef, <32 x i32> zeroinitializer
- %res = xor <32 x i16> %op1, %op2
+ %res = xor <32 x i16> %op1, splat (i16 15)
store <32 x i16> %res, ptr %a
ret void
}
@@ -944,9 +836,7 @@ define void @xor_v16i32(ptr %a) #0 {
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i32>, ptr %a
- %ins = insertelement <16 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <16 x i32> %ins, <16 x i32> undef, <16 x i32> zeroinitializer
- %res = xor <16 x i32> %op1, %op2
+ %res = xor <16 x i32> %op1, splat (i32 31)
store <16 x i32> %res, ptr %a
ret void
}
@@ -960,9 +850,7 @@ define void @xor_v8i64(ptr %a) #0 {
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i64>, ptr %a
- %ins = insertelement <8 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <8 x i64> %ins, <8 x i64> undef, <8 x i32> zeroinitializer
- %res = xor <8 x i64> %op1, %op2
+ %res = xor <8 x i64> %op1, splat (i64 63)
store <8 x i64> %res, ptr %a
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
index 331aab17a4cea..41cce354cc9de 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
@@ -22,12 +22,10 @@ define <8 x i8> @smulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {
; CHECK-NEXT: smulh z0.b, p0/m, z0.b, z1.b
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
- %insert = insertelement <8 x i16> undef, i16 8, i64 0
- %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
%1 = sext <8 x i8> %op1 to <8 x i16>
%2 = sext <8 x i8> %op2 to <8 x i16>
%mul = mul <8 x i16> %1, %2
- %shr = lshr <8 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <8 x i16> %mul, splat (i16 8)
%res = trunc <8 x i16> %shr to <8 x i8>
ret <8 x i8> %res
}
@@ -45,7 +43,7 @@ define <16 x i8> @smulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0)
%1 = sext <16 x i8> %op1 to <16 x i16>
%2 = sext <16 x i8> %op2 to <16 x i16>
%mul = mul <16 x i16> %1, %2
- %shr = lshr <16 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <16 x i16> %mul, splat (i16 8)
%res = trunc <16 x i16> %shr to <16 x i8>
ret <16 x i8> %res
}
@@ -64,7 +62,7 @@ define void @smulh_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {
%1 = sext <32 x i8> %op1 to <32 x i16>
%2 = sext <32 x i8> %op2 to <32 x i16>
%mul = mul <32 x i16> %1, %2
- %shr = lshr <32 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <32 x i16> %mul, splat (i16 8)
%res = trunc <32 x i16> %shr to <32 x i8>
store <32 x i8> %res, ptr %a
ret void
@@ -96,12 +94,10 @@ define void @smulh_v64i8(ptr %a, ptr %b) #0 {
; VBITS_GE_512-NEXT: ret
%op1 = load <64 x i8>, ptr %a
%op2 = load <64 x i8>, ptr %b
- %insert = insertelement <64 x i16> undef, i16 8, i64 0
- %splat = shufflevector <64 x i16> %insert, <64 x i16> undef, <64 x i32> zeroinitializer
%1 = sext <64 x i8> %op1 to <64 x i16>
%2 = sext <64 x i8> %op2 to <64 x i16>
%mul = mul <64 x i16> %1, %2
- %shr = lshr <64 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <64 x i16> %mul, splat (i16 8)
%res = trunc <64 x i16> %shr to <64 x i8>
store <64 x i8> %res, ptr %a
ret void
@@ -121,7 +117,7 @@ define void @smulh_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {
%1 = sext <128 x i8> %op1 to <128 x i16>
%2 = sext <128 x i8> %op2 to <128 x i16>
%mul = mul <128 x i16> %1, %2
- %shr = lshr <128 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <128 x i16> %mul, splat (i16 8)
%res = trunc <128 x i16> %shr to <128 x i8>
store <128 x i8> %res, ptr %a
ret void
@@ -141,7 +137,7 @@ define void @smulh_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {
%1 = sext <256 x i8> %op1 to <256 x i16>
%2 = sext <256 x i8> %op2 to <256 x i16>
%mul = mul <256 x i16> %1, %2
- %shr = lshr <256 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <256 x i16> %mul, splat (i16 8)
%res = trunc <256 x i16> %shr to <256 x i8>
store <256 x i8> %res, ptr %a
ret void
@@ -160,7 +156,7 @@ define <4 x i16> @smulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0)
%1 = sext <4 x i16> %op1 to <4 x i32>
%2 = sext <4 x i16> %op2 to <4 x i32>
%mul = mul <4 x i32> %1, %2
- %shr = lshr <4 x i32> %mul, <i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <4 x i32> %mul, splat (i32 16)
%res = trunc <4 x i32> %shr to <4 x i16>
ret <4 x i16> %res
}
@@ -178,7 +174,7 @@ define <8 x i16> @smulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0)
%1 = sext <8 x i16> %op1 to <8 x i32>
%2 = sext <8 x i16> %op2 to <8 x i32>
%mul = mul <8 x i32> %1, %2
- %shr = lshr <8 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <8 x i32> %mul, splat (i32 16)
%res = trunc <8 x i32> %shr to <8 x i16>
ret <8 x i16> %res
}
@@ -197,7 +193,7 @@ define void @smulh_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {
%1 = sext <16 x i16> %op1 to <16 x i32>
%2 = sext <16 x i16> %op2 to <16 x i32>
%mul = mul <16 x i32> %1, %2
- %shr = lshr <16 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <16 x i32> %mul, splat (i32 16)
%res = trunc <16 x i32> %shr to <16 x i16>
store <16 x i16> %res, ptr %a
ret void
@@ -232,7 +228,7 @@ define void @smulh_v32i16(ptr %a, ptr %b) #0 {
%1 = sext <32 x i16> %op1 to <32 x i32>
%2 = sext <32 x i16> %op2 to <32 x i32>
%mul = mul <32 x i32> %1, %2
- %shr = lshr <32 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <32 x i32> %mul, splat (i32 16)
%res = trunc <32 x i32> %shr to <32 x i16>
store <32 x i16> %res, ptr %a
ret void
@@ -252,7 +248,7 @@ define void @smulh_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {
%1 = sext <64 x i16> %op1 to <64 x i32>
%2 = sext <64 x i16> %op2 to <64 x i32>
%mul = mul <64 x i32> %1, %2
- %shr = lshr <64 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <64 x i32> %mul, splat (i32 16)
%res = trunc <64 x i32> %shr to <64 x i16>
store <64 x i16> %res, ptr %a
ret void
@@ -272,7 +268,7 @@ define void @smulh_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {
%1 = sext <128 x i16> %op1 to <128 x i32>
%2 = sext <128 x i16> %op2 to <128 x i32>
%mul = mul <128 x i32> %1, %2
- %shr = lshr <128 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <128 x i32> %mul, splat (i32 16)
%res = trunc <128 x i32> %shr to <128 x i16>
store <128 x i16> %res, ptr %a
ret void
@@ -291,7 +287,7 @@ define <2 x i32> @smulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0)
%1 = sext <2 x i32> %op1 to <2 x i64>
%2 = sext <2 x i32> %op2 to <2 x i64>
%mul = mul <2 x i64> %1, %2
- %shr = lshr <2 x i64> %mul, <i64 32, i64 32>
+ %shr = lshr <2 x i64> %mul, splat (i64 32)
%res = trunc <2 x i64> %shr to <2 x i32>
ret <2 x i32> %res
}
@@ -309,7 +305,7 @@ define <4 x i32> @smulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0)
%1 = sext <4 x i32> %op1 to <4 x i64>
%2 = sext <4 x i32> %op2 to <4 x i64>
%mul = mul <4 x i64> %1, %2
- %shr = lshr <4 x i64> %mul, <i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <4 x i64> %mul, splat (i64 32)
%res = trunc <4 x i64> %shr to <4 x i32>
ret <4 x i32> %res
}
@@ -328,7 +324,7 @@ define void @smulh_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {
%1 = sext <8 x i32> %op1 to <8 x i64>
%2 = sext <8 x i32> %op2 to <8 x i64>
%mul = mul <8 x i64> %1, %2
- %shr = lshr <8 x i64> %mul, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <8 x i64> %mul, splat (i64 32)
%res = trunc <8 x i64> %shr to <8 x i32>
store <8 x i32> %res, ptr %a
ret void
@@ -363,7 +359,7 @@ define void @smulh_v16i32(ptr %a, ptr %b) #0 {
%1 = sext <16 x i32> %op1 to <16 x i64>
%2 = sext <16 x i32> %op2 to <16 x i64>
%mul = mul <16 x i64> %1, %2
- %shr = lshr <16 x i64> %mul, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <16 x i64> %mul, splat (i64 32)
%res = trunc <16 x i64> %shr to <16 x i32>
store <16 x i32> %res, ptr %a
ret void
@@ -383,7 +379,7 @@ define void @smulh_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {
%1 = sext <32 x i32> %op1 to <32 x i64>
%2 = sext <32 x i32> %op2 to <32 x i64>
%mul = mul <32 x i64> %1, %2
- %shr = lshr <32 x i64> %mul, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <32 x i64> %mul, splat (i64 32)
%res = trunc <32 x i64> %shr to <32 x i32>
store <32 x i32> %res, ptr %a
ret void
@@ -403,7 +399,7 @@ define void @smulh_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {
%1 = sext <64 x i32> %op1 to <64 x i64>
%2 = sext <64 x i32> %op2 to <64 x i64>
%mul = mul <64 x i64> %1, %2
- %shr = lshr <64 x i64> %mul, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <64 x i64> %mul, splat (i64 32)
%res = trunc <64 x i64> %shr to <64 x i32>
store <64 x i32> %res, ptr %a
ret void
@@ -419,12 +415,10 @@ define <1 x i64> @smulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0)
; CHECK-NEXT: smulh z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
- %insert = insertelement <1 x i128> undef, i128 64, i128 0
- %splat = shufflevector <1 x i128> %insert, <1 x i128> undef, <1 x i32> zeroinitializer
%1 = sext <1 x i64> %op1 to <1 x i128>
%2 = sext <1 x i64> %op2 to <1 x i128>
%mul = mul <1 x i128> %1, %2
- %shr = lshr <1 x i128> %mul, %splat
+ %shr = lshr <1 x i128> %mul, splat (i128 64)
%res = trunc <1 x i128> %shr to <1 x i64>
ret <1 x i64> %res
}
@@ -442,7 +436,7 @@ define <2 x i64> @smulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0)
%1 = sext <2 x i64> %op1 to <2 x i128>
%2 = sext <2 x i64> %op2 to <2 x i128>
%mul = mul <2 x i128> %1, %2
- %shr = lshr <2 x i128> %mul, <i128 64, i128 64>
+ %shr = lshr <2 x i128> %mul, splat (i128 64)
%res = trunc <2 x i128> %shr to <2 x i64>
ret <2 x i64> %res
}
@@ -461,7 +455,7 @@ define void @smulh_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {
%1 = sext <4 x i64> %op1 to <4 x i128>
%2 = sext <4 x i64> %op2 to <4 x i128>
%mul = mul <4 x i128> %1, %2
- %shr = lshr <4 x i128> %mul, <i128 64, i128 64, i128 64, i128 64>
+ %shr = lshr <4 x i128> %mul, splat (i128 64)
%res = trunc <4 x i128> %shr to <4 x i64>
store <4 x i64> %res, ptr %a
ret void
@@ -496,7 +490,7 @@ define void @smulh_v8i64(ptr %a, ptr %b) #0 {
%1 = sext <8 x i64> %op1 to <8 x i128>
%2 = sext <8 x i64> %op2 to <8 x i128>
%mul = mul <8 x i128> %1, %2
- %shr = lshr <8 x i128> %mul, <i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64>
+ %shr = lshr <8 x i128> %mul, splat (i128 64)
%res = trunc <8 x i128> %shr to <8 x i64>
store <8 x i64> %res, ptr %a
ret void
@@ -516,7 +510,7 @@ define void @smulh_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {
%1 = sext <16 x i64> %op1 to <16 x i128>
%2 = sext <16 x i64> %op2 to <16 x i128>
%mul = mul <16 x i128> %1, %2
- %shr = lshr <16 x i128> %mul, <i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64>
+ %shr = lshr <16 x i128> %mul, splat (i128 64)
%res = trunc <16 x i128> %shr to <16 x i64>
store <16 x i64> %res, ptr %a
ret void
@@ -536,7 +530,7 @@ define void @smulh_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {
%1 = sext <32 x i64> %op1 to <32 x i128>
%2 = sext <32 x i64> %op2 to <32 x i128>
%mul = mul <32 x i128> %1, %2
- %shr = lshr <32 x i128> %mul, <i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64>
+ %shr = lshr <32 x i128> %mul, splat (i128 64)
%res = trunc <32 x i128> %shr to <32 x i64>
store <32 x i64> %res, ptr %a
ret void
@@ -560,7 +554,7 @@ define <8 x i8> @umulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 {
%1 = zext <8 x i8> %op1 to <8 x i16>
%2 = zext <8 x i8> %op2 to <8 x i16>
%mul = mul <8 x i16> %1, %2
- %shr = lshr <8 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <8 x i16> %mul, splat (i16 8)
%res = trunc <8 x i16> %shr to <8 x i8>
ret <8 x i8> %res
}
@@ -578,7 +572,7 @@ define <16 x i8> @umulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0)
%1 = zext <16 x i8> %op1 to <16 x i16>
%2 = zext <16 x i8> %op2 to <16 x i16>
%mul = mul <16 x i16> %1, %2
- %shr = lshr <16 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <16 x i16> %mul, splat (i16 8)
%res = trunc <16 x i16> %shr to <16 x i8>
ret <16 x i8> %res
}
@@ -597,7 +591,7 @@ define void @umulh_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {
%1 = zext <32 x i8> %op1 to <32 x i16>
%2 = zext <32 x i8> %op2 to <32 x i16>
%mul = mul <32 x i16> %1, %2
- %shr = lshr <32 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <32 x i16> %mul, splat (i16 8)
%res = trunc <32 x i16> %shr to <32 x i8>
store <32 x i8> %res, ptr %a
ret void
@@ -632,7 +626,7 @@ define void @umulh_v64i8(ptr %a, ptr %b) #0 {
%1 = zext <64 x i8> %op1 to <64 x i16>
%2 = zext <64 x i8> %op2 to <64 x i16>
%mul = mul <64 x i16> %1, %2
- %shr = lshr <64 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <64 x i16> %mul, splat (i16 8)
%res = trunc <64 x i16> %shr to <64 x i8>
store <64 x i8> %res, ptr %a
ret void
@@ -649,12 +643,10 @@ define void @umulh_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {
; CHECK-NEXT: ret
%op1 = load <128 x i8>, ptr %a
%op2 = load <128 x i8>, ptr %b
- %insert = insertelement <128 x i16> undef, i16 8, i64 0
- %splat = shufflevector <128 x i16> %insert, <128 x i16> undef, <128 x i32> zeroinitializer
%1 = zext <128 x i8> %op1 to <128 x i16>
%2 = zext <128 x i8> %op2 to <128 x i16>
%mul = mul <128 x i16> %1, %2
- %shr = lshr <128 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <128 x i16> %mul, splat (i16 8)
%res = trunc <128 x i16> %shr to <128 x i8>
store <128 x i8> %res, ptr %a
ret void
@@ -674,7 +666,7 @@ define void @umulh_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 {
%1 = zext <256 x i8> %op1 to <256 x i16>
%2 = zext <256 x i8> %op2 to <256 x i16>
%mul = mul <256 x i16> %1, %2
- %shr = lshr <256 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <256 x i16> %mul, splat (i16 8)
%res = trunc <256 x i16> %shr to <256 x i8>
store <256 x i8> %res, ptr %a
ret void
@@ -694,7 +686,7 @@ define <4 x i16> @umulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0)
%1 = zext <4 x i16> %op1 to <4 x i32>
%2 = zext <4 x i16> %op2 to <4 x i32>
%mul = mul <4 x i32> %1, %2
- %shr = lshr <4 x i32> %mul, <i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <4 x i32> %mul, splat (i32 16)
%res = trunc <4 x i32> %shr to <4 x i16>
ret <4 x i16> %res
}
@@ -712,7 +704,7 @@ define <8 x i16> @umulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0)
%1 = zext <8 x i16> %op1 to <8 x i32>
%2 = zext <8 x i16> %op2 to <8 x i32>
%mul = mul <8 x i32> %1, %2
- %shr = lshr <8 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <8 x i32> %mul, splat (i32 16)
%res = trunc <8 x i32> %shr to <8 x i16>
ret <8 x i16> %res
}
@@ -731,7 +723,7 @@ define void @umulh_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {
%1 = zext <16 x i16> %op1 to <16 x i32>
%2 = zext <16 x i16> %op2 to <16 x i32>
%mul = mul <16 x i32> %1, %2
- %shr = lshr <16 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <16 x i32> %mul, splat (i32 16)
%res = trunc <16 x i32> %shr to <16 x i16>
store <16 x i16> %res, ptr %a
ret void
@@ -766,7 +758,7 @@ define void @umulh_v32i16(ptr %a, ptr %b) #0 {
%1 = zext <32 x i16> %op1 to <32 x i32>
%2 = zext <32 x i16> %op2 to <32 x i32>
%mul = mul <32 x i32> %1, %2
- %shr = lshr <32 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <32 x i32> %mul, splat (i32 16)
%res = trunc <32 x i32> %shr to <32 x i16>
store <32 x i16> %res, ptr %a
ret void
@@ -786,7 +778,7 @@ define void @umulh_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {
%1 = zext <64 x i16> %op1 to <64 x i32>
%2 = zext <64 x i16> %op2 to <64 x i32>
%mul = mul <64 x i32> %1, %2
- %shr = lshr <64 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <64 x i32> %mul, splat (i32 16)
%res = trunc <64 x i32> %shr to <64 x i16>
store <64 x i16> %res, ptr %a
ret void
@@ -806,7 +798,7 @@ define void @umulh_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {
%1 = zext <128 x i16> %op1 to <128 x i32>
%2 = zext <128 x i16> %op2 to <128 x i32>
%mul = mul <128 x i32> %1, %2
- %shr = lshr <128 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <128 x i32> %mul, splat (i32 16)
%res = trunc <128 x i32> %shr to <128 x i16>
store <128 x i16> %res, ptr %a
ret void
@@ -825,7 +817,7 @@ define <2 x i32> @umulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0)
%1 = zext <2 x i32> %op1 to <2 x i64>
%2 = zext <2 x i32> %op2 to <2 x i64>
%mul = mul <2 x i64> %1, %2
- %shr = lshr <2 x i64> %mul, <i64 32, i64 32>
+ %shr = lshr <2 x i64> %mul, splat (i64 32)
%res = trunc <2 x i64> %shr to <2 x i32>
ret <2 x i32> %res
}
@@ -843,7 +835,7 @@ define <4 x i32> @umulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0)
%1 = zext <4 x i32> %op1 to <4 x i64>
%2 = zext <4 x i32> %op2 to <4 x i64>
%mul = mul <4 x i64> %1, %2
- %shr = lshr <4 x i64> %mul, <i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <4 x i64> %mul, splat (i64 32)
%res = trunc <4 x i64> %shr to <4 x i32>
ret <4 x i32> %res
}
@@ -859,12 +851,10 @@ define void @umulh_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {
; CHECK-NEXT: ret
%op1 = load <8 x i32>, ptr %a
%op2 = load <8 x i32>, ptr %b
- %insert = insertelement <8 x i64> undef, i64 32, i64 0
- %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
%1 = zext <8 x i32> %op1 to <8 x i64>
%2 = zext <8 x i32> %op2 to <8 x i64>
%mul = mul <8 x i64> %1, %2
- %shr = lshr <8 x i64> %mul, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <8 x i64> %mul, splat (i64 32)
%res = trunc <8 x i64> %shr to <8 x i32>
store <8 x i32> %res, ptr %a
ret void
@@ -899,7 +889,7 @@ define void @umulh_v16i32(ptr %a, ptr %b) #0 {
%1 = zext <16 x i32> %op1 to <16 x i64>
%2 = zext <16 x i32> %op2 to <16 x i64>
%mul = mul <16 x i64> %1, %2
- %shr = lshr <16 x i64> %mul, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <16 x i64> %mul, splat (i64 32)
%res = trunc <16 x i64> %shr to <16 x i32>
store <16 x i32> %res, ptr %a
ret void
@@ -919,7 +909,7 @@ define void @umulh_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {
%1 = zext <32 x i32> %op1 to <32 x i64>
%2 = zext <32 x i32> %op2 to <32 x i64>
%mul = mul <32 x i64> %1, %2
- %shr = lshr <32 x i64> %mul, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <32 x i64> %mul, splat (i64 32)
%res = trunc <32 x i64> %shr to <32 x i32>
store <32 x i32> %res, ptr %a
ret void
@@ -939,7 +929,7 @@ define void @umulh_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {
%1 = zext <64 x i32> %op1 to <64 x i64>
%2 = zext <64 x i32> %op2 to <64 x i64>
%mul = mul <64 x i64> %1, %2
- %shr = lshr <64 x i64> %mul, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <64 x i64> %mul, splat (i64 32)
%res = trunc <64 x i64> %shr to <64 x i32>
store <64 x i32> %res, ptr %a
ret void
@@ -958,7 +948,7 @@ define <1 x i64> @umulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) vscale_range(2,0)
%1 = zext <1 x i64> %op1 to <1 x i128>
%2 = zext <1 x i64> %op2 to <1 x i128>
%mul = mul <1 x i128> %1, %2
- %shr = lshr <1 x i128> %mul, <i128 64>
+ %shr = lshr <1 x i128> %mul, splat (i128 64)
%res = trunc <1 x i128> %shr to <1 x i64>
ret <1 x i64> %res
}
@@ -976,7 +966,7 @@ define <2 x i64> @umulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0)
%1 = zext <2 x i64> %op1 to <2 x i128>
%2 = zext <2 x i64> %op2 to <2 x i128>
%mul = mul <2 x i128> %1, %2
- %shr = lshr <2 x i128> %mul, <i128 64, i128 64>
+ %shr = lshr <2 x i128> %mul, splat (i128 64)
%res = trunc <2 x i128> %shr to <2 x i64>
ret <2 x i64> %res
}
@@ -995,7 +985,7 @@ define void @umulh_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {
%1 = zext <4 x i64> %op1 to <4 x i128>
%2 = zext <4 x i64> %op2 to <4 x i128>
%mul = mul <4 x i128> %1, %2
- %shr = lshr <4 x i128> %mul, <i128 64, i128 64, i128 64, i128 64>
+ %shr = lshr <4 x i128> %mul, splat (i128 64)
%res = trunc <4 x i128> %shr to <4 x i64>
store <4 x i64> %res, ptr %a
ret void
@@ -1030,7 +1020,7 @@ define void @umulh_v8i64(ptr %a, ptr %b) #0 {
%1 = zext <8 x i64> %op1 to <8 x i128>
%2 = zext <8 x i64> %op2 to <8 x i128>
%mul = mul <8 x i128> %1, %2
- %shr = lshr <8 x i128> %mul, <i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64>
+ %shr = lshr <8 x i128> %mul, splat (i128 64)
%res = trunc <8 x i128> %shr to <8 x i64>
store <8 x i64> %res, ptr %a
ret void
@@ -1050,7 +1040,7 @@ define void @umulh_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {
%1 = zext <16 x i64> %op1 to <16 x i128>
%2 = zext <16 x i64> %op2 to <16 x i128>
%mul = mul <16 x i128> %1, %2
- %shr = lshr <16 x i128> %mul, <i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64>
+ %shr = lshr <16 x i128> %mul, splat (i128 64)
%res = trunc <16 x i128> %shr to <16 x i64>
store <16 x i64> %res, ptr %a
ret void
@@ -1070,7 +1060,7 @@ define void @umulh_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {
%1 = zext <32 x i64> %op1 to <32 x i128>
%2 = zext <32 x i64> %op2 to <32 x i128>
%mul = mul <32 x i128> %1, %2
- %shr = lshr <32 x i128> %mul, <i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64, i128 64>
+ %shr = lshr <32 x i128> %mul, splat (i128 64)
%res = trunc <32 x i128> %shr to <32 x i64>
store <32 x i64> %res, ptr %a
ret void
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
index b633057be139c..2b72d46adb8d4 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
@@ -624,9 +624,7 @@ define void @splat_imm_v64i8(ptr %a) vscale_range(4,0) #0 {
; CHECK-NEXT: ptrue p0.b, vl64
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: ret
- %insert = insertelement <64 x i8> undef, i8 1, i64 0
- %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
- store <64 x i8> %splat, ptr %a
+ store <64 x i8> splat (i8 1), ptr %a
ret void
}
@@ -637,9 +635,7 @@ define void @splat_imm_v32i16(ptr %a) vscale_range(4,0) #0 {
; CHECK-NEXT: ptrue p0.h, vl32
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
- %insert = insertelement <32 x i16> undef, i16 2, i64 0
- %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
- store <32 x i16> %splat, ptr %a
+ store <32 x i16> splat (i16 2), ptr %a
ret void
}
@@ -650,9 +646,7 @@ define void @splat_imm_v16i32(ptr %a) vscale_range(4,0) #0 {
; CHECK-NEXT: ptrue p0.s, vl16
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
- %insert = insertelement <16 x i32> undef, i32 3, i64 0
- %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
- store <16 x i32> %splat, ptr %a
+ store <16 x i32> splat (i32 3), ptr %a
ret void
}
@@ -663,9 +657,7 @@ define void @splat_imm_v8i64(ptr %a) vscale_range(4,0) #0 {
; CHECK-NEXT: ptrue p0.d, vl8
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
- %insert = insertelement <8 x i64> undef, i64 4, i64 0
- %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
- store <8 x i64> %splat, ptr %a
+ store <8 x i64> splat (i64 4), ptr %a
ret void
}
@@ -680,9 +672,7 @@ define void @splat_imm_v32f16(ptr %a) vscale_range(4,0) #0 {
; CHECK-NEXT: ptrue p0.h, vl32
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: ret
- %insert = insertelement <32 x half> undef, half 5.0, i64 0
- %splat = shufflevector <32 x half> %insert, <32 x half> undef, <32 x i32> zeroinitializer
- store <32 x half> %splat, ptr %a
+ store <32 x half> splat (half 5.0), ptr %a
ret void
}
@@ -693,9 +683,7 @@ define void @splat_imm_v16f32(ptr %a) vscale_range(4,0) #0 {
; CHECK-NEXT: ptrue p0.s, vl16
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: ret
- %insert = insertelement <16 x float> undef, float 6.0, i64 0
- %splat = shufflevector <16 x float> %insert, <16 x float> undef, <16 x i32> zeroinitializer
- store <16 x float> %splat, ptr %a
+ store <16 x float> splat (float 6.0), ptr %a
ret void
}
@@ -706,9 +694,7 @@ define void @splat_imm_v8f64(ptr %a) vscale_range(4,0) #0 {
; CHECK-NEXT: ptrue p0.d, vl8
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
- %insert = insertelement <8 x double> undef, double 7.0, i64 0
- %splat = shufflevector <8 x double> %insert, <8 x double> undef, <8 x i32> zeroinitializer
- store <8 x double> %splat, ptr %a
+ store <8 x double> splat (double 7.0), ptr %a
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/sve-gep.ll b/llvm/test/CodeGen/AArch64/sve-gep.ll
index 61ef740a722e9..e60a3e4bf9fb2 100644
--- a/llvm/test/CodeGen/AArch64/sve-gep.ll
+++ b/llvm/test/CodeGen/AArch64/sve-gep.ll
@@ -60,8 +60,7 @@ define <vscale x 2 x ptr> @scalable_of_fixed_1(ptr %base) {
; CHECK-NEXT: add x8, x0, #1
; CHECK-NEXT: mov z0.d, x8
; CHECK-NEXT: ret
- %idx = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %d = getelementptr i8, ptr %base, <vscale x 2 x i64> %idx
+ %d = getelementptr i8, ptr %base, <vscale x 2 x i64> splat (i64 1)
ret <vscale x 2 x ptr> %d
}
@@ -70,8 +69,7 @@ define <vscale x 2 x ptr> @scalable_of_fixed_2(<vscale x 2 x ptr> %base) {
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.d, z0.d, #1 // =0x1
; CHECK-NEXT: ret
- %idx = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %d = getelementptr i8, <vscale x 2 x ptr> %base, <vscale x 2 x i64> %idx
+ %d = getelementptr i8, <vscale x 2 x ptr> %base, <vscale x 2 x i64> splat (i64 1)
ret <vscale x 2 x ptr> %d
}
@@ -207,8 +205,7 @@ define <vscale x 2 x ptr> @scalable_of_scalable_1(ptr %base) {
; CHECK-NEXT: add x8, x0, x8
; CHECK-NEXT: mov z0.d, x8
; CHECK-NEXT: ret
- %idx = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %d = getelementptr <vscale x 2 x i64>, ptr %base, <vscale x 2 x i64> %idx
+ %d = getelementptr <vscale x 2 x i64>, ptr %base, <vscale x 2 x i64> splat (i64 1)
ret <vscale x 2 x ptr> %d
}
@@ -217,8 +214,7 @@ define <vscale x 2 x ptr> @scalable_of_scalable_2(<vscale x 2 x ptr> %base) {
; CHECK: // %bb.0:
; CHECK-NEXT: incd z0.d, all, mul #8
; CHECK-NEXT: ret
- %idx = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %d = getelementptr <vscale x 2 x i64>, <vscale x 2 x ptr> %base, <vscale x 2 x i64> %idx
+ %d = getelementptr <vscale x 2 x i64>, <vscale x 2 x ptr> %base, <vscale x 2 x i64> splat (i64 1)
ret <vscale x 2 x ptr> %d
}
diff --git a/llvm/test/CodeGen/AArch64/sve-int-log.ll b/llvm/test/CodeGen/AArch64/sve-int-log.ll
index 2031a3a9eeb3c..c45d0f437760f 100644
--- a/llvm/test/CodeGen/AArch64/sve-int-log.ll
+++ b/llvm/test/CodeGen/AArch64/sve-int-log.ll
@@ -96,8 +96,7 @@ define <vscale x 2 x i64> @bic_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: bic z0.d, z0.d, z1.d
; CHECK-NEXT: ret
- %allones = shufflevector <vscale x 2 x i64> insertelement(<vscale x 2 x i64> undef, i64 -1, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
- %not_b = xor <vscale x 2 x i64> %b, %allones
+ %not_b = xor <vscale x 2 x i64> %b, splat (i64 -1)
%res = and <vscale x 2 x i64> %a, %not_b
ret <vscale x 2 x i64> %res
}
@@ -107,8 +106,7 @@ define <vscale x 4 x i32> @bic_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: bic z0.d, z0.d, z1.d
; CHECK-NEXT: ret
- %allones = shufflevector <vscale x 4 x i32> insertelement(<vscale x 4 x i32> undef, i32 -1, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
- %not_b = xor <vscale x 4 x i32> %b, %allones
+ %not_b = xor <vscale x 4 x i32> %b, splat (i32 -1)
%res = and <vscale x 4 x i32> %a, %not_b
ret <vscale x 4 x i32> %res
}
@@ -118,8 +116,7 @@ define <vscale x 8 x i16> @bic_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: bic z0.d, z0.d, z1.d
; CHECK-NEXT: ret
- %allones = shufflevector <vscale x 8 x i16> insertelement(<vscale x 8 x i16> undef, i16 -1, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
- %not_b = xor <vscale x 8 x i16> %b, %allones
+ %not_b = xor <vscale x 8 x i16> %b, splat (i16 -1)
%res = and <vscale x 8 x i16> %a, %not_b
ret <vscale x 8 x i16> %res
}
@@ -129,8 +126,7 @@ define <vscale x 16 x i8> @bic_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: bic z0.d, z0.d, z1.d
; CHECK-NEXT: ret
- %allones = shufflevector <vscale x 16 x i8> insertelement(<vscale x 16 x i8> undef, i8 -1, i32 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
- %not_b = xor <vscale x 16 x i8> %b, %allones
+ %not_b = xor <vscale x 16 x i8> %b, splat (i8 -1)
%res = and <vscale x 16 x i8> %a, %not_b
ret <vscale x 16 x i8> %res
}
@@ -140,8 +136,7 @@ define <vscale x 1 x i1> @bic_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b)
; CHECK: // %bb.0:
; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
- %allones = shufflevector <vscale x 1 x i1> insertelement(<vscale x 1 x i1> undef, i1 true, i32 0), <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
- %not_b = xor <vscale x 1 x i1> %b, %allones
+ %not_b = xor <vscale x 1 x i1> %b, splat (i1 true)
%res = and <vscale x 1 x i1> %a, %not_b
ret <vscale x 1 x i1> %res
}
@@ -151,8 +146,7 @@ define <vscale x 2 x i1> @bic_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b)
; CHECK: // %bb.0:
; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
- %allones = shufflevector <vscale x 2 x i1> insertelement(<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
- %not_b = xor <vscale x 2 x i1> %b, %allones
+ %not_b = xor <vscale x 2 x i1> %b, splat (i1 true)
%res = and <vscale x 2 x i1> %a, %not_b
ret <vscale x 2 x i1> %res
}
@@ -162,8 +156,7 @@ define <vscale x 4 x i1> @bic_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b)
; CHECK: // %bb.0:
; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
- %allones = shufflevector <vscale x 4 x i1> insertelement(<vscale x 4 x i1> undef, i1 true, i32 0), <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
- %not_b = xor <vscale x 4 x i1> %b, %allones
+ %not_b = xor <vscale x 4 x i1> %b, splat (i1 true)
%res = and <vscale x 4 x i1> %a, %not_b
ret <vscale x 4 x i1> %res
}
@@ -173,8 +166,7 @@ define <vscale x 8 x i1> @bic_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b)
; CHECK: // %bb.0:
; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
- %allones = shufflevector <vscale x 8 x i1> insertelement(<vscale x 8 x i1> undef, i1 true, i32 0), <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
- %not_b = xor <vscale x 8 x i1> %b, %allones
+ %not_b = xor <vscale x 8 x i1> %b, splat (i1 true)
%res = and <vscale x 8 x i1> %a, %not_b
ret <vscale x 8 x i1> %res
}
@@ -184,8 +176,7 @@ define <vscale x 16 x i1> @bic_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1>
; CHECK: // %bb.0:
; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
- %allones = shufflevector <vscale x 16 x i1> insertelement(<vscale x 16 x i1> undef, i1 true, i32 0), <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
- %not_b = xor <vscale x 16 x i1> %b, %allones
+ %not_b = xor <vscale x 16 x i1> %b, splat (i1 true)
%res = and <vscale x 16 x i1> %a, %not_b
ret <vscale x 16 x i1> %res
}
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
index a995823fe446c..a2061579c8c5e 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
@@ -1112,8 +1112,7 @@ define <vscale x 16 x i1> @predicated_icmp_eq_imm(<vscale x 16 x i1> %a, <vscale
; CHECK: // %bb.0:
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 0, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
- %icmp = icmp eq <vscale x 16 x i8> %b, %imm
+ %icmp = icmp eq <vscale x 16 x i8> %b, zeroinitializer
%and = and <vscale x 16 x i1> %a, %icmp
ret <vscale x 16 x i1> %and
}
@@ -1123,8 +1122,7 @@ define <vscale x 8 x i1> @predicated_icmp_ne_imm(<vscale x 8 x i1> %a, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #-16
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -16, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
- %icmp = icmp ne <vscale x 8 x i16> %b, %imm
+ %icmp = icmp ne <vscale x 8 x i16> %b, splat (i16 -16)
%and = and <vscale x 8 x i1> %a, %icmp
ret <vscale x 8 x i1> %and
}
@@ -1134,8 +1132,7 @@ define <vscale x 4 x i1> @predicated_icmp_sge_imm(<vscale x 4 x i1> %a, <vscale
; CHECK: // %bb.0:
; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #1
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
- %icmp = icmp sge <vscale x 4 x i32> %b, %imm
+ %icmp = icmp sge <vscale x 4 x i32> %b, splat (i32 1)
%and = and <vscale x 4 x i1> %a, %icmp
ret <vscale x 4 x i1> %and
}
@@ -1145,8 +1142,7 @@ define <vscale x 2 x i1> @predicated_icmp_sgt_imm(<vscale x 2 x i1> %a, <vscale
; CHECK: // %bb.0:
; CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, #2
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 2, i64 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
- %icmp = icmp sgt <vscale x 2 x i64> %b, %imm
+ %icmp = icmp sgt <vscale x 2 x i64> %b, splat (i64 2)
%and = and <vscale x 2 x i1> %a, %icmp
ret <vscale x 2 x i1> %and
}
@@ -1156,8 +1152,7 @@ define <vscale x 16 x i1> @predicated_icmp_sle_imm(<vscale x 16 x i1> %a, <vscal
; CHECK: // %bb.0:
; CHECK-NEXT: cmple p0.b, p0/z, z0.b, #-1
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 -1, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
- %icmp = icmp sle <vscale x 16 x i8> %b, %imm
+ %icmp = icmp sle <vscale x 16 x i8> %b, splat (i8 -1)
%and = and <vscale x 16 x i1> %a, %icmp
ret <vscale x 16 x i1> %and
}
@@ -1167,8 +1162,7 @@ define <vscale x 8 x i1> @predicated_icmp_slt_imm(<vscale x 8 x i1> %a, <vscale
; CHECK: // %bb.0:
; CHECK-NEXT: cmplt p0.h, p0/z, z0.h, #-2
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -2, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
- %icmp = icmp slt <vscale x 8 x i16> %b, %imm
+ %icmp = icmp slt <vscale x 8 x i16> %b, splat (i16 -2)
%and = and <vscale x 8 x i1> %a, %icmp
ret <vscale x 8 x i1> %and
}
@@ -1178,8 +1172,7 @@ define <vscale x 4 x i1> @predicated_icmp_uge_imm(<vscale x 4 x i1> %a, <vscale
; CHECK: // %bb.0:
; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #1
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
- %icmp = icmp uge <vscale x 4 x i32> %b, %imm
+ %icmp = icmp uge <vscale x 4 x i32> %b, splat (i32 1)
%and = and <vscale x 4 x i1> %a, %icmp
ret <vscale x 4 x i1> %and
}
@@ -1189,8 +1182,7 @@ define <vscale x 2 x i1> @predicated_icmp_ugt_imm(<vscale x 2 x i1> %a, <vscale
; CHECK: // %bb.0:
; CHECK-NEXT: cmphi p0.d, p0/z, z0.d, #2
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 2, i64 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
- %icmp = icmp ugt <vscale x 2 x i64> %b, %imm
+ %icmp = icmp ugt <vscale x 2 x i64> %b, splat (i64 2)
%and = and <vscale x 2 x i1> %a, %icmp
ret <vscale x 2 x i1> %and
}
@@ -1200,8 +1192,7 @@ define <vscale x 16 x i1> @predicated_icmp_ule_imm(<vscale x 16 x i1> %a, <vscal
; CHECK: // %bb.0:
; CHECK-NEXT: cmpls p0.b, p0/z, z0.b, #3
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 3, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
- %icmp = icmp ule <vscale x 16 x i8> %b, %imm
+ %icmp = icmp ule <vscale x 16 x i8> %b, splat (i8 3)
%and = and <vscale x 16 x i1> %a, %icmp
ret <vscale x 16 x i1> %and
}
@@ -1211,8 +1202,7 @@ define <vscale x 8 x i1> @predicated_icmp_ult_imm(<vscale x 8 x i1> %a, <vscale
; CHECK: // %bb.0:
; CHECK-NEXT: cmplo p0.h, p0/z, z0.h, #127
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 127, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
- %icmp = icmp ult <vscale x 8 x i16> %b, %imm
+ %icmp = icmp ult <vscale x 8 x i16> %b, splat (i16 127)
%and = and <vscale x 8 x i1> %a, %icmp
ret <vscale x 8 x i1> %and
}
@@ -1240,8 +1230,7 @@ define %svboolx2 @and_of_multiuse_icmp_sle_imm(<vscale x 4 x i1> %a, <vscale x 4
; CHECK-NEXT: cmple p1.s, p1/z, z0.s, #1
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
- %cmp = icmp sle <vscale x 4 x i32> %b, %imm
+ %cmp = icmp sle <vscale x 4 x i32> %b, splat (i32 1)
%and = and <vscale x 4 x i1> %a, %cmp
%ins.1 = insertvalue %svboolx2 poison, <vscale x 4 x i1> %and, 0
%ins.2 = insertvalue %svboolx2 %ins.1, <vscale x 4 x i1> %cmp, 1
@@ -1269,8 +1258,7 @@ define %svboolx2 @and_of_multiuse_icmp_ugt_imm(<vscale x 4 x i1> %a, <vscale x 4
; CHECK-NEXT: cmphi p1.s, p1/z, z0.s, #1
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
- %imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
- %cmp = icmp ugt <vscale x 4 x i32> %b, %imm
+ %cmp = icmp ugt <vscale x 4 x i32> %b, splat (i32 1)
%and = and <vscale x 4 x i1> %a, %cmp
%ins.1 = insertvalue %svboolx2 poison, <vscale x 4 x i1> %and, 0
%ins.2 = insertvalue %svboolx2 %ins.1, <vscale x 4 x i1> %cmp, 1
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
index 5db7ee75c2a8d..6c6fecb2a0d22 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
@@ -5,55 +5,47 @@
; AND
;
-define <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> %a) {
+define <vscale x 16 x i8> @and_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
; CHECK-LABEL: and_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.b, z0.b, #0x7
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 16 x i1> insertelement (<vscale x 16 x i1> undef, i1 true, i32 0), <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
- %b = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 7, i32 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.and.u.nxv16i8(<vscale x 16 x i1> %pg,
<vscale x 16 x i8> %a,
- <vscale x 16 x i8> %b)
+ <vscale x 16 x i8> splat (i8 7))
ret <vscale x 16 x i8> %out
}
-define <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> %a) {
+define <vscale x 8 x i16> @and_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
; CHECK-LABEL: and_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.h, z0.h, #0xf0
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 8 x i1> insertelement (<vscale x 8 x i1> undef, i1 true, i32 0), <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
- %b = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 240, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.and.u.nxv8i16(<vscale x 8 x i1> %pg,
<vscale x 8 x i16> %a,
- <vscale x 8 x i16> %b)
+ <vscale x 8 x i16> splat (i16 240))
ret <vscale x 8 x i16> %out
}
-define <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> %a) {
+define <vscale x 4 x i32> @and_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
; CHECK-LABEL: and_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.s, z0.s, #0xffff00
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 4 x i1> insertelement (<vscale x 4 x i1> undef, i1 true, i32 0), <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
- %b = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 16776960, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1> %pg,
<vscale x 4 x i32> %a,
- <vscale x 4 x i32> %b)
+ <vscale x 4 x i32> splat (i32 16776960))
ret <vscale x 4 x i32> %out
}
-define <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a) {
+define <vscale x 2 x i64> @and_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
; CHECK-LABEL: and_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.d, z0.d, #0xfffc000000000000
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
- %b = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 18445618173802708992, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.and.u.nxv2i64(<vscale x 2 x i1> %pg,
<vscale x 2 x i64> %a,
- <vscale x 2 x i64> %b)
+ <vscale x 2 x i64> splat (i64 18445618173802708992))
ret <vscale x 2 x i64> %out
}
@@ -61,55 +53,47 @@ define <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a) {
; BIC
;
-define <vscale x 16 x i8> @bic_i8(<vscale x 16 x i8> %a) {
+define <vscale x 16 x i8> @bic_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
; CHECK-LABEL: bic_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.b, z0.b, #0x1
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 16 x i1> insertelement (<vscale x 16 x i1> undef, i1 true, i32 0), <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
- %b = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 254, i32 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.u.nxv16i8(<vscale x 16 x i1> %pg,
<vscale x 16 x i8> %a,
- <vscale x 16 x i8> %b)
+ <vscale x 16 x i8> splat (i8 254))
ret <vscale x 16 x i8> %out
}
-define <vscale x 8 x i16> @bic_i16(<vscale x 8 x i16> %a) {
+define <vscale x 8 x i16> @bic_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
; CHECK-LABEL: bic_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.h, z0.h, #0x1
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 8 x i1> insertelement (<vscale x 8 x i1> undef, i1 true, i32 0), <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
- %b = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 65534, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.u.nxv8i16(<vscale x 8 x i1> %pg,
<vscale x 8 x i16> %a,
- <vscale x 8 x i16> %b)
+ <vscale x 8 x i16> splat (i16 65534))
ret <vscale x 8 x i16> %out
}
-define <vscale x 4 x i32> @bic_i32(<vscale x 4 x i32> %a) {
+define <vscale x 4 x i32> @bic_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
; CHECK-LABEL: bic_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.s, z0.s, #0xff0000ff
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 4 x i1> insertelement (<vscale x 4 x i1> undef, i1 true, i32 0), <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
- %b = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 16776960, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.u.nxv4i32(<vscale x 4 x i1> %pg,
<vscale x 4 x i32> %a,
- <vscale x 4 x i32> %b)
+ <vscale x 4 x i32> splat (i32 16776960))
ret <vscale x 4 x i32> %out
}
-define <vscale x 2 x i64> @bic_i64(<vscale x 2 x i64> %a) {
+define <vscale x 2 x i64> @bic_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
; CHECK-LABEL: bic_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.d, z0.d, #0x3ffffffffffff
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
- %b = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 18445618173802708992, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.u.nxv2i64(<vscale x 2 x i1> %pg,
<vscale x 2 x i64> %a,
- <vscale x 2 x i64> %b)
+ <vscale x 2 x i64> splat (i64 18445618173802708992))
ret <vscale x 2 x i64> %out
}
@@ -117,55 +101,47 @@ define <vscale x 2 x i64> @bic_i64(<vscale x 2 x i64> %a) {
; EOR
;
-define <vscale x 16 x i8> @eor_i8(<vscale x 16 x i8> %a) {
+define <vscale x 16 x i8> @eor_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
; CHECK-LABEL: eor_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: eor z0.b, z0.b, #0xf
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 16 x i1> insertelement (<vscale x 16 x i1> undef, i1 true, i32 0), <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
- %b = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 15, i32 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.u.nxv16i8(<vscale x 16 x i1> %pg,
<vscale x 16 x i8> %a,
- <vscale x 16 x i8> %b)
+ <vscale x 16 x i8> splat (i8 15))
ret <vscale x 16 x i8> %out
}
-define <vscale x 8 x i16> @eor_i16(<vscale x 8 x i16> %a) {
+define <vscale x 8 x i16> @eor_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
; CHECK-LABEL: eor_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: eor z0.h, z0.h, #0xfc07
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 8 x i1> insertelement (<vscale x 8 x i1> undef, i1 true, i32 0), <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
- %b = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 64519, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.u.nxv8i16(<vscale x 8 x i1> %pg,
<vscale x 8 x i16> %a,
- <vscale x 8 x i16> %b)
+ <vscale x 8 x i16> splat (i16 64519))
ret <vscale x 8 x i16> %out
}
-define <vscale x 4 x i32> @eor_i32(<vscale x 4 x i32> %a) {
+define <vscale x 4 x i32> @eor_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
; CHECK-LABEL: eor_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: eor z0.s, z0.s, #0xffff00
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 4 x i1> insertelement (<vscale x 4 x i1> undef, i1 true, i32 0), <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
- %b = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 16776960, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1> %pg,
<vscale x 4 x i32> %a,
- <vscale x 4 x i32> %b)
+ <vscale x 4 x i32> splat (i32 16776960))
ret <vscale x 4 x i32> %out
}
-define <vscale x 2 x i64> @eor_i64(<vscale x 2 x i64> %a) {
+define <vscale x 2 x i64> @eor_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
; CHECK-LABEL: eor_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: eor z0.d, z0.d, #0x1000000000000
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
- %b = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 281474976710656, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.u.nxv2i64(<vscale x 2 x i1> %pg,
<vscale x 2 x i64> %a,
- <vscale x 2 x i64> %b)
+ <vscale x 2 x i64> splat (i64 281474976710656))
ret <vscale x 2 x i64> %out
}
@@ -173,55 +149,47 @@ define <vscale x 2 x i64> @eor_i64(<vscale x 2 x i64> %a) {
; ORR
;
-define <vscale x 16 x i8> @orr_i8(<vscale x 16 x i8> %a) {
+define <vscale x 16 x i8> @orr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
; CHECK-LABEL: orr_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: orr z0.b, z0.b, #0x6
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 16 x i1> insertelement (<vscale x 16 x i1> undef, i1 true, i32 0), <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
- %b = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 6, i32 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> %pg,
<vscale x 16 x i8> %a,
- <vscale x 16 x i8> %b)
+ <vscale x 16 x i8> splat (i8 6))
ret <vscale x 16 x i8> %out
}
-define <vscale x 8 x i16> @orr_i16(<vscale x 8 x i16> %a) {
+define <vscale x 8 x i16> @orr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
; CHECK-LABEL: orr_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: orr z0.h, z0.h, #0x8001
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 8 x i1> insertelement (<vscale x 8 x i1> undef, i1 true, i32 0), <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
- %b = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 32769, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> %pg,
<vscale x 8 x i16> %a,
- <vscale x 8 x i16> %b)
+ <vscale x 8 x i16> splat (i16 32769))
ret <vscale x 8 x i16> %out
}
-define <vscale x 4 x i32> @orr_i32(<vscale x 4 x i32> %a) {
+define <vscale x 4 x i32> @orr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
; CHECK-LABEL: orr_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: orr z0.s, z0.s, #0xffff
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 4 x i1> insertelement (<vscale x 4 x i1> undef, i1 true, i32 0), <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
- %b = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 65535, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> %pg,
<vscale x 4 x i32> %a,
- <vscale x 4 x i32> %b)
+ <vscale x 4 x i32> splat (i32 65535))
ret <vscale x 4 x i32> %out
}
-define <vscale x 2 x i64> @orr_i64(<vscale x 2 x i64> %a) {
+define <vscale x 2 x i64> @orr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
; CHECK-LABEL: orr_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: orr z0.d, z0.d, #0x7ffc000000000000
; CHECK-NEXT: ret
- %pg = shufflevector <vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
- %b = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 9222246136947933184, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> %pg,
<vscale x 2 x i64> %a,
- <vscale x 2 x i64> %b)
+ <vscale x 2 x i64> splat (i64 9222246136947933184))
ret <vscale x 2 x i64> %out
}
diff --git a/llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll b/llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
index 5d53c00c52728..7edfe2e20e94c 100644
--- a/llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
+++ b/llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
@@ -14,8 +14,6 @@ define void @ld_st_nxv8i16(ptr %in, ptr %out) {
; IR-NEXT: entry:
; IR-NEXT: br label [[LOOP_PH:%.*]]
; IR: loop.ph:
-; IR-NEXT: [[P_VEC_SPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> undef, i16 3, i32 0
-; IR-NEXT: [[P_VEC_SPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[P_VEC_SPLATINSERT]], <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
; IR-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
; IR-NEXT: [[SCALED_VF:%.*]] = shl i64 [[VSCALE]], 3
; IR-NEXT: br label [[LOOP:%.*]]
@@ -26,7 +24,7 @@ define void @ld_st_nxv8i16(ptr %in, ptr %out) {
; IR-NEXT: [[TMP1:%.*]] = shl i64 [[INDVAR]], 1
; IR-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[OUT:%.*]], i64 [[TMP1]]
; IR-NEXT: [[VAL:%.*]] = load <vscale x 8 x i16>, ptr [[UGLYGEP1]], align 16
-; IR-NEXT: [[ADDP_VEC:%.*]] = add <vscale x 8 x i16> [[VAL]], [[P_VEC_SPLAT]]
+; IR-NEXT: [[ADDP_VEC:%.*]] = add <vscale x 8 x i16> [[VAL]], splat (i16 3)
; IR-NEXT: store <vscale x 8 x i16> [[ADDP_VEC]], ptr [[UGLYGEP]], align 16
; IR-NEXT: [[INDVAR_NEXT]] = add nsw i64 [[INDVAR]], [[SCALED_VF]]
; IR-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[INDVAR_NEXT]], 1024
@@ -38,15 +36,14 @@ define void @ld_st_nxv8i16(ptr %in, ptr %out) {
;
; ASM-LABEL: ld_st_nxv8i16:
; ASM: // %bb.0: // %entry
-; ASM-NEXT: mov z0.h, #3 // =0x3
; ASM-NEXT: ptrue p0.h
; ASM-NEXT: mov x8, xzr
; ASM-NEXT: cnth x9
; ASM-NEXT: .LBB0_1: // %loop
; ASM-NEXT: // =>This Inner Loop Header: Depth=1
-; ASM-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1]
-; ASM-NEXT: add z1.h, z1.h, z0.h
-; ASM-NEXT: st1h { z1.h }, p0, [x1, x8, lsl #1]
+; ASM-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
+; ASM-NEXT: add z0.h, z0.h, #3
+; ASM-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]
; ASM-NEXT: add x8, x8, x9
; ASM-NEXT: cmp x8, #1024
; ASM-NEXT: b.ne .LBB0_1
@@ -56,8 +53,6 @@ entry:
br label %loop.ph
loop.ph:
- %p_vec.splatinsert = insertelement <vscale x 8 x i16> undef, i16 3, i32 0
- %p_vec.splat = shufflevector <vscale x 8 x i16> %p_vec.splatinsert, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vscale = call i64 @llvm.vscale.i64()
%scaled_vf = shl i64 %vscale, 3
br label %loop
@@ -67,7 +62,7 @@ loop: ; preds = %loop, %loop.ph
%ptr.in = getelementptr inbounds i16, ptr %in, i64 %indvar
%ptr.out = getelementptr inbounds i16, ptr %out, i64 %indvar
%val = load <vscale x 8 x i16>, ptr %ptr.in, align 16
- %addp_vec = add <vscale x 8 x i16> %val, %p_vec.splat
+ %addp_vec = add <vscale x 8 x i16> %val, splat (i16 3)
store <vscale x 8 x i16> %addp_vec, ptr %ptr.out, align 16
%indvar.next = add nsw i64 %indvar, %scaled_vf
%exit.cond = icmp eq i64 %indvar.next, 1024
@@ -85,10 +80,6 @@ define void @masked_ld_st_nxv8i16(ptr %in, ptr %out, i64 %n) {
; IR-NEXT: entry:
; IR-NEXT: br label [[LOOP_PH:%.*]]
; IR: loop.ph:
-; IR-NEXT: [[P_VEC_SPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> undef, i16 3, i32 0
-; IR-NEXT: [[P_VEC_SPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[P_VEC_SPLATINSERT]], <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
-; IR-NEXT: [[PTRUE_VEC_SPLATINSERT:%.*]] = insertelement <vscale x 8 x i1> undef, i1 true, i32 0
-; IR-NEXT: [[PTRUE_VEC_SPLAT:%.*]] = shufflevector <vscale x 8 x i1> [[PTRUE_VEC_SPLATINSERT]], <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
; IR-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
; IR-NEXT: [[SCALED_VF:%.*]] = shl i64 [[VSCALE]], 3
; IR-NEXT: br label [[LOOP:%.*]]
@@ -98,9 +89,9 @@ define void @masked_ld_st_nxv8i16(ptr %in, ptr %out, i64 %n) {
; IR-NEXT: [[UGLYGEP1:%.*]] = getelementptr i8, ptr [[IN:%.*]], i64 [[TMP0]]
; IR-NEXT: [[TMP1:%.*]] = shl i64 [[INDVAR]], 1
; IR-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[OUT:%.*]], i64 [[TMP1]]
-; IR-NEXT: [[VAL:%.*]] = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr [[UGLYGEP1]], i32 4, <vscale x 8 x i1> [[PTRUE_VEC_SPLAT]], <vscale x 8 x i16> undef)
-; IR-NEXT: [[ADDP_VEC:%.*]] = add <vscale x 8 x i16> [[VAL]], [[P_VEC_SPLAT]]
-; IR-NEXT: call void @llvm.masked.store.nxv8i16.p0(<vscale x 8 x i16> [[ADDP_VEC]], ptr [[UGLYGEP]], i32 4, <vscale x 8 x i1> [[PTRUE_VEC_SPLAT]])
+; IR-NEXT: [[VAL:%.*]] = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr [[UGLYGEP1]], i32 4, <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> undef)
+; IR-NEXT: [[ADDP_VEC:%.*]] = add <vscale x 8 x i16> [[VAL]], splat (i16 3)
+; IR-NEXT: call void @llvm.masked.store.nxv8i16.p0(<vscale x 8 x i16> [[ADDP_VEC]], ptr [[UGLYGEP]], i32 4, <vscale x 8 x i1> splat (i1 true))
; IR-NEXT: [[INDVAR_NEXT]] = add nsw i64 [[INDVAR]], [[SCALED_VF]]
; IR-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[N:%.*]], [[INDVAR_NEXT]]
; IR-NEXT: br i1 [[EXIT_COND]], label [[LOOP_EXIT:%.*]], label [[LOOP]]
@@ -111,15 +102,14 @@ define void @masked_ld_st_nxv8i16(ptr %in, ptr %out, i64 %n) {
;
; ASM-LABEL: masked_ld_st_nxv8i16:
; ASM: // %bb.0: // %entry
-; ASM-NEXT: mov z0.h, #3 // =0x3
; ASM-NEXT: ptrue p0.h
; ASM-NEXT: mov x8, xzr
; ASM-NEXT: cnth x9
; ASM-NEXT: .LBB1_1: // %loop
; ASM-NEXT: // =>This Inner Loop Header: Depth=1
-; ASM-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1]
-; ASM-NEXT: add z1.h, z1.h, z0.h
-; ASM-NEXT: st1h { z1.h }, p0, [x1, x8, lsl #1]
+; ASM-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
+; ASM-NEXT: add z0.h, z0.h, #3
+; ASM-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]
; ASM-NEXT: add x8, x8, x9
; ASM-NEXT: cmp x2, x8
; ASM-NEXT: b.ne .LBB1_1
@@ -129,10 +119,6 @@ entry:
br label %loop.ph
loop.ph:
- %p_vec.splatinsert = insertelement <vscale x 8 x i16> undef, i16 3, i32 0
- %p_vec.splat = shufflevector <vscale x 8 x i16> %p_vec.splatinsert, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
- %ptrue_vec.splatinsert = insertelement <vscale x 8 x i1> undef, i1 true, i32 0
- %ptrue_vec.splat = shufflevector <vscale x 8 x i1> %ptrue_vec.splatinsert, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
%vscale = call i64 @llvm.vscale.i64()
%scaled_vf = shl i64 %vscale, 3
br label %loop
@@ -141,9 +127,9 @@ loop: ; preds = %loop, %loop.ph
%indvar = phi i64 [ 0, %loop.ph ], [ %indvar.next, %loop ]
%ptr.in = getelementptr inbounds i16, ptr %in, i64 %indvar
%ptr.out = getelementptr inbounds i16, ptr %out, i64 %indvar
- %val = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr %ptr.in, i32 4, <vscale x 8 x i1> %ptrue_vec.splat, <vscale x 8 x i16> undef)
- %addp_vec = add <vscale x 8 x i16> %val, %p_vec.splat
- call void @llvm.masked.store.nxv8i16.p0(<vscale x 8 x i16> %addp_vec, ptr %ptr.out, i32 4, <vscale x 8 x i1> %ptrue_vec.splat)
+ %val = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr %ptr.in, i32 4, <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> undef)
+ %addp_vec = add <vscale x 8 x i16> %val, splat (i16 3)
+ call void @llvm.masked.store.nxv8i16.p0(<vscale x 8 x i16> %addp_vec, ptr %ptr.out, i32 4, <vscale x 8 x i1> splat (i1 true))
%indvar.next = add nsw i64 %indvar, %scaled_vf
%exit.cond = icmp eq i64 %indvar.next, %n
br i1 %exit.cond, label %loop.exit, label %loop
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
index 1335bb769821f..2e8d91e7083bf 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
@@ -130,9 +130,7 @@ define void @add_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i32 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = add <32 x i8> %op1, %op2
+ %res = add <32 x i8> %op1, splat(i8 7)
store <32 x i8> %res, ptr %a
ret void
}
@@ -204,9 +202,7 @@ define void @add_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = add <16 x i16> %op1, %op2
+ %res = add <16 x i16> %op1, splat(i16 15)
store <16 x i16> %res, ptr %a
ret void
}
@@ -250,9 +246,7 @@ define void @add_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = add <8 x i32> %op1, %op2
+ %res = add <8 x i32> %op1, splat(i32 31)
store <8 x i32> %res, ptr %a
ret void
}
@@ -286,9 +280,7 @@ define void @add_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = add <4 x i64> %op1, %op2
+ %res = add <4 x i64> %op1, splat(i64 63)
store <4 x i64> %res, ptr %a
ret void
}
@@ -412,9 +404,7 @@ define void @and_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i32 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = and <32 x i8> %op1, %op2
+ %res = and <32 x i8> %op1, splat(i8 7)
store <32 x i8> %res, ptr %a
ret void
}
@@ -486,9 +476,7 @@ define void @and_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = and <16 x i16> %op1, %op2
+ %res = and <16 x i16> %op1, splat(i16 15)
store <16 x i16> %res, ptr %a
ret void
}
@@ -532,9 +520,7 @@ define void @and_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = and <8 x i32> %op1, %op2
+ %res = and <8 x i32> %op1, splat(i32 31)
store <8 x i32> %res, ptr %a
ret void
}
@@ -568,9 +554,7 @@ define void @and_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = and <4 x i64> %op1, %op2
+ %res = and <4 x i64> %op1, splat(i64 63)
store <4 x i64> %res, ptr %a
ret void
}
@@ -694,9 +678,7 @@ define void @ashr_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i32 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = ashr <32 x i8> %op1, %op2
+ %res = ashr <32 x i8> %op1, splat(i8 7)
store <32 x i8> %res, ptr %a
ret void
}
@@ -768,9 +750,7 @@ define void @ashr_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = ashr <16 x i16> %op1, %op2
+ %res = ashr <16 x i16> %op1, splat(i16 15)
store <16 x i16> %res, ptr %a
ret void
}
@@ -814,9 +794,7 @@ define void @ashr_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = ashr <8 x i32> %op1, %op2
+ %res = ashr <8 x i32> %op1, splat(i32 31)
store <8 x i32> %res, ptr %a
ret void
}
@@ -850,9 +828,7 @@ define void @ashr_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = ashr <4 x i64> %op1, %op2
+ %res = ashr <4 x i64> %op1, splat(i64 63)
store <4 x i64> %res, ptr %a
ret void
}
@@ -1011,9 +987,7 @@ define void @icmp_eq_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %cmp = icmp eq <32 x i8> %op1, %op2
+ %cmp = icmp eq <32 x i8> %op1, splat(i8 7)
%res = sext <32 x i1> %cmp to <32 x i8>
store <32 x i8> %res, ptr %a
ret void
@@ -1105,9 +1079,7 @@ define void @icmp_sge_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %cmp = icmp sge <16 x i16> %op1, %op2
+ %cmp = icmp sge <16 x i16> %op1, splat(i16 15)
%res = sext <16 x i1> %cmp to <16 x i16>
store <16 x i16> %res, ptr %a
ret void
@@ -1163,9 +1135,7 @@ define void @icmp_sgt_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 -8, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %cmp = icmp sgt <8 x i32> %op1, %op2
+ %cmp = icmp sgt <8 x i32> %op1, splat(i32 -8)
%res = sext <8 x i1> %cmp to <8 x i32>
store <8 x i32> %res, ptr %a
ret void
@@ -1207,9 +1177,7 @@ define void @icmp_ult_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %cmp = icmp ult <4 x i64> %op1, %op2
+ %cmp = icmp ult <4 x i64> %op1, splat(i64 63)
%res = sext <4 x i1> %cmp to <4 x i64>
store <4 x i64> %res, ptr %a
ret void
@@ -1334,9 +1302,7 @@ define void @lshr_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = lshr <32 x i8> %op1, %op2
+ %res = lshr <32 x i8> %op1, splat(i8 7)
store <32 x i8> %res, ptr %a
ret void
}
@@ -1408,9 +1374,7 @@ define void @lshr_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = lshr <16 x i16> %op1, %op2
+ %res = lshr <16 x i16> %op1, splat(i16 15)
store <16 x i16> %res, ptr %a
ret void
}
@@ -1454,9 +1418,7 @@ define void @lshr_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = lshr <8 x i32> %op1, %op2
+ %res = lshr <8 x i32> %op1, splat(i32 31)
store <8 x i32> %res, ptr %a
ret void
}
@@ -1490,9 +1452,7 @@ define void @lshr_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = lshr <4 x i64> %op1, %op2
+ %res = lshr <4 x i64> %op1, splat(i64 63)
store <4 x i64> %res, ptr %a
ret void
}
@@ -1648,9 +1608,7 @@ define void @mul_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = mul <32 x i8> %op1, %op2
+ %res = mul <32 x i8> %op1, splat(i8 7)
store <32 x i8> %res, ptr %a
ret void
}
@@ -1738,9 +1696,7 @@ define void @mul_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = mul <16 x i16> %op1, %op2
+ %res = mul <16 x i16> %op1, splat(i16 15)
store <16 x i16> %res, ptr %a
ret void
}
@@ -1796,9 +1752,7 @@ define void @mul_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = mul <8 x i32> %op1, %op2
+ %res = mul <8 x i32> %op1, splat(i32 31)
store <8 x i32> %res, ptr %a
ret void
}
@@ -1838,9 +1792,7 @@ define void @mul_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = mul <4 x i64> %op1, %op2
+ %res = mul <4 x i64> %op1, splat(i64 63)
store <4 x i64> %res, ptr %a
ret void
}
@@ -1964,9 +1916,7 @@ define void @or_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = or <32 x i8> %op1, %op2
+ %res = or <32 x i8> %op1, splat(i8 7)
store <32 x i8> %res, ptr %a
ret void
}
@@ -2038,9 +1988,7 @@ define void @or_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = or <16 x i16> %op1, %op2
+ %res = or <16 x i16> %op1, splat(i16 15)
store <16 x i16> %res, ptr %a
ret void
}
@@ -2084,9 +2032,7 @@ define void @or_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = or <8 x i32> %op1, %op2
+ %res = or <8 x i32> %op1, splat(i32 31)
store <8 x i32> %res, ptr %a
ret void
}
@@ -2120,9 +2066,7 @@ define void @or_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = or <4 x i64> %op1, %op2
+ %res = or <4 x i64> %op1, splat(i64 63)
store <4 x i64> %res, ptr %a
ret void
}
@@ -2246,9 +2190,7 @@ define void @shl_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = shl <32 x i8> %op1, %op2
+ %res = shl <32 x i8> %op1, splat(i8 7)
store <32 x i8> %res, ptr %a
ret void
}
@@ -2320,9 +2262,7 @@ define void @shl_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = shl <16 x i16> %op1, %op2
+ %res = shl <16 x i16> %op1, splat(i16 15)
store <16 x i16> %res, ptr %a
ret void
}
@@ -2366,9 +2306,7 @@ define void @shl_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = shl <8 x i32> %op1, %op2
+ %res = shl <8 x i32> %op1, splat(i32 31)
store <8 x i32> %res, ptr %a
ret void
}
@@ -2402,9 +2340,7 @@ define void @shl_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = shl <4 x i64> %op1, %op2
+ %res = shl <4 x i64> %op1, splat(i64 63)
store <4 x i64> %res, ptr %a
ret void
}
@@ -2561,9 +2497,7 @@ define void @smax_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = call <32 x i8> @llvm.smax.v32i8(<32 x i8> %op1, <32 x i8> %op2)
+ %res = call <32 x i8> @llvm.smax.v32i8(<32 x i8> %op1, <32 x i8> splat(i8 7))
store <32 x i8> %res, ptr %a
ret void
}
@@ -2652,9 +2586,7 @@ define void @smax_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = call <16 x i16> @llvm.smax.v16i16(<16 x i16> %op1, <16 x i16> %op2)
+ %res = call <16 x i16> @llvm.smax.v16i16(<16 x i16> %op1, <16 x i16> splat(i16 15))
store <16 x i16> %res, ptr %a
ret void
}
@@ -2707,9 +2639,7 @@ define void @smax_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %op1, <8 x i32> %op2)
+ %res = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %op1, <8 x i32> splat(i32 31))
store <8 x i32> %res, ptr %a
ret void
}
@@ -2748,9 +2678,7 @@ define void @smax_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %op1, <4 x i64> %op2)
+ %res = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %op1, <4 x i64> splat(i64 63))
store <4 x i64> %res, ptr %a
ret void
}
@@ -2907,9 +2835,7 @@ define void @smin_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = call <32 x i8> @llvm.smin.v32i8(<32 x i8> %op1, <32 x i8> %op2)
+ %res = call <32 x i8> @llvm.smin.v32i8(<32 x i8> %op1, <32 x i8> splat(i8 7))
store <32 x i8> %res, ptr %a
ret void
}
@@ -2998,9 +2924,7 @@ define void @smin_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = call <16 x i16> @llvm.smin.v16i16(<16 x i16> %op1, <16 x i16> %op2)
+ %res = call <16 x i16> @llvm.smin.v16i16(<16 x i16> %op1, <16 x i16> splat(i16 15))
store <16 x i16> %res, ptr %a
ret void
}
@@ -3053,9 +2977,7 @@ define void @smin_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %op1, <8 x i32> %op2)
+ %res = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %op1, <8 x i32> splat(i32 31))
store <8 x i32> %res, ptr %a
ret void
}
@@ -3094,9 +3016,7 @@ define void @smin_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %op1, <4 x i64> %op2)
+ %res = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %op1, <4 x i64> splat(i64 63))
store <4 x i64> %res, ptr %a
ret void
}
@@ -3220,9 +3140,7 @@ define void @sub_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = sub <32 x i8> %op1, %op2
+ %res = sub <32 x i8> %op1, splat(i8 7)
store <32 x i8> %res, ptr %a
ret void
}
@@ -3294,9 +3212,7 @@ define void @sub_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = sub <16 x i16> %op1, %op2
+ %res = sub <16 x i16> %op1, splat(i16 15)
store <16 x i16> %res, ptr %a
ret void
}
@@ -3340,9 +3256,7 @@ define void @sub_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = sub <8 x i32> %op1, %op2
+ %res = sub <8 x i32> %op1, splat(i32 31)
store <8 x i32> %res, ptr %a
ret void
}
@@ -3376,9 +3290,7 @@ define void @sub_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = sub <4 x i64> %op1, %op2
+ %res = sub <4 x i64> %op1, splat(i64 63)
store <4 x i64> %res, ptr %a
ret void
}
@@ -3535,9 +3447,7 @@ define void @umax_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = call <32 x i8> @llvm.umax.v32i8(<32 x i8> %op1, <32 x i8> %op2)
+ %res = call <32 x i8> @llvm.umax.v32i8(<32 x i8> %op1, <32 x i8> splat(i8 7))
store <32 x i8> %res, ptr %a
ret void
}
@@ -3626,9 +3536,7 @@ define void @umax_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = call <16 x i16> @llvm.umax.v16i16(<16 x i16> %op1, <16 x i16> %op2)
+ %res = call <16 x i16> @llvm.umax.v16i16(<16 x i16> %op1, <16 x i16> splat(i16 15))
store <16 x i16> %res, ptr %a
ret void
}
@@ -3681,9 +3589,7 @@ define void @umax_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = call <8 x i32> @llvm.umax.v8i32(<8 x i32> %op1, <8 x i32> %op2)
+ %res = call <8 x i32> @llvm.umax.v8i32(<8 x i32> %op1, <8 x i32> splat(i32 31))
store <8 x i32> %res, ptr %a
ret void
}
@@ -3722,9 +3628,7 @@ define void @umax_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %op1, <4 x i64> %op2)
+ %res = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %op1, <4 x i64> splat(i64 63))
store <4 x i64> %res, ptr %a
ret void
}
@@ -3881,9 +3785,7 @@ define void @umin_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = call <32 x i8> @llvm.umin.v32i8(<32 x i8> %op1, <32 x i8> %op2)
+ %res = call <32 x i8> @llvm.umin.v32i8(<32 x i8> %op1, <32 x i8> splat(i8 7))
store <32 x i8> %res, ptr %a
ret void
}
@@ -3972,9 +3874,7 @@ define void @umin_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = call <16 x i16> @llvm.umin.v16i16(<16 x i16> %op1, <16 x i16> %op2)
+ %res = call <16 x i16> @llvm.umin.v16i16(<16 x i16> %op1, <16 x i16> splat(i16 15))
store <16 x i16> %res, ptr %a
ret void
}
@@ -4027,9 +3927,7 @@ define void @umin_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %op1, <8 x i32> %op2)
+ %res = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %op1, <8 x i32> splat(i32 31))
store <8 x i32> %res, ptr %a
ret void
}
@@ -4068,9 +3966,7 @@ define void @umin_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %op1, <4 x i64> %op2)
+ %res = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %op1, <4 x i64> splat(i64 63))
store <4 x i64> %res, ptr %a
ret void
}
@@ -4194,9 +4090,7 @@ define void @xor_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
- %ins = insertelement <32 x i8> undef, i8 7, i64 0
- %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
- %res = xor <32 x i8> %op1, %op2
+ %res = xor <32 x i8> %op1, splat(i8 7)
store <32 x i8> %res, ptr %a
ret void
}
@@ -4268,9 +4162,7 @@ define void @xor_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
- %ins = insertelement <16 x i16> undef, i16 15, i64 0
- %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
- %res = xor <16 x i16> %op1, %op2
+ %res = xor <16 x i16> %op1, splat(i16 15)
store <16 x i16> %res, ptr %a
ret void
}
@@ -4314,9 +4206,7 @@ define void @xor_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
- %ins = insertelement <8 x i32> undef, i32 31, i64 0
- %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
- %res = xor <8 x i32> %op1, %op2
+ %res = xor <8 x i32> %op1, splat(i32 31)
store <8 x i32> %res, ptr %a
ret void
}
@@ -4350,9 +4240,7 @@ define void @xor_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
- %ins = insertelement <4 x i64> undef, i64 63, i64 0
- %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
- %res = xor <4 x i64> %op1, %op2
+ %res = xor <4 x i64> %op1, splat(i64 63)
store <4 x i64> %res, ptr %a
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
index b0fdce9a93bd3..97f2e7a1e66cb 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE
-; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE2
-; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,SVE2
+; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s --check-prefixes=SVE
+; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=SVE2
+; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=SVE2
; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
; This test only tests the legal types for a given vector width, as mulh nodes
@@ -66,12 +66,10 @@ define <4 x i8> @smulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]
; NONEON-NOSVE-NEXT: add sp, sp, #32
; NONEON-NOSVE-NEXT: ret
- %insert = insertelement <4 x i16> undef, i16 4, i64 0
- %splat = shufflevector <4 x i16> %insert, <4 x i16> undef, <4 x i32> zeroinitializer
%1 = sext <4 x i8> %op1 to <4 x i16>
%2 = sext <4 x i8> %op2 to <4 x i16>
%mul = mul <4 x i16> %1, %2
- %shr = lshr <4 x i16> %mul, <i16 4, i16 4, i16 4, i16 4>
+ %shr = lshr <4 x i16> %mul, splat (i16 4)
%res = trunc <4 x i16> %shr to <4 x i8>
ret <4 x i8> %res
}
@@ -142,12 +140,10 @@ define <8 x i8> @smulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]
; NONEON-NOSVE-NEXT: add sp, sp, #32
; NONEON-NOSVE-NEXT: ret
- %insert = insertelement <8 x i16> undef, i16 8, i64 0
- %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
%1 = sext <8 x i8> %op1 to <8 x i16>
%2 = sext <8 x i8> %op2 to <8 x i16>
%mul = mul <8 x i16> %1, %2
- %shr = lshr <8 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <8 x i16> %mul, splat (i16 8)
%res = trunc <8 x i16> %shr to <8 x i8>
ret <8 x i8> %res
}
@@ -286,7 +282,7 @@ define <16 x i8> @smulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
%1 = sext <16 x i8> %op1 to <16 x i16>
%2 = sext <16 x i8> %op2 to <16 x i16>
%mul = mul <16 x i16> %1, %2
- %shr = lshr <16 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <16 x i16> %mul, splat (i16 8)
%res = trunc <16 x i16> %shr to <16 x i8>
ret <16 x i8> %res
}
@@ -565,7 +561,7 @@ define void @smulh_v32i8(ptr %a, ptr %b) {
%1 = sext <32 x i8> %op1 to <32 x i16>
%2 = sext <32 x i8> %op2 to <32 x i16>
%mul = mul <32 x i16> %1, %2
- %shr = lshr <32 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <32 x i16> %mul, splat (i16 8)
%res = trunc <32 x i16> %shr to <32 x i8>
store <32 x i8> %res, ptr %a
ret void
@@ -616,7 +612,7 @@ define <2 x i16> @smulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
%1 = sext <2 x i16> %op1 to <2 x i32>
%2 = sext <2 x i16> %op2 to <2 x i32>
%mul = mul <2 x i32> %1, %2
- %shr = lshr <2 x i32> %mul, <i32 16, i32 16>
+ %shr = lshr <2 x i32> %mul, splat (i32 16)
%res = trunc <2 x i32> %shr to <2 x i16>
ret <2 x i16> %res
}
@@ -670,7 +666,7 @@ define <4 x i16> @smulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
%1 = sext <4 x i16> %op1 to <4 x i32>
%2 = sext <4 x i16> %op2 to <4 x i32>
%mul = mul <4 x i32> %1, %2
- %shr = lshr <4 x i32> %mul, <i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <4 x i32> %mul, splat (i32 16)
%res = trunc <4 x i32> %shr to <4 x i16>
ret <4 x i16> %res
}
@@ -747,7 +743,7 @@ define <8 x i16> @smulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
%1 = sext <8 x i16> %op1 to <8 x i32>
%2 = sext <8 x i16> %op2 to <8 x i32>
%mul = mul <8 x i32> %1, %2
- %shr = lshr <8 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <8 x i32> %mul, splat (i32 16)
%res = trunc <8 x i32> %shr to <8 x i16>
ret <8 x i16> %res
}
@@ -900,7 +896,7 @@ define void @smulh_v16i16(ptr %a, ptr %b) {
%1 = sext <16 x i16> %op1 to <16 x i32>
%2 = sext <16 x i16> %op2 to <16 x i32>
%mul = mul <16 x i32> %1, %2
- %shr = lshr <16 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <16 x i32> %mul, splat (i32 16)
%res = trunc <16 x i32> %shr to <16 x i16>
store <16 x i16> %res, ptr %a
ret void
@@ -942,7 +938,7 @@ define <2 x i32> @smulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
%1 = sext <2 x i32> %op1 to <2 x i64>
%2 = sext <2 x i32> %op2 to <2 x i64>
%mul = mul <2 x i64> %1, %2
- %shr = lshr <2 x i64> %mul, <i64 32, i64 32>
+ %shr = lshr <2 x i64> %mul, splat (i64 32)
%res = trunc <2 x i64> %shr to <2 x i32>
ret <2 x i32> %res
}
@@ -993,7 +989,7 @@ define <4 x i32> @smulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
%1 = sext <4 x i32> %op1 to <4 x i64>
%2 = sext <4 x i32> %op2 to <4 x i64>
%mul = mul <4 x i64> %1, %2
- %shr = lshr <4 x i64> %mul, <i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <4 x i64> %mul, splat (i64 32)
%res = trunc <4 x i64> %shr to <4 x i32>
ret <4 x i32> %res
}
@@ -1073,7 +1069,7 @@ define void @smulh_v8i32(ptr %a, ptr %b) {
%1 = sext <8 x i32> %op1 to <8 x i64>
%2 = sext <8 x i32> %op2 to <8 x i64>
%mul = mul <8 x i64> %1, %2
- %shr = lshr <8 x i64> %mul, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <8 x i64> %mul, splat (i64 32)
%res = trunc <8 x i64> %shr to <8 x i32>
store <8 x i32> %res, ptr %a
ret void
@@ -1108,12 +1104,10 @@ define <1 x i64> @smulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
- %insert = insertelement <1 x i128> undef, i128 64, i128 0
- %splat = shufflevector <1 x i128> %insert, <1 x i128> undef, <1 x i32> zeroinitializer
%1 = sext <1 x i64> %op1 to <1 x i128>
%2 = sext <1 x i64> %op2 to <1 x i128>
%mul = mul <1 x i128> %1, %2
- %shr = lshr <1 x i128> %mul, %splat
+ %shr = lshr <1 x i128> %mul, splat (i128 64)
%res = trunc <1 x i128> %shr to <1 x i64>
ret <1 x i64> %res
}
@@ -1153,7 +1147,7 @@ define <2 x i64> @smulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
%1 = sext <2 x i64> %op1 to <2 x i128>
%2 = sext <2 x i64> %op2 to <2 x i128>
%mul = mul <2 x i128> %1, %2
- %shr = lshr <2 x i128> %mul, <i128 64, i128 64>
+ %shr = lshr <2 x i128> %mul, splat (i128 64)
%res = trunc <2 x i128> %shr to <2 x i64>
ret <2 x i64> %res
}
@@ -1210,7 +1204,7 @@ define void @smulh_v4i64(ptr %a, ptr %b) {
%1 = sext <4 x i64> %op1 to <4 x i128>
%2 = sext <4 x i64> %op2 to <4 x i128>
%mul = mul <4 x i128> %1, %2
- %shr = lshr <4 x i128> %mul, <i128 64, i128 64, i128 64, i128 64>
+ %shr = lshr <4 x i128> %mul, splat (i128 64)
%res = trunc <4 x i128> %shr to <4 x i64>
store <4 x i64> %res, ptr %a
ret void
@@ -1275,7 +1269,7 @@ define <4 x i8> @umulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
%1 = zext <4 x i8> %op1 to <4 x i16>
%2 = zext <4 x i8> %op2 to <4 x i16>
%mul = mul <4 x i16> %1, %2
- %shr = lshr <4 x i16> %mul, <i16 4, i16 4, i16 4, i16 4>
+ %shr = lshr <4 x i16> %mul, splat (i16 4)
%res = trunc <4 x i16> %shr to <4 x i8>
ret <4 x i8> %res
}
@@ -1349,7 +1343,7 @@ define <8 x i8> @umulh_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
%1 = zext <8 x i8> %op1 to <8 x i16>
%2 = zext <8 x i8> %op2 to <8 x i16>
%mul = mul <8 x i16> %1, %2
- %shr = lshr <8 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <8 x i16> %mul, splat (i16 8)
%res = trunc <8 x i16> %shr to <8 x i8>
ret <8 x i8> %res
}
@@ -1488,7 +1482,7 @@ define <16 x i8> @umulh_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
%1 = zext <16 x i8> %op1 to <16 x i16>
%2 = zext <16 x i8> %op2 to <16 x i16>
%mul = mul <16 x i16> %1, %2
- %shr = lshr <16 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <16 x i16> %mul, splat (i16 8)
%res = trunc <16 x i16> %shr to <16 x i8>
ret <16 x i8> %res
}
@@ -1767,7 +1761,7 @@ define void @umulh_v32i8(ptr %a, ptr %b) {
%1 = zext <32 x i8> %op1 to <32 x i16>
%2 = zext <32 x i8> %op2 to <32 x i16>
%mul = mul <32 x i16> %1, %2
- %shr = lshr <32 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ %shr = lshr <32 x i16> %mul, splat (i16 8)
%res = trunc <32 x i16> %shr to <32 x i8>
store <32 x i8> %res, ptr %a
ret void
@@ -1817,7 +1811,7 @@ define <2 x i16> @umulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
%1 = zext <2 x i16> %op1 to <2 x i32>
%2 = zext <2 x i16> %op2 to <2 x i32>
%mul = mul <2 x i32> %1, %2
- %shr = lshr <2 x i32> %mul, <i32 16, i32 16>
+ %shr = lshr <2 x i32> %mul, splat (i32 16)
%res = trunc <2 x i32> %shr to <2 x i16>
ret <2 x i16> %res
}
@@ -1871,7 +1865,7 @@ define <4 x i16> @umulh_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
%1 = zext <4 x i16> %op1 to <4 x i32>
%2 = zext <4 x i16> %op2 to <4 x i32>
%mul = mul <4 x i32> %1, %2
- %shr = lshr <4 x i32> %mul, <i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <4 x i32> %mul, splat (i32 16)
%res = trunc <4 x i32> %shr to <4 x i16>
ret <4 x i16> %res
}
@@ -1948,7 +1942,7 @@ define <8 x i16> @umulh_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
%1 = zext <8 x i16> %op1 to <8 x i32>
%2 = zext <8 x i16> %op2 to <8 x i32>
%mul = mul <8 x i32> %1, %2
- %shr = lshr <8 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <8 x i32> %mul, splat (i32 16)
%res = trunc <8 x i32> %shr to <8 x i16>
ret <8 x i16> %res
}
@@ -2101,7 +2095,7 @@ define void @umulh_v16i16(ptr %a, ptr %b) {
%1 = zext <16 x i16> %op1 to <16 x i32>
%2 = zext <16 x i16> %op2 to <16 x i32>
%mul = mul <16 x i32> %1, %2
- %shr = lshr <16 x i32> %mul, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shr = lshr <16 x i32> %mul, splat (i32 16)
%res = trunc <16 x i32> %shr to <16 x i16>
store <16 x i16> %res, ptr %a
ret void
@@ -2143,7 +2137,7 @@ define <2 x i32> @umulh_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
%1 = zext <2 x i32> %op1 to <2 x i64>
%2 = zext <2 x i32> %op2 to <2 x i64>
%mul = mul <2 x i64> %1, %2
- %shr = lshr <2 x i64> %mul, <i64 32, i64 32>
+ %shr = lshr <2 x i64> %mul, splat (i64 32)
%res = trunc <2 x i64> %shr to <2 x i32>
ret <2 x i32> %res
}
@@ -2194,7 +2188,7 @@ define <4 x i32> @umulh_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
%1 = zext <4 x i32> %op1 to <4 x i64>
%2 = zext <4 x i32> %op2 to <4 x i64>
%mul = mul <4 x i64> %1, %2
- %shr = lshr <4 x i64> %mul, <i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <4 x i64> %mul, splat (i64 32)
%res = trunc <4 x i64> %shr to <4 x i32>
ret <4 x i32> %res
}
@@ -2271,12 +2265,10 @@ define void @umulh_v8i32(ptr %a, ptr %b) {
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
%op2 = load <8 x i32>, ptr %b
- %insert = insertelement <8 x i64> undef, i64 32, i64 0
- %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
%1 = zext <8 x i32> %op1 to <8 x i64>
%2 = zext <8 x i32> %op2 to <8 x i64>
%mul = mul <8 x i64> %1, %2
- %shr = lshr <8 x i64> %mul, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+ %shr = lshr <8 x i64> %mul, splat (i64 32)
%res = trunc <8 x i64> %shr to <8 x i32>
store <8 x i32> %res, ptr %a
ret void
@@ -2314,7 +2306,7 @@ define <1 x i64> @umulh_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
%1 = zext <1 x i64> %op1 to <1 x i128>
%2 = zext <1 x i64> %op2 to <1 x i128>
%mul = mul <1 x i128> %1, %2
- %shr = lshr <1 x i128> %mul, <i128 64>
+ %shr = lshr <1 x i128> %mul, splat (i128 64)
%res = trunc <1 x i128> %shr to <1 x i64>
ret <1 x i64> %res
}
@@ -2354,7 +2346,7 @@ define <2 x i64> @umulh_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
%1 = zext <2 x i64> %op1 to <2 x i128>
%2 = zext <2 x i64> %op2 to <2 x i128>
%mul = mul <2 x i128> %1, %2
- %shr = lshr <2 x i128> %mul, <i128 64, i128 64>
+ %shr = lshr <2 x i128> %mul, splat (i128 64)
%res = trunc <2 x i128> %shr to <2 x i64>
ret <2 x i64> %res
}
@@ -2411,10 +2403,8 @@ define void @umulh_v4i64(ptr %a, ptr %b) {
%1 = zext <4 x i64> %op1 to <4 x i128>
%2 = zext <4 x i64> %op2 to <4 x i128>
%mul = mul <4 x i128> %1, %2
- %shr = lshr <4 x i128> %mul, <i128 64, i128 64, i128 64, i128 64>
+ %shr = lshr <4 x i128> %mul, splat (i128 64)
%res = trunc <4 x i128> %shr to <4 x i64>
store <4 x i64> %res, ptr %a
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
index 96be762b4c8f6..939565216f586 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
@@ -599,9 +599,7 @@ define void @splat_imm_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI24_0]
; NONEON-NOSVE-NEXT: stp q0, q0, [x0]
; NONEON-NOSVE-NEXT: ret
- %insert = insertelement <32 x i8> undef, i8 1, i64 0
- %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
- store <32 x i8> %splat, ptr %a
+ store <32 x i8> splat (i8 1), ptr %a
ret void
}
@@ -618,9 +616,7 @@ define void @splat_imm_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI25_0]
; NONEON-NOSVE-NEXT: stp q0, q0, [x0]
; NONEON-NOSVE-NEXT: ret
- %insert = insertelement <16 x i16> undef, i16 2, i64 0
- %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
- store <16 x i16> %splat, ptr %a
+ store <16 x i16> splat (i16 2), ptr %a
ret void
}
@@ -637,9 +633,7 @@ define void @splat_imm_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI26_0]
; NONEON-NOSVE-NEXT: stp q0, q0, [x0]
; NONEON-NOSVE-NEXT: ret
- %insert = insertelement <8 x i32> undef, i32 3, i64 0
- %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
- store <8 x i32> %splat, ptr %a
+ store <8 x i32> splat (i32 3), ptr %a
ret void
}
@@ -656,9 +650,7 @@ define void @splat_imm_v4i64(ptr %a) {
; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI27_0]
; NONEON-NOSVE-NEXT: stp q0, q0, [x0]
; NONEON-NOSVE-NEXT: ret
- %insert = insertelement <4 x i64> undef, i64 4, i64 0
- %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
- store <4 x i64> %splat, ptr %a
+ store <4 x i64> splat (i64 4), ptr %a
ret void
}
@@ -679,9 +671,7 @@ define void @splat_imm_v16f16(ptr %a) {
; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI28_0]
; NONEON-NOSVE-NEXT: stp q0, q0, [x0]
; NONEON-NOSVE-NEXT: ret
- %insert = insertelement <16 x half> undef, half 5.0, i64 0
- %splat = shufflevector <16 x half> %insert, <16 x half> undef, <16 x i32> zeroinitializer
- store <16 x half> %splat, ptr %a
+ store <16 x half> splat (half 5.0), ptr %a
ret void
}
@@ -698,9 +688,7 @@ define void @splat_imm_v8f32(ptr %a) {
; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI29_0]
; NONEON-NOSVE-NEXT: stp q0, q0, [x0]
; NONEON-NOSVE-NEXT: ret
- %insert = insertelement <8 x float> undef, float 6.0, i64 0
- %splat = shufflevector <8 x float> %insert, <8 x float> undef, <8 x i32> zeroinitializer
- store <8 x float> %splat, ptr %a
+ store <8 x float> splat (float 6.0), ptr %a
ret void
}
@@ -717,8 +705,6 @@ define void @splat_imm_v4f64(ptr %a) {
; NONEON-NOSVE-NEXT: ldr q0, [x8, :lo12:.LCPI30_0]
; NONEON-NOSVE-NEXT: stp q0, q0, [x0]
; NONEON-NOSVE-NEXT: ret
- %insert = insertelement <4 x double> undef, double 7.0, i64 0
- %splat = shufflevector <4 x double> %insert, <4 x double> undef, <4 x i32> zeroinitializer
- store <4 x double> %splat, ptr %a
+ store <4 x double> splat (double 7.0), ptr %a
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll b/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
index a4f009b289b71..f16b6a4d50bca 100644
--- a/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
@@ -6,8 +6,7 @@ define <vscale x 16 x i8> @sel_8_positive(<vscale x 16 x i1> %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.b, p0/z, #3 // =0x3
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 3, i32 0), <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i32> zeroinitializer
- %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %vec, <vscale x 16 x i8> zeroinitializer
+ %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> splat (i8 3), <vscale x 16 x i8> zeroinitializer
ret <vscale x 16 x i8> %sel
}
@@ -16,8 +15,7 @@ define <vscale x 8 x i16> @sel_16_positive(<vscale x 8 x i1> %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.h, p0/z, #3 // =0x3
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 3, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> zeroinitializer
+ %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 3), <vscale x 8 x i16> zeroinitializer
ret <vscale x 8 x i16> %sel
}
@@ -26,8 +24,7 @@ define <vscale x 4 x i32> @sel_32_positive(<vscale x 4 x i1> %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.s, p0/z, #3 // =0x3
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> zeroinitializer
+ %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x i32> %sel
}
@@ -36,8 +33,7 @@ define <vscale x 2 x i64> @sel_64_positive(<vscale x 2 x i1> %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, p0/z, #3 // =0x3
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 3, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> zeroinitializer
+ %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 3), <vscale x 2 x i64> zeroinitializer
ret <vscale x 2 x i64> %sel
}
@@ -46,8 +42,7 @@ define <vscale x 16 x i8> @sel_8_negative(<vscale x 16 x i1> %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.b, p0/z, #-128 // =0xffffffffffffff80
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 -128, i32 0), <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i32> zeroinitializer
- %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %vec, <vscale x 16 x i8> zeroinitializer
+ %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> zeroinitializer
ret <vscale x 16 x i8> %sel
}
@@ -56,8 +51,7 @@ define <vscale x 8 x i16> @sel_16_negative(<vscale x 8 x i1> %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.h, p0/z, #-128 // =0xffffffffffffff80
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -128, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> zeroinitializer
+ %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 -128), <vscale x 8 x i16> zeroinitializer
ret <vscale x 8 x i16> %sel
}
@@ -66,8 +60,7 @@ define <vscale x 4 x i32> @sel_32_negative(<vscale x 4 x i1> %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.s, p0/z, #-128 // =0xffffffffffffff80
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 -128, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> zeroinitializer
+ %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 -128), <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x i32> %sel
}
@@ -76,8 +69,7 @@ define <vscale x 2 x i64> @sel_64_negative(<vscale x 2 x i1> %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, p0/z, #-128 // =0xffffffffffffff80
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 -128, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> zeroinitializer
+ %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 -128), <vscale x 2 x i64> zeroinitializer
ret <vscale x 2 x i64> %sel
}
@@ -86,8 +78,7 @@ define <vscale x 8 x i16> @sel_16_shifted(<vscale x 8 x i1> %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.h, p0/z, #512 // =0x200
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 512, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> zeroinitializer
+ %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 512), <vscale x 8 x i16> zeroinitializer
ret <vscale x 8 x i16> %sel
}
@@ -96,8 +87,7 @@ define <vscale x 4 x i32> @sel_32_shifted(<vscale x 4 x i1> %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.s, p0/z, #512 // =0x200
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 512, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> zeroinitializer
+ %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 512), <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x i32> %sel
}
@@ -106,8 +96,7 @@ define <vscale x 2 x i64> @sel_64_shifted(<vscale x 2 x i1> %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, p0/z, #512 // =0x200
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 512, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> zeroinitializer
+ %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 512), <vscale x 2 x i64> zeroinitializer
ret <vscale x 2 x i64> %sel
}
@@ -122,8 +111,7 @@ define <vscale x 8 x i16> @sel_16_illegal_wrong_extension(<vscale x 8 x i1> %p)
; CHECK-NEXT: mov z1.h, #0 // =0x0
; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 128, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> zeroinitializer
+ %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 128), <vscale x 8 x i16> zeroinitializer
ret <vscale x 8 x i16> %sel
}
@@ -134,8 +122,7 @@ define <vscale x 4 x i32> @sel_32_illegal_wrong_extension(<vscale x 4 x i1> %p)
; CHECK-NEXT: mov z1.s, #0 // =0x0
; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 128, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> zeroinitializer
+ %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 128), <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x i32> %sel
}
@@ -146,8 +133,7 @@ define <vscale x 2 x i64> @sel_64_illegal_wrong_extension(<vscale x 2 x i1> %p)
; CHECK-NEXT: mov z1.d, #0 // =0x0
; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 128, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> zeroinitializer
+ %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 128), <vscale x 2 x i64> zeroinitializer
ret <vscale x 2 x i64> %sel
}
@@ -159,8 +145,7 @@ define <vscale x 8 x i16> @sel_16_illegal_shifted(<vscale x 8 x i1> %p) {
; CHECK-NEXT: mov z0.h, w8
; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 513, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> zeroinitializer
+ %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 513), <vscale x 8 x i16> zeroinitializer
ret <vscale x 8 x i16> %sel
}
@@ -172,8 +157,7 @@ define <vscale x 4 x i32> @sel_32_illegal_shifted(<vscale x 4 x i1> %p) {
; CHECK-NEXT: mov z0.s, w8
; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 513, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> zeroinitializer
+ %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 513), <vscale x 4 x i32> zeroinitializer
ret <vscale x 4 x i32> %sel
}
@@ -185,8 +169,7 @@ define <vscale x 2 x i64> @sel_64_illegal_shifted(<vscale x 2 x i1> %p) {
; CHECK-NEXT: mov z0.d, x8
; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 513, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> zeroinitializer
+ %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 513), <vscale x 2 x i64> zeroinitializer
ret <vscale x 2 x i64> %sel
}
@@ -195,8 +178,7 @@ define <vscale x 16 x i8> @sel_merge_8_positive(<vscale x 16 x i1> %p, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.b, p0/m, #3 // =0x3
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 3, i32 0), <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i32> zeroinitializer
- %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %vec, <vscale x 16 x i8> %in
+ %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> splat (i8 3), <vscale x 16 x i8> %in
ret <vscale x 16 x i8> %sel
}
@@ -205,8 +187,7 @@ define <vscale x 8 x i16> @sel_merge_16_positive(<vscale x 8 x i1> %p, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.h, p0/m, #3 // =0x3
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 3, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> %in
+ %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 3), <vscale x 8 x i16> %in
ret <vscale x 8 x i16> %sel
}
@@ -215,8 +196,7 @@ define <vscale x 4 x i32> @sel_merge_32_positive(<vscale x 4 x i1> %p, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.s, p0/m, #3 // =0x3
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> %in
+ %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> %in
ret <vscale x 4 x i32> %sel
}
@@ -225,8 +205,7 @@ define <vscale x 2 x i64> @sel_merge_64_positive(<vscale x 2 x i1> %p, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, p0/m, #3 // =0x3
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 3, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> %in
+ %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 3), <vscale x 2 x i64> %in
ret <vscale x 2 x i64> %sel
}
@@ -235,8 +214,7 @@ define <vscale x 16 x i8> @sel_merge_8_negative(<vscale x 16 x i1> %p, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.b, p0/m, #-128 // =0xffffffffffffff80
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 -128, i32 0), <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i32> zeroinitializer
- %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %vec, <vscale x 16 x i8> %in
+ %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> %in
ret <vscale x 16 x i8> %sel
}
@@ -245,8 +223,7 @@ define <vscale x 8 x i16> @sel_merge_16_negative(<vscale x 8 x i1> %p, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.h, p0/m, #-128 // =0xffffffffffffff80
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -128, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> %in
+ %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 -128), <vscale x 8 x i16> %in
ret <vscale x 8 x i16> %sel
}
@@ -255,8 +232,7 @@ define <vscale x 4 x i32> @sel_merge_32_negative(<vscale x 4 x i1> %p, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.s, p0/m, #-128 // =0xffffffffffffff80
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 -128, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> %in
+ %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 -128), <vscale x 4 x i32> %in
ret <vscale x 4 x i32> %sel
}
@@ -265,8 +241,7 @@ define <vscale x 2 x i64> @sel_merge_64_negative(<vscale x 2 x i1> %p, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, p0/m, #-128 // =0xffffffffffffff80
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 -128, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> %in
+ %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 -128), <vscale x 2 x i64> %in
ret <vscale x 2 x i64> %sel
}
@@ -367,8 +342,7 @@ define <vscale x 8 x half> @sel_merge_nxv8f16_negative_zero(<vscale x 8 x i1> %p
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: mov z0.h, p0/m, z1.h
; CHECK-NEXT: ret
-%vec = shufflevector <vscale x 8 x half> insertelement (<vscale x 8 x half> undef, half -0.0, i32 0), <vscale x 8 x half> zeroinitializer, <vscale x 8 x i32> zeroinitializer
-%sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> %vec, <vscale x 8 x half> %in
+%sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> splat (half -0.0), <vscale x 8 x half> %in
ret <vscale x 8 x half> %sel
}
@@ -379,8 +353,7 @@ define <vscale x 4 x half> @sel_merge_nx4f16_negative_zero(<vscale x 4 x i1> %p,
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: mov z0.s, p0/m, z1.s
; CHECK-NEXT: ret
-%vec = shufflevector <vscale x 4 x half> insertelement (<vscale x 4 x half> undef, half -0.0, i32 0), <vscale x 4 x half> zeroinitializer, <vscale x 4 x i32> zeroinitializer
-%sel = select <vscale x 4 x i1> %p, <vscale x 4 x half> %vec, <vscale x 4 x half> %in
+%sel = select <vscale x 4 x i1> %p, <vscale x 4 x half> splat (half -0.0), <vscale x 4 x half> %in
ret <vscale x 4 x half> %sel
}
@@ -391,8 +364,7 @@ define <vscale x 2 x half> @sel_merge_nx2f16_negative_zero(<vscale x 2 x i1> %p,
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: mov z0.d, p0/m, z1.d
; CHECK-NEXT: ret
-%vec = shufflevector <vscale x 2 x half> insertelement (<vscale x 2 x half> undef, half -0.0, i32 0), <vscale x 2 x half> zeroinitializer, <vscale x 2 x i32> zeroinitializer
-%sel = select <vscale x 2 x i1> %p, <vscale x 2 x half> %vec, <vscale x 2 x half> %in
+%sel = select <vscale x 2 x i1> %p, <vscale x 2 x half> splat (half -0.0), <vscale x 2 x half> %in
ret <vscale x 2 x half> %sel
}
@@ -403,8 +375,7 @@ define <vscale x 4 x float> @sel_merge_nx4f32_negative_zero(<vscale x 4 x i1> %p
; CHECK-NEXT: mov z1.s, w8
; CHECK-NEXT: mov z0.s, p0/m, z1.s
; CHECK-NEXT: ret
-%vec = shufflevector <vscale x 4 x float> insertelement (<vscale x 4 x float> undef, float -0.0, i32 0), <vscale x 4 x float> zeroinitializer, <vscale x 4 x i32> zeroinitializer
-%sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %vec, <vscale x 4 x float> %in
+%sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> splat (float -0.0), <vscale x 4 x float> %in
ret <vscale x 4 x float> %sel
}
@@ -415,8 +386,7 @@ define <vscale x 2 x float> @sel_merge_nx2f32_negative_zero(<vscale x 2 x i1> %p
; CHECK-NEXT: mov z1.s, w8
; CHECK-NEXT: mov z0.d, p0/m, z1.d
; CHECK-NEXT: ret
-%vec = shufflevector <vscale x 2 x float> insertelement (<vscale x 2 x float> undef, float -0.0, i32 0), <vscale x 2 x float> zeroinitializer, <vscale x 2 x i32> zeroinitializer
-%sel = select <vscale x 2 x i1> %p, <vscale x 2 x float> %vec, <vscale x 2 x float> %in
+%sel = select <vscale x 2 x i1> %p, <vscale x 2 x float> splat (float -0.0), <vscale x 2 x float> %in
ret <vscale x 2 x float> %sel
}
@@ -427,8 +397,7 @@ define <vscale x 2 x double> @sel_merge_nx2f64_negative_zero(<vscale x 2 x i1> %
; CHECK-NEXT: mov z1.d, x8
; CHECK-NEXT: mov z0.d, p0/m, z1.d
; CHECK-NEXT: ret
-%vec = shufflevector <vscale x 2 x double> insertelement (<vscale x 2 x double> undef, double -0.0, i32 0), <vscale x 2 x double> zeroinitializer, <vscale x 2 x i32> zeroinitializer
-%sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %vec, <vscale x 2 x double> %in
+%sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> splat (double -0.0), <vscale x 2 x double> %in
ret <vscale x 2 x double> %sel
}
@@ -437,8 +406,7 @@ define <vscale x 8 x i16> @sel_merge_16_shifted(<vscale x 8 x i1> %p, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.h, p0/m, #512 // =0x200
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 512, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> %in
+ %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 512), <vscale x 8 x i16> %in
ret <vscale x 8 x i16> %sel
}
@@ -447,8 +415,7 @@ define <vscale x 4 x i32> @sel_merge_32_shifted(<vscale x 4 x i1> %p, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.s, p0/m, #512 // =0x200
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 512, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> %in
+ %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 512), <vscale x 4 x i32> %in
ret <vscale x 4 x i32> %sel
}
@@ -457,8 +424,7 @@ define <vscale x 2 x i64> @sel_merge_64_shifted(<vscale x 2 x i1> %p, <vscale x
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, p0/m, #512 // =0x200
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 512, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> %in
+ %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 512), <vscale x 2 x i64> %in
ret <vscale x 2 x i64> %sel
}
@@ -472,8 +438,7 @@ define <vscale x 8 x i16> @sel_merge_16_illegal_wrong_extension(<vscale x 8 x i1
; CHECK-NEXT: mov z1.h, #128 // =0x80
; CHECK-NEXT: mov z0.h, p0/m, z1.h
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 128, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> %in
+ %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 128), <vscale x 8 x i16> %in
ret <vscale x 8 x i16> %sel
}
@@ -483,8 +448,7 @@ define <vscale x 4 x i32> @sel_merge_32_illegal_wrong_extension(<vscale x 4 x i1
; CHECK-NEXT: mov z1.s, #128 // =0x80
; CHECK-NEXT: mov z0.s, p0/m, z1.s
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 128, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> %in
+ %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 128), <vscale x 4 x i32> %in
ret <vscale x 4 x i32> %sel
}
@@ -494,8 +458,7 @@ define <vscale x 2 x i64> @sel_merge_64_illegal_wrong_extension(<vscale x 2 x i1
; CHECK-NEXT: mov z1.d, #128 // =0x80
; CHECK-NEXT: mov z0.d, p0/m, z1.d
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 128, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> %in
+ %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 128), <vscale x 2 x i64> %in
ret <vscale x 2 x i64> %sel
}
@@ -506,8 +469,7 @@ define <vscale x 8 x i16> @sel_merge_16_illegal_shifted(<vscale x 8 x i1> %p, <v
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: mov z0.h, p0/m, z1.h
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 513, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> %in
+ %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> splat (i16 513), <vscale x 8 x i16> %in
ret <vscale x 8 x i16> %sel
}
@@ -518,8 +480,7 @@ define <vscale x 4 x i32> @sel_merge_32_illegal_shifted(<vscale x 4 x i1> %p, <v
; CHECK-NEXT: mov z1.s, w8
; CHECK-NEXT: mov z0.s, p0/m, z1.s
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 513, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> %in
+ %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> splat (i32 513), <vscale x 4 x i32> %in
ret <vscale x 4 x i32> %sel
}
@@ -530,7 +491,6 @@ define <vscale x 2 x i64> @sel_merge_64_illegal_shifted(<vscale x 2 x i1> %p, <v
; CHECK-NEXT: mov z1.d, x8
; CHECK-NEXT: mov z0.d, p0/m, z1.d
; CHECK-NEXT: ret
- %vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 513, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> %in
+ %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> splat (i64 513), <vscale x 2 x i64> %in
ret <vscale x 2 x i64> %sel
}
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