[llvm] AMDGPU: Enable RELA for PAL target (PR #128516)

[via llvm-commits]

https://github.com/MarcoCastorina created https://github.com/llvm/llvm-project/pull/128516

This fixes the generation of dwarf data for this target.

>From 57de5ae8b82aa7a5dbfc84f94ed3d30bf1e6a0df Mon Sep 17 00:00:00 2001
From: "Castorina, Marco" <marco.castorina at amd.com>
Date: Mon, 24 Feb 2025 13:14:59 +0000
Subject: [PATCH] Enable RELA for PAL target

---
 llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
index 8c4314e6d6cc4..477f840d0f4be 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
@@ -239,7 +239,8 @@ class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
 public:
   ELFAMDGPUAsmBackend(const Target &T, const Triple &TT)
       : AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
-        HasRelocationAddend(TT.getOS() == Triple::AMDHSA) {
+        HasRelocationAddend(TT.getOS() == Triple::AMDHSA ||
+                            TT.getOS() == Triple::AMDPAL) {
     switch (TT.getOS()) {
     case Triple::AMDHSA:
       OSABI = ELF::ELFOSABI_AMDGPU_HSA;