[llvm] [AMDGPU] Avoid repeated hash lookups (NFC) (PR #129189)

[Kazu Hirata via llvm-commits]

https://github.com/kazutakahirata created https://github.com/llvm/llvm-project/pull/129189

None

>From 8aa81ea7c55376a5b9abf4b12fabe28559722951 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Thu, 27 Feb 2025 01:54:57 -0800
Subject: [PATCH] [AMDGPU] Avoid repeated hash lookups (NFC)

---
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index f293b3aba7b79..33018ae9677a3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -314,18 +314,20 @@ RegBankLegalizeRules::getRulesForOpc(MachineInstr &MI) const {
       Opc == AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS ||
       Opc == AMDGPU::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) {
     unsigned IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
-    if (!IRulesAlias.contains(IntrID)) {
+    auto IRAIt = IRulesAlias.find(IntrID);
+    if (IRAIt == IRulesAlias.end()) {
       LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
       llvm_unreachable("No rules defined for intrinsic opcode");
     }
-    return IRules.at(IRulesAlias.at(IntrID));
+    return IRules.at(IRAIt->second);
   }
 
-  if (!GRulesAlias.contains(Opc)) {
+  auto GRAIt = GRulesAlias.find(Opc);
+  if (GRAIt == GRulesAlias.end()) {
     LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
     llvm_unreachable("No rules defined for generic opcode");
   }
-  return GRules.at(GRulesAlias.at(Opc));
+  return GRules.at(GRAIt->second);
 }
 
 // Syntactic sugar wrapper for predicate lambda that enables '&&', '||' and '!'.