[llvm] [AMDGPU][True16][CodeGen] optimize codengen for mad-mix in true16 (PR #124995)
Brox Chen via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 27 10:46:03 PST 2025
https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/124995
>From 2a27a8518237754c05983cb73ce027225ccfcbb5 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Wed, 29 Jan 2025 17:20:01 -0500
Subject: [PATCH] madmixpat update for true16
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 4 +
.../AMDGPU/AMDGPUInstructionSelector.cpp | 8 +
.../CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll | 3160 +++++++++++++----
llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll | 163 +-
llvm/test/CodeGen/AMDGPU/mad-mix.ll | 165 +-
5 files changed, 2674 insertions(+), 826 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 8e90754103ff1..57cf206a025ec 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -3651,6 +3651,10 @@ bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src,
// TODO: Should we try to look for neg/abs here?
}
+ // Prevent unnecessary subreg COPY to VGPR_16
+ if (Subtarget->useRealTrue16Insts() && Src.getOpcode() == ISD::TRUNCATE) {
+ Src = Src.getOperand(0);
+ }
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index a787c10a9421c..479caec2aa628 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -5841,6 +5841,14 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
CheckAbsNeg();
}
+ // Since we looked through FPEXT and removed it, we must also remove
+ // G_TRUNC. G_TRUNC to 16-bits would have a destination in RC VGPR_16, which
+ // is not compatible with MadMix instructions
+ Register PeekSrc = Src;
+ if (Subtarget->useRealTrue16Insts() &&
+ mi_match(PeekSrc, *MRI, m_GTrunc(m_Reg(PeekSrc))))
+ Src = PeekSrc;
+
Matched = true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
index 5ba036c386a40..e7dafb94c8829 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
@@ -9,11 +9,13 @@
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9,GFX9-IEEE %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9,GFX9-FLUSH %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-IEEE %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-FLUSH %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-IEEE %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FLUSH %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+real-true16 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-IEEE,GFX11-IEEE-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=-real-true16 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-IEEE,GFX11-IEEE-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+real-true16 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-FLUSH,GFX11-FLUSH-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=-real-true16 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-FLUSH,GFX11-FLUSH-FAKE16 %s
define half @v_fdiv_f16(half %a, half %b) {
; GFX6-IEEE-LABEL: v_fdiv_f16:
@@ -168,23 +170,77 @@ define half @v_fdiv_f16(half %a, half %b) {
; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0
-; GFX11-NEXT: v_rcp_f32_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v3, v3, v2
-; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v2
-; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_mul_f32_e32 v2, v4, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v2
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT: v_div_fixup_f16 v0, v2, v1, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_fdiv_f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v2, v4, v2
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.h, v1.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_fdiv_f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v1
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v2, v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v1, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_fdiv_f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v2, v4, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.h, v1.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_fdiv_f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v2, v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v1, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv half %a, %b
ret half %fdiv
}
@@ -214,13 +270,37 @@ define half @v_fdiv_f16_afn(half %a, half %b) {
; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_f16_afn:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_fdiv_f16_afn:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v1.l
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_fdiv_f16_afn:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_fdiv_f16_afn:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_fdiv_f16_afn:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn half %a, %b
ret half %fdiv
}
@@ -378,23 +458,77 @@ define half @v_fdiv_f16_ulp25(half %a, half %b) {
; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_f16_ulp25:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0
-; GFX11-NEXT: v_rcp_f32_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v3, v3, v2
-; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v2
-; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_mul_f32_e32 v2, v4, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v2
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT: v_div_fixup_f16 v0, v2, v1, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_fdiv_f16_ulp25:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v2, v4, v2
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.h, v1.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_fdiv_f16_ulp25:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v1
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v2, v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v1, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_fdiv_f16_ulp25:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v2, v4, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.h, v1.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_fdiv_f16_ulp25:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v2, v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v1, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv half %a, %b
ret half %fdiv
}
@@ -447,11 +581,35 @@ define half @v_neg_rcp_f16(half %x) {
; GFX89-NEXT: v_rcp_f16_e64 v0, -v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10PLUS-LABEL: v_neg_rcp_f16:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_rcp_f16_e64 v0, -v0
-; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_neg_rcp_f16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-TRUE16-LABEL: v_neg_rcp_f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_neg_rcp_f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_neg_rcp_f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_neg_rcp_f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv half -1.0, %x
ret half %fdiv
}
@@ -504,11 +662,35 @@ define half @v_rcp_f16(half %x) {
; GFX89-NEXT: v_rcp_f16_e32 v0, v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10PLUS-LABEL: v_rcp_f16:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_rcp_f16_e32 v0, v0
-; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_rcp_f16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f16_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-TRUE16-LABEL: v_rcp_f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rcp_f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rcp_f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rcp_f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv half 1.0, %x
ret half %fdiv
}
@@ -561,11 +743,35 @@ define half @v_rcp_f16_arcp(half %x) {
; GFX89-NEXT: v_rcp_f16_e32 v0, v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10PLUS-LABEL: v_rcp_f16_arcp:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_rcp_f16_e32 v0, v0
-; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_rcp_f16_arcp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f16_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-TRUE16-LABEL: v_rcp_f16_arcp:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rcp_f16_arcp:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rcp_f16_arcp:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rcp_f16_arcp:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp half 1.0, %x
ret half %fdiv
}
@@ -587,11 +793,35 @@ define half @v_rcp_f16_arcp_afn(half %x) {
; GFX89-NEXT: v_rcp_f16_e32 v0, v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10PLUS-LABEL: v_rcp_f16_arcp_afn:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_rcp_f16_e32 v0, v0
-; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_rcp_f16_arcp_afn:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f16_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-TRUE16-LABEL: v_rcp_f16_arcp_afn:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rcp_f16_arcp_afn:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rcp_f16_arcp_afn:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rcp_f16_arcp_afn:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp afn half 1.0, %x
ret half %fdiv
}
@@ -644,11 +874,35 @@ define half @v_rcp_f16_ulp25(half %x) {
; GFX89-NEXT: v_rcp_f16_e32 v0, v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10PLUS-LABEL: v_rcp_f16_ulp25:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_rcp_f16_e32 v0, v0
-; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_rcp_f16_ulp25:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f16_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-TRUE16-LABEL: v_rcp_f16_ulp25:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rcp_f16_ulp25:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rcp_f16_ulp25:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rcp_f16_ulp25:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv half 1.0, %x
ret half %fdiv
}
@@ -678,13 +932,37 @@ define half @v_fdiv_f16_afn_ulp25(half %a, half %b) {
; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_f16_afn_ulp25:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_fdiv_f16_afn_ulp25:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v1.l
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_fdiv_f16_afn_ulp25:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_fdiv_f16_afn_ulp25:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_fdiv_f16_afn_ulp25:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn half %a, %b
ret half %fdiv
}
@@ -745,13 +1023,37 @@ define half @v_fdiv_f16_arcp_ulp25(half %a, half %b) {
; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_f16_arcp_ulp25:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_fdiv_f16_arcp_ulp25:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v1.l
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_fdiv_f16_arcp_ulp25:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_fdiv_f16_arcp_ulp25:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_fdiv_f16_arcp_ulp25:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp half %a, %b
ret half %fdiv
}
@@ -1040,34 +1342,129 @@ define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {
; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_v2f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v6, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v2
-; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: v_cvt_f32_f16_e32 v7, v5
-; GFX11-NEXT: v_rcp_f32_e32 v4, v4
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v4
-; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_fmac_f32 v6, v8, v3 :: v_dual_fmac_f32 v7, v9, v4
-; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_mul_f32 v4, v9, v4
-; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX11-NEXT: v_dual_add_f32 v3, v3, v6 :: v_dual_and_b32 v4, 0xff800000, v4
-; GFX11-NEXT: v_add_f32_e32 v4, v4, v7
-; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT: v_cvt_f16_f32_e32 v4, v4
-; GFX11-NEXT: v_div_fixup_f16 v0, v3, v1, v0
-; GFX11-NEXT: v_div_fixup_f16 v1, v4, v2, v5
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_fdiv_v2f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v7.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v4, v4, v2
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v6, v6, v3
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v10, -v5, v4, v7 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v11, -v8, v6, v9 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v4, v10, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v6, v11, v3
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v4, v7 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v7, -v8, v6, v9 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_dual_mul_f32 v2, v5, v2 :: v_dual_mul_f32 v3, v7, v3
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-IEEE-TRUE16-NEXT: v_dual_add_f32 v2, v2, v4 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.h, v3
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v2.l, v1.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.h, v2.h, v1.h, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_fdiv_v2f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v4, v4
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v4
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_fmac_f32 v6, v8, v3 :: v_dual_fmac_f32 v7, v9, v4
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_mul_f32 v4, v9, v4
+; GFX11-IEEE-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-IEEE-FAKE16-NEXT: v_dual_add_f32 v3, v3, v6 :: v_dual_and_b32 v4, 0xff800000, v4
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v4, v4, v7
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v3, v1, v0
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v1, v4, v2, v5
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_fdiv_v2f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v7.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v4, v4, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v6, v6, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v10, -v5, v4, v7 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v11, -v8, v6, v9 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v4, v10, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v6, v11, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v4, v7 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v7, -v8, v6, v9 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_mul_f32 v2, v5, v2 :: v_dual_mul_f32 v3, v7, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_add_f32 v2, v2, v4 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.h, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v2.l, v1.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.h, v2.h, v1.h, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_fdiv_v2f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v4, v4
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_fmac_f32 v6, v8, v3 :: v_dual_fmac_f32 v7, v9, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_mul_f32 v4, v9, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_add_f32 v3, v3, v6 :: v_dual_and_b32 v4, 0xff800000, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v4, v4, v7
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v3, v1, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v1, v4, v2, v5
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv <2 x half> %a, %b
ret <2 x half> %fdiv
}
@@ -1118,18 +1515,53 @@ define <2 x half> @v_fdiv_v2f16_afn(<2 x half> %a, <2 x half> %b) {
; GFX10-NEXT: v_pack_b32_f16 v0, v2, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_v2f16_afn:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT: v_rcp_f16_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT: v_mul_f16_e32 v1, v3, v2
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_fdiv_v2f16_afn:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v1.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v1.h, v1.h
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.h, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_fdiv_v2f16_afn:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v1, v3, v2
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_fdiv_v2f16_afn:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v1.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v1.h, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.h, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_fdiv_v2f16_afn:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v1, v3, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn <2 x half> %a, %b
ret <2 x half> %fdiv
}
@@ -1418,34 +1850,129 @@ define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_v2f16_ulp25:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v6, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v2
-; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: v_cvt_f32_f16_e32 v7, v5
-; GFX11-NEXT: v_rcp_f32_e32 v4, v4
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v4
-; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_fmac_f32 v6, v8, v3 :: v_dual_fmac_f32 v7, v9, v4
-; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_mul_f32 v4, v9, v4
-; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX11-NEXT: v_dual_add_f32 v3, v3, v6 :: v_dual_and_b32 v4, 0xff800000, v4
-; GFX11-NEXT: v_add_f32_e32 v4, v4, v7
-; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT: v_cvt_f16_f32_e32 v4, v4
-; GFX11-NEXT: v_div_fixup_f16 v0, v3, v1, v0
-; GFX11-NEXT: v_div_fixup_f16 v1, v4, v2, v5
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_fdiv_v2f16_ulp25:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v7.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v4, v4, v2
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v6, v6, v3
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v10, -v5, v4, v7 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v11, -v8, v6, v9 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v4, v10, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v6, v11, v3
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v4, v7 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v7, -v8, v6, v9 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_dual_mul_f32 v2, v5, v2 :: v_dual_mul_f32 v3, v7, v3
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-IEEE-TRUE16-NEXT: v_dual_add_f32 v2, v2, v4 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.h, v3
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v2.l, v1.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.h, v2.h, v1.h, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_fdiv_v2f16_ulp25:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v4, v4
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v4
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_fmac_f32 v6, v8, v3 :: v_dual_fmac_f32 v7, v9, v4
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_mul_f32 v4, v9, v4
+; GFX11-IEEE-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-IEEE-FAKE16-NEXT: v_dual_add_f32 v3, v3, v6 :: v_dual_and_b32 v4, 0xff800000, v4
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v4, v4, v7
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v3, v1, v0
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v1, v4, v2, v5
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_fdiv_v2f16_ulp25:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v7.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v4, v4, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v6, v6, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v10, -v5, v4, v7 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v11, -v8, v6, v9 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v4, v10, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v6, v11, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v4, v7 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v7, -v8, v6, v9 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_mul_f32 v2, v5, v2 :: v_dual_mul_f32 v3, v7, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_add_f32 v2, v2, v4 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.h, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v2.l, v1.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.h, v2.h, v1.h, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_fdiv_v2f16_ulp25:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v5
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v4, v4
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_fmac_f32 v6, v8, v3 :: v_dual_fmac_f32 v7, v9, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_mul_f32 v4, v9, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_add_f32 v3, v3, v6 :: v_dual_and_b32 v4, 0xff800000, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v4, v4, v7
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v3, v1, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v1, v4, v2, v5
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv <2 x half> %a, %b
ret <2 x half> %fdiv
}
@@ -1721,34 +2248,123 @@ define <2 x half> @v_rcp_v2f16(<2 x half> %x) {
; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rcp_v2f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v4, 1.0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT: v_rcp_f32_e32 v2, v2
-; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v5, v4, v2
-; GFX11-NEXT: v_mul_f32_e32 v4, v4, v3
-; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v4, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v2
-; GFX11-NEXT: v_mul_f32_e32 v3, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
-; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
-; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_rcp_v2f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, 1.0
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v1
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v1
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_dual_mul_f32 v1, v4, v1 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-IEEE-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0xff800000, v1
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v1, v1, v6
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v2
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, 1.0
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.h, v1.h, v0.h, 1.0
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rcp_v2f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-IEEE-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rcp_v2f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_mul_f32 v1, v4, v1 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0xff800000, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v1, v1, v6
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.h, v1.h, v0.h, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rcp_v2f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x
ret <2 x half> %fdiv
}
@@ -2024,34 +2640,123 @@ define <2 x half> @v_neg_rcp_v2f16(<2 x half> %x) {
; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_neg_rcp_v2f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v4, -1.0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT: v_rcp_f32_e32 v2, v2
-; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v5, v4, v2
-; GFX11-NEXT: v_mul_f32_e32 v4, v4, v3
-; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v4, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v4, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v4, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v2
-; GFX11-NEXT: v_mul_f32_e32 v3, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
-; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
-; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_neg_rcp_v2f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, -1.0
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v1
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v1
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_dual_mul_f32 v1, v4, v1 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-IEEE-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0xff800000, v1
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v1, v1, v6
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v2
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, -1.0
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.h, v1.h, v0.h, -1.0
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_neg_rcp_v2f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, -1.0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-IEEE-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_neg_rcp_v2f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_mul_f32 v1, v4, v1 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0xff800000, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v1, v1, v6
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.h, v1.h, v0.h, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_neg_rcp_v2f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv <2 x half> <half -1.0, half -1.0>, %x
ret <2 x half> %fdiv
}
@@ -2343,36 +3048,133 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rcp_v2f16_fabs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_f16_e32 v5, 1.0
-; GFX11-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v6, v5, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v6, 1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v2
-; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v3
-; GFX11-NEXT: v_rcp_f32_e32 v4, v4
-; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v6, 1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v5, v5, v4
-; GFX11-NEXT: v_fma_mix_f32 v8, -|v0|, v5, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v5, v8, v4
-; GFX11-NEXT: v_fma_mix_f32 v0, -|v0|, v5, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_mul_f32 v3, v7, v3 :: v_dual_mul_f32 v0, v0, v4
-; GFX11-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX11-NEXT: v_dual_add_f32 v0, v0, v5 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_add_f32_e32 v3, v3, v6
-; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT: v_div_fixup_f16 v0, v0, v2, 1.0
-; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
-; GFX11-NEXT: v_pack_b32_f16 v0, v1, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_rcp_v2f16_fabs:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, 1.0
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v0
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v0
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v0, v4, v0
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v0, v0, v6
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v1.l, 1.0
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.h, v0.h, v1.h, 1.0
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rcp_v2f16_fabs:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v6, v5, v3
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v6, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v4, v4
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v5, v5, v4
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v8, -|v0|, v5, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v5, v8, v4
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, v5, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v3, v7, v3 :: v_dual_mul_f32 v0, v0, v4
+; GFX11-IEEE-FAKE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-IEEE-FAKE16-NEXT: v_dual_add_f32 v0, v0, v5 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v0, v2, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rcp_v2f16_fabs:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v0, v4, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v0, v0, v6
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v1.l, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.h, v0.h, v1.h, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rcp_v2f16_fabs:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v6, v5, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v6, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v4, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v5, v5, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v8, -|v0|, v5, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v5, v8, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, v5, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v3, v7, v3 :: v_dual_mul_f32 v0, v0, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_add_f32 v0, v0, v5 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v0, v2, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%x.fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
%fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x.fabs
ret <2 x half> %fdiv
@@ -2665,36 +3467,133 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_neg_rcp_v2f16_fabs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_f16_e32 v5, -1.0
-; GFX11-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v6, v5, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v6, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v2
-; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v3
-; GFX11-NEXT: v_rcp_f32_e32 v4, v4
-; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v6, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v5, v5, v4
-; GFX11-NEXT: v_fma_mix_f32 v8, -|v0|, v5, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v5, v8, v4
-; GFX11-NEXT: v_fma_mix_f32 v0, -|v0|, v5, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_mul_f32 v3, v7, v3 :: v_dual_mul_f32 v0, v0, v4
-; GFX11-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX11-NEXT: v_dual_add_f32 v0, v0, v5 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_add_f32_e32 v3, v3, v6
-; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT: v_div_fixup_f16 v0, v0, v2, -1.0
-; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
-; GFX11-NEXT: v_pack_b32_f16 v0, v1, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_neg_rcp_v2f16_fabs:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, -1.0
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v0
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v0
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v0, v4, v0
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v0, v0, v6
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v1.l, -1.0
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.h, v0.h, v1.h, -1.0
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_neg_rcp_v2f16_fabs:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, -1.0
+; GFX11-IEEE-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v6, v5, v3
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v6, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v4, v4
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v5, v5, v4
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v8, -|v0|, v5, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v5, v8, v4
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, v5, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v3, v7, v3 :: v_dual_mul_f32 v0, v0, v4
+; GFX11-IEEE-FAKE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-IEEE-FAKE16-NEXT: v_dual_add_f32 v0, v0, v5 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v0, v2, -1.0
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_neg_rcp_v2f16_fabs:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v0, v4, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v0, v0, v6
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v1.l, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.h, v0.h, v1.h, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_neg_rcp_v2f16_fabs:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v6, v5, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v6, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v4, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v5, v5, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v8, -|v0|, v5, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v5, v8, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, v5, -1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v3, v7, v3 :: v_dual_mul_f32 v0, v0, v4
+; GFX11-FLUSH-FAKE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_add_f32 v0, v0, v5 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v0, v2, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%x.fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
%fdiv = fdiv <2 x half> <half -1.0, half -1.0>, %x.fabs
ret <2 x half> %fdiv
@@ -2795,15 +3694,43 @@ define <2 x half> @v_rcp_v2f16_arcp(<2 x half> %x) {
; GFX10-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rcp_v2f16_arcp:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT: v_rcp_f16_e32 v0, v0
-; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_rcp_v2f16_arcp:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rcp_v2f16_arcp:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rcp_v2f16_arcp:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rcp_v2f16_arcp:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp <2 x half> <half 1.0, half 1.0>, %x
ret <2 x half> %fdiv
}
@@ -2847,15 +3774,43 @@ define <2 x half> @v_rcp_v2f16_arcp_afn(<2 x half> %x) {
; GFX10-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rcp_v2f16_arcp_afn:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT: v_rcp_f16_e32 v0, v0
-; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_rcp_v2f16_arcp_afn:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rcp_v2f16_arcp_afn:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rcp_v2f16_arcp_afn:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rcp_v2f16_arcp_afn:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp afn <2 x half> <half 1.0, half 1.0>, %x
ret <2 x half> %fdiv
}
@@ -3131,34 +4086,123 @@ define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {
; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rcp_v2f16_ulp25:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v4, 1.0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT: v_rcp_f32_e32 v2, v2
-; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v5, v4, v2
-; GFX11-NEXT: v_mul_f32_e32 v4, v4, v3
-; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v4, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v2
-; GFX11-NEXT: v_mul_f32_e32 v3, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
-; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
-; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_rcp_v2f16_ulp25:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, 1.0
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v1
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v1
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_dual_mul_f32 v1, v4, v1 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-IEEE-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0xff800000, v1
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v1, v1, v6
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v2
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, 1.0
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.h, v1.h, v0.h, 1.0
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rcp_v2f16_ulp25:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-IEEE-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rcp_v2f16_ulp25:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_mul_f32 v1, v4, v1 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0xff800000, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v1, v1, v6
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.h, v1.h, v0.h, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rcp_v2f16_ulp25:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v0, v4, 1.0 op_sel:[1,0,0] op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x
ret <2 x half> %fdiv
}
@@ -3209,18 +4253,53 @@ define <2 x half> @v_fdiv_v2f16_afn_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX10-NEXT: v_pack_b32_f16 v0, v2, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_v2f16_afn_ulp25:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT: v_rcp_f16_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT: v_mul_f16_e32 v1, v3, v2
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_fdiv_v2f16_afn_ulp25:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v1.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v1.h, v1.h
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.h, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_fdiv_v2f16_afn_ulp25:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v1, v3, v2
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_fdiv_v2f16_afn_ulp25:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v1.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v1.h, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.h, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_fdiv_v2f16_afn_ulp25:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v1, v3, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn <2 x half> %a, %b
ret <2 x half> %fdiv
}
@@ -3327,18 +4406,53 @@ define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX10-NEXT: v_pack_b32_f16 v0, v2, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_v2f16_arcp_ulp25:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT: v_rcp_f16_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT: v_mul_f16_e32 v1, v3, v2
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_fdiv_v2f16_arcp_ulp25:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v1.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v1.h, v1.h
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.h, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_fdiv_v2f16_arcp_ulp25:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v1, v3, v2
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_fdiv_v2f16_arcp_ulp25:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v1.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v1.h, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.h, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_fdiv_v2f16_arcp_ulp25:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v1, v3, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp <2 x half> %a, %b
ret <2 x half> %fdiv
}
@@ -3389,18 +4503,53 @@ define <2 x half> @v_fdiv_v2f16_arcp_afn_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX10-NEXT: v_pack_b32_f16 v0, v2, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT: v_rcp_f16_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT: v_mul_f16_e32 v1, v3, v2
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v1.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v1.h, v1.h
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.h, v1.h
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v1, v3, v2
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v1.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v1.h, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.h, v1.h
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v1, v3, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn arcp <2 x half> %a, %b
ret <2 x half> %fdiv
}
@@ -3562,23 +4711,77 @@ define amdgpu_ps i16 @s_fdiv_f16(i16 inreg %a.arg, i16 inreg %b.arg) {
; GFX10-FLUSH-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-FLUSH-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: s_fdiv_f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s0
-; GFX11-NEXT: v_rcp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v1, v1, v0
-; GFX11-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v1, v2, v0
-; GFX11-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
-; GFX11-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT: v_div_fixup_f16 v0, v0, s1, s0
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-IEEE-TRUE16-LABEL: s_fdiv_f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, s1
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, s0
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v1, v1, v0
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v1, v2, v0
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, s1, s0
+; GFX11-IEEE-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-IEEE-FAKE16-LABEL: s_fdiv_f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, s1
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, s0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v1, v1, v0
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v1, v2, v0
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-IEEE-FAKE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v0, s1, s0
+; GFX11-IEEE-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-TRUE16-LABEL: s_fdiv_f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, s1
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, s0
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v1, v1, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v1, v2, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, s1, s0
+; GFX11-FLUSH-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-FAKE16-LABEL: s_fdiv_f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, s1
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, s0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v1, v1, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v1, v2, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v0, s1, s0
+; GFX11-FLUSH-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-FAKE16-NEXT: ; return to shader part epilog
%a = bitcast i16 %a.arg to half
%b = bitcast i16 %b.arg to half
%fdiv = fdiv half %a, %b
@@ -3642,13 +4845,37 @@ define amdgpu_ps i16 @s_fdiv_f16_arcp(i16 inreg %a.arg, i16 inreg %b.arg) {
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: s_fdiv_f16_arcp:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_rcp_f16_e32 v0, s1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f16_e32 v0, s0, v0
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-IEEE-TRUE16-LABEL: s_fdiv_f16_arcp:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, s1
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.l, s0, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-IEEE-FAKE16-LABEL: s_fdiv_f16_arcp:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, s1
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v0, s0, v0
+; GFX11-IEEE-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-TRUE16-LABEL: s_fdiv_f16_arcp:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, s1
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, s0, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-FAKE16-LABEL: s_fdiv_f16_arcp:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, s1
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v0, s0, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-FAKE16-NEXT: ; return to shader part epilog
%a = bitcast i16 %a.arg to half
%b = bitcast i16 %b.arg to half
%fdiv = fdiv arcp half %a, %b
@@ -3681,13 +4908,37 @@ define amdgpu_ps i16 @s_fdiv_f16_afn(i16 inreg %a.arg, i16 inreg %b.arg) {
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: s_fdiv_f16_afn:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_rcp_f16_e32 v0, s1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f16_e32 v0, s0, v0
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-IEEE-TRUE16-LABEL: s_fdiv_f16_afn:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, s1
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f16_e32 v0.l, s0, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-IEEE-FAKE16-LABEL: s_fdiv_f16_afn:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, s1
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f16_e32 v0, s0, v0
+; GFX11-IEEE-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-TRUE16-LABEL: s_fdiv_f16_afn:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, s1
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, s0, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-FAKE16-LABEL: s_fdiv_f16_afn:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, s1
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f16_e32 v0, s0, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-FAKE16-NEXT: ; return to shader part epilog
%a = bitcast i16 %a.arg to half
%b = bitcast i16 %b.arg to half
%fdiv = fdiv afn half %a, %b
@@ -3995,34 +5246,101 @@ define amdgpu_ps i32 @s_fdiv_v2f16(i32 inreg %a.arg, i32 inreg %b.arg) {
; GFX10-FLUSH-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-FLUSH-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: s_fdiv_v2f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b32 s2, s1, 16
-; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s2
-; GFX11-NEXT: s_lshr_b32 s3, s0, 16
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, s0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, s3
-; GFX11-NEXT: v_rcp_f32_e32 v0, v0
-; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_dual_mul_f32 v2, v2, v0 :: v_dual_mul_f32 v3, v3, v1
-; GFX11-NEXT: v_fma_mix_f32 v4, -s1, v2, s0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v5, -s2, v3, s3 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_fmac_f32 v2, v4, v0 :: v_dual_fmac_f32 v3, v5, v1
-; GFX11-NEXT: v_fma_mix_f32 v4, -s1, v2, s0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v5, -s2, v3, s3 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_mul_f32 v0, v4, v0 :: v_dual_mul_f32 v1, v5, v1
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff800000, v1
-; GFX11-NEXT: v_dual_add_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xff800000, v0
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT: v_div_fixup_f16 v1, v1, s2, s3
-; GFX11-NEXT: v_div_fixup_f16 v0, v0, s1, s0
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-IEEE-TRUE16-LABEL: s_fdiv_v2f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, s1
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, s0
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v1, v1, v0
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v1, v2, v0
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, s1, s0
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-IEEE-FAKE16-LABEL: s_fdiv_v2f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, s1
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, s2
+; GFX11-IEEE-FAKE16-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, s0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, s3
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v2, v2, v0 :: v_dual_mul_f32 v3, v3, v1
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v4, -s1, v2, s0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v5, -s2, v3, s3 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_fmac_f32 v2, v4, v0 :: v_dual_fmac_f32 v3, v5, v1
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v4, -s1, v2, s0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v5, -s2, v3, s3 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v0, v4, v0 :: v_dual_mul_f32 v1, v5, v1
+; GFX11-IEEE-FAKE16-NEXT: v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-IEEE-FAKE16-NEXT: v_dual_add_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xff800000, v0
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v1, v1, s2, s3
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v0, s1, s0
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-TRUE16-LABEL: s_fdiv_v2f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, s1
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, s0
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v1, v1, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v1, v2, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, s1, s0
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-FAKE16-LABEL: s_fdiv_v2f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, s1
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, s2
+; GFX11-FLUSH-FAKE16-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, s0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, s3
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v2, v2, v0 :: v_dual_mul_f32 v3, v3, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v4, -s1, v2, s0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v5, -s2, v3, s3 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_fmac_f32 v2, v4, v0 :: v_dual_fmac_f32 v3, v5, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v4, -s1, v2, s0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v5, -s2, v3, s3 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v0, v4, v0 :: v_dual_mul_f32 v1, v5, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_add_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xff800000, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v1, v1, s2, s3
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v0, s1, s0
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-FAKE16-NEXT: ; return to shader part epilog
%a = bitcast i32 %a.arg to <2 x half>
%b = bitcast i32 %b.arg to <2 x half>
%fdiv = fdiv <2 x half> %a, %b
@@ -4084,12 +5402,33 @@ define amdgpu_ps i16 @s_rcp_f16(i16 inreg %a.arg) {
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: s_rcp_f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_rcp_f16_e32 v0, s0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-IEEE-TRUE16-LABEL: s_rcp_f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, s0
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-IEEE-FAKE16-LABEL: s_rcp_f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, s0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-TRUE16-LABEL: s_rcp_f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, s0
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-FAKE16-LABEL: s_rcp_f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, s0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-FAKE16-NEXT: ; return to shader part epilog
%a = bitcast i16 %a.arg to half
%fdiv = fdiv half 1.0, %a
%result = bitcast half %fdiv to i16
@@ -4150,12 +5489,33 @@ define amdgpu_ps i16 @s_neg_rcp_f16(i16 inreg %a.arg) {
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: s_neg_rcp_f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_rcp_f16_e64 v0, -s0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-IEEE-TRUE16-LABEL: s_neg_rcp_f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -s0
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-IEEE-FAKE16-LABEL: s_neg_rcp_f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e64 v0, -s0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-TRUE16-LABEL: s_neg_rcp_f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -s0
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-FAKE16-LABEL: s_neg_rcp_f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e64 v0, -s0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-FAKE16-NEXT: ; return to shader part epilog
%a = bitcast i16 %a.arg to half
%fdiv = fdiv half -1.0, %a
%result = bitcast half %fdiv to i16
@@ -4222,12 +5582,33 @@ define amdgpu_ps i16 @s_rsq_f16(i16 inreg %a.arg) {
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: s_rsq_f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_rsq_f16_e32 v0, s0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-IEEE-TRUE16-LABEL: s_rsq_f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: v_rsq_f16_e32 v0.l, s0
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-IEEE-FAKE16-LABEL: s_rsq_f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: v_rsq_f16_e32 v0, s0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-TRUE16-LABEL: s_rsq_f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: v_rsq_f16_e32 v0.l, s0
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-FAKE16-LABEL: s_rsq_f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: v_rsq_f16_e32 v0, s0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-FAKE16-NEXT: ; return to shader part epilog
%a = bitcast i16 %a.arg to half
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%fdiv = fdiv contract half 1.0, %sqrt
@@ -4525,37 +5906,131 @@ define amdgpu_ps i32 @s_rsq_v2f16(i32 inreg %a.arg) {
; GFX10-FLUSH-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-FLUSH-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: s_rsq_v2f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b32 s1, s0, 16
-; GFX11-NEXT: v_sqrt_f16_e32 v0, s0
-; GFX11-NEXT: v_sqrt_f16_e32 v1, s1
-; GFX11-NEXT: v_cvt_f32_f16_e32 v4, -1.0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT: v_rcp_f32_e32 v2, v2
-; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v5, v4, v2
-; GFX11-NEXT: v_mul_f32_e32 v4, v4, v3
-; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v4, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v2
-; GFX11-NEXT: v_mul_f32_e32 v3, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
-; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
-; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-IEEE-TRUE16-LABEL: s_rsq_v2f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, s0
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, -1.0
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v2, v2, v1
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v2, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fma_f32 v5, v5, v1, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v3, -v3, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v1
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v6, -v4, v2, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v2, v6, v1
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v3
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v2, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.h, v0.h, v0.l, -1.0
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v1, v4, v1
+; GFX11-IEEE-TRUE16-NEXT: v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, -1.0
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-IEEE-FAKE16-LABEL: s_rsq_v2f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v0, s0
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v1, s1
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, -1.0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-IEEE-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-IEEE-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-TRUE16-LABEL: s_rsq_v2f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, s0
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v2, v2, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v2, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_f32 v5, v5, v1, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v3, -v3, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v6, -v4, v2, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v2, v6, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v3
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v2, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.h, v0.h, v0.l, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v1, v4, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FLUSH-FAKE16-LABEL: s_rsq_v2f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v0, s0
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v1, s1
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FLUSH-FAKE16-NEXT: ; return to shader part epilog
%a = bitcast i32 %a.arg to <2 x half>
%sqrt = call contract <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)
%fdiv = fdiv contract <2 x half> <half -1.0, half -1.0>, %sqrt
@@ -4617,11 +6092,35 @@ define half @v_rsq_f16(half %a) {
; GFX89-NEXT: v_rsq_f16_e32 v0, v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10PLUS-LABEL: v_rsq_f16:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_rsq_f16_e32 v0, v0
-; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_rsq_f16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_rsq_f16_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-TRUE16-LABEL: v_rsq_f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rsq_f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rsq_f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rsq_f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%fdiv = fdiv contract half 1.0, %sqrt
ret half %fdiv
@@ -4689,13 +6188,37 @@ define half @v_neg_rsq_f16(half %a) {
; GFX10-NEXT: v_rcp_f16_e64 v0, -v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_neg_rsq_f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_neg_rsq_f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_neg_rsq_f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_neg_rsq_f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_neg_rsq_f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%fdiv = fdiv contract half -1.0, %sqrt
ret half %fdiv
@@ -4765,14 +6288,41 @@ define { half, half } @v_rsq_f16_multi_use(half %a) {
; GFX10-NEXT: v_mov_b32_e32 v0, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rsq_f16_multi_use:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e32 v2, v0
-; GFX11-NEXT: v_rsq_f16_e32 v1, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_rsq_f16_multi_use:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v2.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_rsq_f16_e32 v1.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rsq_f16_multi_use:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v2, v0
+; GFX11-IEEE-FAKE16-NEXT: v_rsq_f16_e32 v1, v0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rsq_f16_multi_use:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v2.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rsq_f16_e32 v1.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rsq_f16_multi_use:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v2, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_rsq_f16_e32 v1, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%insert.0 = insertvalue { half, half } poison, half %sqrt, 0
%fdiv = fdiv contract half 1.0, %sqrt
@@ -4842,13 +6392,37 @@ define half @v_rsq_f16_missing_contract0(half %a) {
; GFX10-NEXT: v_rcp_f16_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rsq_f16_missing_contract0:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_rcp_f16_e32 v0, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_rsq_f16_missing_contract0:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rsq_f16_missing_contract0:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rsq_f16_missing_contract0:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rsq_f16_missing_contract0:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call half @llvm.sqrt.f16(half %a)
%fdiv = fdiv contract half 1.0, %sqrt
ret half %fdiv
@@ -4916,13 +6490,37 @@ define half @v_rsq_f16_missing_contract1(half %a) {
; GFX10-NEXT: v_rcp_f16_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rsq_f16_missing_contract1:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_rcp_f16_e32 v0, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_rsq_f16_missing_contract1:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rsq_f16_missing_contract1:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rsq_f16_missing_contract1:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rsq_f16_missing_contract1:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%fdiv = fdiv half 1.0, %sqrt
ret half %fdiv
@@ -4990,13 +6588,37 @@ define half @v_neg_rsq_f16_missing_contract0(half %a) {
; GFX10-NEXT: v_rcp_f16_e64 v0, -v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_neg_rsq_f16_missing_contract0:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_neg_rsq_f16_missing_contract0:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_neg_rsq_f16_missing_contract0:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_neg_rsq_f16_missing_contract0:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_neg_rsq_f16_missing_contract0:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call half @llvm.sqrt.f16(half %a)
%fdiv = fdiv contract half -1.0, %sqrt
ret half %fdiv
@@ -5064,13 +6686,37 @@ define half @v_neg_rsq_f16_missing_contract1(half %a) {
; GFX10-NEXT: v_rcp_f16_e64 v0, -v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_neg_rsq_f16_missing_contract1:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_neg_rsq_f16_missing_contract1:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_neg_rsq_f16_missing_contract1:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_neg_rsq_f16_missing_contract1:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_neg_rsq_f16_missing_contract1:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%fdiv = fdiv half -1.0, %sqrt
ret half %fdiv
@@ -5138,13 +6784,37 @@ define half @v_neg_rsq_f16_fabs(half %a) {
; GFX10-NEXT: v_rcp_f16_e64 v0, -v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_neg_rsq_f16_fabs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e64 v0, |v0|
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_neg_rsq_f16_fabs:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e64 v0.l, |v0.l|
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_neg_rsq_f16_fabs:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e64 v0, |v0|
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_neg_rsq_f16_fabs:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e64 v0.l, |v0.l|
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_neg_rsq_f16_fabs:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e64 v0, |v0|
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%a.fabs = call half @llvm.fabs.f16(half %a)
%sqrt = call contract half @llvm.sqrt.f16(half %a.fabs)
%fdiv = fdiv contract half -1.0, %sqrt
@@ -5205,11 +6875,35 @@ define half @v_rsq_f16_arcp(half %a) {
; GFX89-NEXT: v_rsq_f16_e32 v0, v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10PLUS-LABEL: v_rsq_f16_arcp:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_rsq_f16_e32 v0, v0
-; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_rsq_f16_arcp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_rsq_f16_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-TRUE16-LABEL: v_rsq_f16_arcp:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rsq_f16_arcp:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rsq_f16_arcp:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rsq_f16_arcp:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%fdiv = fdiv contract arcp half 1.0, %sqrt
ret half %fdiv
@@ -5277,13 +6971,37 @@ define half @v_neg_rsq_f16_arcp(half %a) {
; GFX10-NEXT: v_rcp_f16_e64 v0, -v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_neg_rsq_f16_arcp:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_neg_rsq_f16_arcp:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_neg_rsq_f16_arcp:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_neg_rsq_f16_arcp:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_neg_rsq_f16_arcp:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e64 v0, -v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%fdiv = fdiv contract arcp half -1.0, %sqrt
ret half %fdiv
@@ -5309,11 +7027,35 @@ define half @v_rsq_f16_afn(half %a) {
; GFX89-NEXT: v_rsq_f16_e32 v0, v0
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10PLUS-LABEL: v_rsq_f16_afn:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_rsq_f16_e32 v0, v0
-; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_rsq_f16_afn:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_rsq_f16_e32 v0, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-TRUE16-LABEL: v_rsq_f16_afn:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rsq_f16_afn:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rsq_f16_afn:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rsq_f16_afn:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
%fdiv = fdiv afn contract half 1.0, %sqrt
ret half %fdiv
@@ -5347,13 +7089,37 @@ define half @v_rsq_f16_afn_nocontract(half %a) {
; GFX10-NEXT: v_rcp_f16_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rsq_f16_afn_nocontract:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_rcp_f16_e32 v0, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_rsq_f16_afn_nocontract:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rsq_f16_afn_nocontract:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rsq_f16_afn_nocontract:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rsq_f16_afn_nocontract:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call half @llvm.sqrt.f16(half %a)
%fdiv = fdiv afn half 1.0, %sqrt
ret half %fdiv
@@ -5637,37 +7403,135 @@ define <2 x half> @v_rsq_v2f16(<2 x half> %a) {
; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rsq_v2f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v4, 1.0
-; GFX11-NEXT: v_sqrt_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT: v_rcp_f32_e32 v2, v2
-; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v5, v4, v2
-; GFX11-NEXT: v_mul_f32_e32 v4, v4, v3
-; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v4, 1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v4, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v4, 1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v2
-; GFX11-NEXT: v_mul_f32_e32 v3, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
-; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
-; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_rsq_v2f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.h, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, 1.0
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v1
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v1
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_dual_mul_f32 v1, v4, v1 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-IEEE-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0xff800000, v1
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v1, v1, v6
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v2
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, 1.0
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.h, v1.h, v0.h, 1.0
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_rsq_v2f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-IEEE-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_rsq_v2f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.h, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_mul_f32 v1, v4, v1 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0xff800000, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v1, v1, v6
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.h, v1.h, v0.h, 1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_rsq_v2f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, 1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)
%fdiv = fdiv contract <2 x half> <half 1.0, half 1.0>, %sqrt
ret <2 x half> %fdiv
@@ -5951,37 +7815,135 @@ define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {
; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_neg_rsq_v2f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v4, -1.0
-; GFX11-NEXT: v_sqrt_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v0
-; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT: v_rcp_f32_e32 v2, v2
-; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v5, v4, v2
-; GFX11-NEXT: v_mul_f32_e32 v4, v4, v3
-; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v4, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v2
-; GFX11-NEXT: v_mul_f32_e32 v3, v7, v3
-; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
-; GFX11-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
-; GFX11-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
-; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
-; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0
-; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-IEEE-TRUE16-LABEL: v_neg_rsq_v2f16:
+; GFX11-IEEE-TRUE16: ; %bb.0:
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_sqrt_f16_e32 v0.h, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, -1.0
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-IEEE-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v1
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v1
+; GFX11-IEEE-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-IEEE-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-TRUE16-NEXT: v_dual_mul_f32 v1, v4, v1 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-IEEE-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0xff800000, v1
+; GFX11-IEEE-TRUE16-NEXT: v_add_f32_e32 v1, v1, v6
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-IEEE-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v2
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, -1.0
+; GFX11-IEEE-TRUE16-NEXT: v_div_fixup_f16 v0.h, v1.h, v0.h, -1.0
+; GFX11-IEEE-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-IEEE-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-IEEE-FAKE16-LABEL: v_neg_rsq_v2f16:
+; GFX11-IEEE-FAKE16: ; %bb.0:
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-IEEE-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, -1.0
+; GFX11-IEEE-FAKE16-NEXT: v_sqrt_f16_e32 v1, v1
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-IEEE-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-IEEE-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-IEEE-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-IEEE-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-IEEE-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
+; GFX11-IEEE-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-IEEE-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0
+; GFX11-IEEE-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-IEEE-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-TRUE16-LABEL: v_neg_rsq_v2f16:
+; GFX11-FLUSH-TRUE16: ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_sqrt_f16_e32 v0.h, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v3, v3, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v8, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v3, v8, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v7, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v5, -v5, v3, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_fma_mix_f32 v4, -v4, v6, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_mul_f32 v1, v4, v1 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0xff800000, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_add_f32_e32 v1, v1, v6
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-FLUSH-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v2
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.l, v1.l, v0.l, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_div_fixup_f16 v0.h, v1.h, v0.h, -1.0
+; GFX11-FLUSH-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FLUSH-FAKE16-LABEL: v_neg_rsq_v2f16:
+; GFX11-FLUSH-FAKE16: ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_sqrt_f16_e32 v1, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v4, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v7, -v1, v4, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_mul_f32_e32 v3, v7, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_fma_mix_f32 v6, -v0, v5, -1.0 op_sel_hi:[1,0,1]
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_mul_f32 v2, v6, v2 :: v_dual_and_b32 v3, 0xff800000, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_dual_add_f32 v3, v3, v4 :: v_dual_and_b32 v2, 0xff800000, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX11-FLUSH-FAKE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX11-FLUSH-FAKE16-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0
+; GFX11-FLUSH-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)
%fdiv = fdiv contract <2 x half> <half -1.0, half -1.0>, %sqrt
ret <2 x half> %fdiv
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
index 9949b823dfec1..884ebd9c0ea08 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
@@ -424,10 +424,11 @@ define <2 x half> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half
; SDAG-GFX1100-TRUE16: ; %bb.0:
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v4, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.h, v3.l
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32:
@@ -546,11 +547,12 @@ define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half
; SDAG-GFX1100-TRUE16: ; %bb.0:
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v0.l
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v7, v2, v4 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.h, v6.l
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v6
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32:
@@ -716,14 +718,14 @@ define <4 x half> @v_mad_mix_v4f32(<4 x half> %src0, <4 x half> %src1, <4 x half
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v1.h, v7.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v8, v2, v4 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v6, v3, v5 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.h, v6.l
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.h, v7.l
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v4f32:
@@ -924,27 +926,14 @@ define <4 x half> @v_mad_mix_v4f32(<4 x half> %src0, <4 x half> %src1, <4 x half
; FIXME (DAG): Fold clamp
define <2 x half> @v_mad_mix_v2f32_clamp_postcvt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
-; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_postcvt:
-; SDAG-GFX1100-TRUE16: ; %bb.0:
-; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v3, v4, v5 op_sel_hi:[1,1,1] clamp
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
-; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_clamp_postcvt:
-; SDAG-GFX1100-FAKE16: ; %bb.0:
-; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; SDAG-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
-; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_v2f32_clamp_postcvt:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GFX1100-NEXT: v_mov_b32_e32 v0, v3
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_v2f32_clamp_postcvt:
; GFX900: ; %bb.0:
@@ -1001,15 +990,6 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt(<2 x half> %src0, <2 x half> %s
; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v1, v1 clamp
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_clamp_postcvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-VI-LABEL: v_mad_mix_v2f32_clamp_postcvt:
; GISEL-VI: ; %bb.0:
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1073,17 +1053,14 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v2, v3, v5, v4 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: v_pack_b32_f16 v1, v0.l, 0
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
+; SDAG-GFX1100-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, 0
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-TRUE16-NEXT: v_pk_max_f16 v0, v2, v2 clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1 clamp
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; SDAG-GFX1100-TRUE16-NEXT: v_pk_max_f16 v0, v3, v3 clamp
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32_clamp_postcvt:
@@ -1287,19 +1264,17 @@ define <4 x half> @v_mad_mix_v4f32_clamp_postcvt(<4 x half> %src0, <4 x half> %s
; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v4f32_clamp_postcvt:
; SDAG-GFX1100-TRUE16: ; %bb.0:
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v7, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.h, v6.l
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.h, v7.l
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.h, v7.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v2, v1, v3, v5 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v6, v7, v4 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-TRUE16-NEXT: v_pk_max_f16 v1, v2, v2 clamp
-; SDAG-GFX1100-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0 clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_pk_max_f16 v0, v6, v6 clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_pk_max_f16 v1, v7, v7 clamp
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v4f32_clamp_postcvt:
@@ -1542,14 +1517,11 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_lo(<2 x half> %src0, <2 x half>
; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
; SDAG-GFX1100-TRUE16: ; %bb.0:
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v3, v4, v5 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: v_max_f16_e64 v3.l, v3.l, v3.l clamp
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1712,13 +1684,9 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_hi(<2 x half> %src0, <2 x half>
; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_postcvt_hi:
; SDAG-GFX1100-TRUE16: ; %bb.0:
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v3, v4, v5 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1888,15 +1856,12 @@ define <2 x half> @v_mad_mix_v2f32_clamp_precvt(<2 x half> %src0, <2 x half> %sr
; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_precvt:
; SDAG-GFX1100-TRUE16: ; %bb.0:
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel_hi:[1,1,1] clamp
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v3, v4, v5 op_sel_hi:[1,1,1] clamp
-; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v3
; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX1100-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2049,18 +2014,13 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v3f32_clamp_precvt:
; SDAG-GFX1100-TRUE16: ; %bb.0:
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v6, v7, v8 op_sel_hi:[1,1,1] clamp
-; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v3, v4 op_sel_hi:[1,1,1] clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v6
; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
; SDAG-GFX1100-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -2248,20 +2208,13 @@ define <4 x half> @v_mad_mix_v4f32_clamp_precvt(<4 x half> %src0, <4 x half> %sr
; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v4f32_clamp_precvt:
; SDAG-GFX1100-TRUE16: ; %bb.0:
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v9.l, v2.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v10.l, v4.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v6, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v7, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v8, v9, v10 op_sel_hi:[1,1,1] clamp
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v6, v7, v11 op_sel_hi:[1,1,1] clamp
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
-; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v6
+; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v7
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v3
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix.ll b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
index 4c2a16c17b38a..232b9eb063df9 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
@@ -198,26 +198,14 @@ define float @v_mad_mix_f32_f16hi_f16hi_f16hi_elt(<2 x half> %src0, <2 x half> %
}
define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
-; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32:
-; SDAG-GFX1100-TRUE16: ; %bb.0:
-; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v3, v4, v5 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
-; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32:
-; SDAG-GFX1100-FAKE16: ; %bb.0:
-; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; SDAG-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
-; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_v2f32:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-NEXT: v_mov_b32_e32 v0, v3
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_v2f32:
; SDAG-GFX900: ; %bb.0:
@@ -281,15 +269,6 @@ define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x hal
; SDAG-CI-NEXT: v_mac_f32_e32 v0, v4, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -352,24 +331,14 @@ define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x hal
}
define <2 x float> @v_mad_mix_v2f32_shuffle(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
-; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_shuffle:
-; SDAG-GFX1100-TRUE16: ; %bb.0:
-; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v3, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v4, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_shuffle:
-; SDAG-GFX1100-FAKE16: ; %bb.0:
-; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; SDAG-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
-; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_v2f32_shuffle:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
+; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-NEXT: v_mov_b32_e32 v0, v3
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_v2f32_shuffle:
; GFX900: ; %bb.0:
@@ -428,15 +397,6 @@ define <2 x float> @v_mad_mix_v2f32_shuffle(<2 x half> %src0, <2 x half> %src1,
; SDAG-CI-NEXT: v_mad_f32 v1, v4, v3, v5
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_shuffle:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
; GISEL-CI-LABEL: v_mad_mix_v2f32_shuffle:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1255,28 +1215,15 @@ define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imm63(half %src0, half %src1) #0 {
}
define <2 x float> @v_mad_mix_v2f32_f32imm1(<2 x half> %src0, <2 x half> %src1) #0 {
-; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_f32imm1:
-; SDAG-GFX1100-TRUE16: ; %bb.0:
-; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; SDAG-GFX1100-TRUE16-NEXT: s_mov_b32 s0, 1.0
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v3, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
-; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_f32imm1:
-; SDAG-GFX1100-FAKE16: ; %bb.0:
-; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-FAKE16-NEXT: s_mov_b32 s0, 1.0
-; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; SDAG-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
-; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_f32imm1:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: s_mov_b32 s0, 1.0
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_v2f32_f32imm1:
; SDAG-GFX900: ; %bb.0:
@@ -1400,28 +1347,15 @@ define <2 x float> @v_mad_mix_v2f32_f32imm1(<2 x half> %src0, <2 x half> %src1)
}
define <2 x float> @v_mad_mix_v2f32_cvtf16imminv2pi(<2 x half> %src0, <2 x half> %src1) #0 {
-; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
-; SDAG-GFX1100-TRUE16: ; %bb.0:
-; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; SDAG-GFX1100-TRUE16-NEXT: s_mov_b32 s0, 0x3e230000
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v3, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
-; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
-; SDAG-GFX1100-FAKE16: ; %bb.0:
-; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-FAKE16-NEXT: s_mov_b32 s0, 0x3e230000
-; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; SDAG-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
-; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0x3e230000
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
; SDAG-GFX900: ; %bb.0:
@@ -1552,28 +1486,15 @@ define <2 x float> @v_mad_mix_v2f32_cvtf16imminv2pi(<2 x half> %src0, <2 x half>
}
define <2 x float> @v_mad_mix_v2f32_f32imminv2pi(<2 x half> %src0, <2 x half> %src1) #0 {
-; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_f32imminv2pi:
-; SDAG-GFX1100-TRUE16: ; %bb.0:
-; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; SDAG-GFX1100-TRUE16-NEXT: s_mov_b32 s0, 0.15915494
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v3, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
-; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_f32imminv2pi:
-; SDAG-GFX1100-FAKE16: ; %bb.0:
-; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-FAKE16-NEXT: s_mov_b32 s0, 0.15915494
-; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; SDAG-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
-; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_f32imminv2pi:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0.15915494
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_v2f32_f32imminv2pi:
; SDAG-GFX900: ; %bb.0:
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