[llvm] [Exegesis][RISCV] Add initial RVV support (PR #128767)

[Craig Topper via llvm-commits]

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@@ -75,30 +647,10 @@ static std::vector<MCInst> loadFP64RegBits32(const MCSubtargetInfo &STI,
   return Instrs;
 }
 
-static MCInst nop() {
-  // ADDI X0, X0, 0
-  return MCInstBuilder(RISCV::ADDI)
-      .addReg(RISCV::X0)
-      .addReg(RISCV::X0)
-      .addImm(0);
-}
-
-static bool isVectorRegList(MCRegister Reg) {
-  return RISCV::VRM2RegClass.contains(Reg) ||
-         RISCV::VRM4RegClass.contains(Reg) ||
-         RISCV::VRM8RegClass.contains(Reg) ||
-         RISCV::VRN2M1RegClass.contains(Reg) ||
-         RISCV::VRN2M2RegClass.contains(Reg) ||
-         RISCV::VRN2M4RegClass.contains(Reg) ||
-         RISCV::VRN3M1RegClass.contains(Reg) ||
-         RISCV::VRN3M2RegClass.contains(Reg) ||
-         RISCV::VRN4M1RegClass.contains(Reg) ||
-         RISCV::VRN4M2RegClass.contains(Reg) ||
-         RISCV::VRN5M1RegClass.contains(Reg) ||
-         RISCV::VRN6M1RegClass.contains(Reg) ||
-         RISCV::VRN7M1RegClass.contains(Reg) ||
-         RISCV::VRN8M1RegClass.contains(Reg);
-}
+// NOTE: Alternatively, we can use BitVector here, but the number of RVV MC
+// opcodes is just a small portion of the entire opcode space, so I thought it
+// would be a waste of space to use BitVector.
+static SmallSet<unsigned, 16> RVVMCOpcodesWithPseudos;
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topperc wrote:

I thought you could check if the implicit uses had VTYPE/VL in it, but it looks like we messed up the implicit uses on some instructions.

Let's use mutable for now. That will at least manage the scope and lifetime.

https://github.com/llvm/llvm-project/pull/128767