[llvm] 15e295d - [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (#128739)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 27 02:27:11 PST 2025
Author: Lucas Ramirez
Date: 2025-02-27T11:27:07+01:00
New Revision: 15e295d30aa356a0ab1d83e477375cf3ef314947
URL: https://github.com/llvm/llvm-project/commit/15e295d30aa356a0ab1d83e477375cf3ef314947
DIFF: https://github.com/llvm/llvm-project/commit/15e295d30aa356a0ab1d83e477375cf3ef314947.diff
LOG: [MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (#128739)
The MI scheduler skips regions containing a single MI during scheduling.
This can prevent targets that perform multi-stage scheduling and move
MIs between regions during some stages to reason correctly about the
entire IR, since some MIs will not be assigned to a region at the
beginning.
This makes the machine scheduler no longer skip single-MI regions. Only
a few unit tests are affected (mainly those which check for the
scheduler's debug output).
Added:
Modified:
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
llvm/test/CodeGen/ARM/misched-branch-targets.mir
llvm/test/CodeGen/PowerPC/pr47155-47156.ll
llvm/test/CodeGen/X86/fake-use-scheduler.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index bd7eeca1f84d9..d67e4ef572469 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -779,8 +779,11 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
// it. Perhaps it still needs to be bundled.
Scheduler.enterRegion(&*MBB, I, RegionEnd, NumRegionInstrs);
- // Skip empty scheduling regions (0 or 1 schedulable instructions).
- if (I == RegionEnd || I == std::prev(RegionEnd)) {
+ // Skip empty scheduling regions but include single-MI regions; we want
+ // those to be scheduled so that backends which move MIs across regions
+ // during scheduling can reason about and schedule those regions
+ // correctly.
+ if (I == RegionEnd) {
// Close the current region. Bundle the terminator if needed.
// This invalidates 'RegionEnd' and 'I'.
Scheduler.exitRegion();
diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
index d415346b49b28..2a08c52e447ba 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
+++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
@@ -2,6 +2,8 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
# REQUIRES: asserts
+# CHECK: ********** MI Scheduling **********
+# CHECK-NEXT: test_get_liveins:%bb.0
# CHECK: ********** MI Scheduling **********
# CHECK-NEXT: test_get_liveins:%bb.1
# CHECK: Region live-in pressure: VGPRs: 1 AGPRs: 0, SGPRs: 0, LVGPR WT: 0, LSGPR WT: 0
diff --git a/llvm/test/CodeGen/ARM/misched-branch-targets.mir b/llvm/test/CodeGen/ARM/misched-branch-targets.mir
index 610344f844001..4b27ed93119c9 100644
--- a/llvm/test/CodeGen/ARM/misched-branch-targets.mir
+++ b/llvm/test/CodeGen/ARM/misched-branch-targets.mir
@@ -1,7 +1,7 @@
-# RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s
-# RUN: llc -o - -passes=machine-scheduler -misched=shuffle %s | FileCheck %s
-# RUN: llc -o - -run-pass=postmisched %s | FileCheck %s
-# RUN: llc -o - -passes=postmisched %s | FileCheck %s
+# RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck -check-prefixes=CHECK,CHECK-MISCHED %s
+# RUN: llc -o - -passes=machine-scheduler -misched=shuffle %s | FileCheck -check-prefixes=CHECK,CHECK-MISCHED %s
+# RUN: llc -o - -run-pass=postmisched %s | FileCheck -check-prefixes=CHECK,CHECK-POSTMISCHED %s
+# RUN: llc -o - -passes=postmisched %s | FileCheck -check-prefixes=CHECK,CHECK-POSTMISCHED %s
# REQUIRES: asserts
# -misched=shuffle is only available with assertions enabled
@@ -147,7 +147,8 @@ body: |
# CHECK-LABEL: name: foo_setjmp
# CHECK: body:
-# CHECK: tBL 14 /* CC::al */, $noreg, @setjmp, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
+# CHECK-MISCHED: tBL 14 /* CC::al */, $noreg, @setjmp, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def $r0
+# CHECK-POSTMISCHED: tBL 14 /* CC::al */, $noreg, @setjmp, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
# CHECK-NEXT: t2BTI
---
diff --git a/llvm/test/CodeGen/PowerPC/pr47155-47156.ll b/llvm/test/CodeGen/PowerPC/pr47155-47156.ll
index 02f287634578a..1fb3607eb05c3 100644
--- a/llvm/test/CodeGen/PowerPC/pr47155-47156.ll
+++ b/llvm/test/CodeGen/PowerPC/pr47155-47156.ll
@@ -4,6 +4,7 @@
; RUN: -stop-after=postmisched -debug-only=machine-scheduler 2>&1 >/dev/null | FileCheck %s
define void @pr47155() {
+; CHECK-LABEL: Machine code for function pr47155
; CHECK: *** Final schedule for %bb.0 ***
; CHECK: ********** MI Scheduling **********
; CHECK-NEXT: pr47155:%bb.0 entry
@@ -23,6 +24,7 @@ entry:
}
define void @pr47156(ptr %fn) {
+; CHECK-LABEL: Machine code for function pr47156
; CHECK: *** Final schedule for %bb.0 ***
; CHECK: ********** MI Scheduling **********
; CHECK-NEXT: pr47156:%bb.0 entry
diff --git a/llvm/test/CodeGen/X86/fake-use-scheduler.mir b/llvm/test/CodeGen/X86/fake-use-scheduler.mir
index 8b82c4ed2485d..20c9ffec61383 100644
--- a/llvm/test/CodeGen/X86/fake-use-scheduler.mir
+++ b/llvm/test/CodeGen/X86/fake-use-scheduler.mir
@@ -9,6 +9,12 @@
#
# CHECK: ********** MI Scheduling **********
# CHECK-NEXT: foo:%bb.0 entry
+# CHECK-NEXT: From: $rax = COPY %5:gr64
+# CHECK-NEXT: To: RET 0, killed $rax
+# CHECK-NEXT: RegionInstrs: 1
+#
+# CHECK: ********** MI Scheduling **********
+# CHECK-NEXT: foo:%bb.0 entry
# CHECK-NEXT: From: %0:gr64 = COPY $rdi
# CHECK-NEXT: To: FAKE_USE %5:gr64
# CHECK-NEXT: RegionInstrs: 7
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