[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

> I've thought the same but it always felt tricky to pull off properly. The last time I looked at it I wondered whether it could be handling entirely during isel via complex patterns. I hesitated because I worried it could cause significant noise and make it harder for machine passes that attempt to analyse/merge offsets. This could be ill founded but with no performance based motivation I figured I'll just ignore it for now. Feel free to investigate this yourself but for my money I think you'll be better off just pushing this PR through and moving on until analysis shows a genuine need to look deeper.
> 
> I'll caveat this by saying despite implementing the feature the whole `-msve-vector-bits` has never sat well with me, although I do appreciate that when maximum performance is required the ideals of scalable vectors becomes secondary :)

Thanks for the suggestion, I'll ask around if there are known cases where missing out on the addressing modes is causing problems. In any case, although that wasn't the main goal, the current patch should also help fix the addressing mode issues for VLS 128.

For what it's worth, I'm not the biggest fan of `-msve-vector-bits`/VLS SVE either. I wish the best performance could _always_ be plain SVE. I suppose `-msve-vector-bits` is just a stop-gap solution until we get there. :)

https://github.com/llvm/llvm-project/pull/127500