[llvm] [TargetInstrInfo] Add target hook for InstrSchedModel latency. [NFCI] (PR #128925)

[Austin Kerbow via llvm-commits]

https://github.com/kerbowa created https://github.com/llvm/llvm-project/pull/128925

Allows targets to dynamically set latency values in the DAG builder.
This is useful in multi-pass schedulers like in the AMDGUP backend where
we may want to schedule a region multiple times with a different machine
model or tweaked latencies for a specific instruction type.

>From fe6782da986b184d334b222a2adfefa4aa4b4bb4 Mon Sep 17 00:00:00 2001
From: Austin Kerbow <Austin.Kerbow at amd.com>
Date: Tue, 25 Feb 2025 19:37:46 -0800
Subject: [PATCH] [TargetInstrInfo] Add target hook for InstrSchedModel
 latency. [NFCI]

Allows targets to dynamically set latency values in the DAG builder.
This is useful in multi-pass schedulers like in the AMDGUP backend where
we may want to schedule a region multiple times with a different machine
model or tweaked latencies for a specific instruction type.
---
 llvm/include/llvm/CodeGen/TargetInstrInfo.h | 11 ++++++++---
 llvm/include/llvm/CodeGen/TargetSchedule.h  |  3 +--
 llvm/lib/CodeGen/TargetInstrInfo.cpp        | 12 ++++++++++++
 llvm/lib/CodeGen/TargetSchedule.cpp         |  9 +++------
 4 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 9e7893d5c4142..b548cbebde9e0 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1802,13 +1802,18 @@ class TargetInstrInfo : public MCInstrInfo {
                     const MachineInstr &DefMI, unsigned DefIdx,
                     const MachineInstr &UseMI, unsigned UseIdx) const;
 
-  /// Compute the instruction latency of a given instruction.
-  /// If the instruction has higher cost when predicated, it's returned via
-  /// PredCost.
+  /// Compute the instruction latency of a given instruction using the itinerary
+  /// model.  If the instruction has higher cost when predicated, it's returned
+  /// via PredCost.
   virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
                                    const MachineInstr &MI,
                                    unsigned *PredCost = nullptr) const;
 
+  /// Compute the instruction latency using the InstrSchedModel or the default
+  /// def latency when no model is available.
+  virtual unsigned getInstrLatency(const TargetSchedModel &TargetSchedModel,
+                                   const MachineInstr &MI) const;
+
   virtual unsigned getPredicationCost(const MachineInstr &MI) const;
 
   virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
diff --git a/llvm/include/llvm/CodeGen/TargetSchedule.h b/llvm/include/llvm/CodeGen/TargetSchedule.h
index bfe4234abf8eb..3c5c3aa8b5057 100644
--- a/llvm/include/llvm/CodeGen/TargetSchedule.h
+++ b/llvm/include/llvm/CodeGen/TargetSchedule.h
@@ -43,8 +43,6 @@ class TargetSchedModel {
   // Resource units per cycle. Latency normalization factor.
   unsigned ResourceLCM = 0;
 
-  unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
-
 public:
   TargetSchedModel() : SchedModel(MCSchedModel::Default) {}
 
@@ -189,6 +187,7 @@ class TargetSchedModel {
                                bool UseDefaultDefLatency = true) const;
   unsigned computeInstrLatency(const MCInst &Inst) const;
   unsigned computeInstrLatency(unsigned Opcode) const;
+  unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
 
 
   /// Output dependency latency of a pair of defs of the same register.
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 7a905b65f26e5..289c15d28a435 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1514,6 +1514,18 @@ unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
   return ItinData->getStageLatency(MI.getDesc().getSchedClass());
 }
 
+unsigned
+TargetInstrInfo::getInstrLatency(const TargetSchedModel &TargetSchedModel,
+                                 const MachineInstr &MI) const {
+  if (TargetSchedModel.hasInstrSchedModel()) {
+    const MCSchedClassDesc *SCDesc = TargetSchedModel.resolveSchedClass(&MI);
+    if (SCDesc->isValid())
+      return TargetSchedModel.computeInstrLatency(*SCDesc);
+  }
+
+  return defaultDefLatency(*TargetSchedModel.getMCSchedModel(), MI);
+}
+
 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
                                        const MachineInstr &DefMI,
                                        unsigned DefIdx) const {
diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp
index db884b4940395..91d3a794e50b6 100644
--- a/llvm/lib/CodeGen/TargetSchedule.cpp
+++ b/llvm/lib/CodeGen/TargetSchedule.cpp
@@ -261,12 +261,9 @@ TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
       (!hasInstrSchedModel() && !UseDefaultDefLatency))
     return TII->getInstrLatency(&InstrItins, *MI);
 
-  if (hasInstrSchedModel()) {
-    const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
-    if (SCDesc->isValid())
-      return computeInstrLatency(*SCDesc);
-  }
-  return TII->defaultDefLatency(SchedModel, *MI);
+  // This is used by targets that define an InstrSchedModel or want to use the
+  // default def latency.
+  return TII->getInstrLatency(*this, *MI);
 }
 
 unsigned TargetSchedModel::