[llvm] [SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (PR #128800)

[Luke Lau via llvm-commits]

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@@ -0,0 +1,136 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define bfloat @vreduce_fmin_nxv4f16(<vscale x 4 x bfloat> %val) {
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lukel97 wrote:

Minor nit, 
```suggestion
define bfloat @vreduce_fmin_nxv4bf16(<vscale x 4 x bfloat> %val) {
```

etc.

https://github.com/llvm/llvm-project/pull/128800