[llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)

[Matt Arsenault via llvm-commits]

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@@ -3611,13 +3611,26 @@ SIRegisterInfo::getRegClassForOperandReg(const MachineRegisterInfo &MRI,
   return getSubRegisterClass(SrcRC, MO.getSubReg());
 }
 
+bool SIRegisterInfo::isVGPR(MCRegister Reg) const {
+  const TargetRegisterClass *RC = getPhysRegBaseClass(Reg);
+  // Registers without classes are unaddressable, SGPR-like registers.
+  return RC && isVGPRClass(RC);
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arsenm wrote:

Move to inline in header 

https://github.com/llvm/llvm-project/pull/128927