[llvm] [RISCV] Use addiw for or_is_add when or input is sign extended. (PR #128635)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue Feb 25 10:05:04 PST 2025

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https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/128635

Previous message: [llvm] [RISCV] Use addiw for or_is_add when or input is sign extended. (PR #128635)
Next message: [clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
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