[llvm] [AMDGPU][True16][MC] true16 for v_alignbit_b32 (PR #119409)
Brox Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 26 13:13:26 PST 2025
https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/119409
>From 7ab30ef75d98de6a24e5b8b5a21391f88eaeb5f8 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Tue, 10 Dec 2024 01:20:40 -0500
Subject: [PATCH] VOP3 v_alignbit_b32 mc support true16
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 115 +-
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 9 +-
.../AMDGPU/GlobalISel/inst-select-fshr.mir | 11 +-
llvm/test/CodeGen/AMDGPU/bf16.ll | 11092 ++++++----------
llvm/test/CodeGen/AMDGPU/bswap.ll | 28 +-
llvm/test/MC/AMDGPU/gfx11_asm_vop3.s | 29 +-
llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s | 67 +-
llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s | 41 +-
llvm/test/MC/AMDGPU/gfx12_asm_vop3.s | 3 +
llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s | 3 +
llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s | 3 +
.../Disassembler/AMDGPU/gfx11_dasm_vop3.txt | 16 +-
.../AMDGPU/gfx11_dasm_vop3_dpp16.txt | 31 +-
.../AMDGPU/gfx11_dasm_vop3_dpp8.txt | 16 +-
.../Disassembler/AMDGPU/gfx12_dasm_vop3.txt | 16 +-
.../AMDGPU/gfx12_dasm_vop3_dpp16.txt | 36 +-
.../AMDGPU/gfx12_dasm_vop3_dpp8.txt | 21 +-
17 files changed, 4235 insertions(+), 7302 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 6f80dbcfe5e71..b994e4bee22c6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2498,6 +2498,7 @@ def : AMDGPUPat <
$src1), sub1)
>;
+let True16Predicate = NotHasTrue16BitInsts in {
def : ROTRPattern <V_ALIGNBIT_B32_e64>;
def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
@@ -2507,6 +2508,42 @@ def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
(V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
+} // end True16Predicate = NotHasTrue16BitInsts
+
+let True16Predicate = UseFakeTrue16Insts in {
+def : GCNPat <
+ (rotr i32:$src0, i32:$src1),
+ (V_ALIGNBIT_B32_fake16_e64 /* src0_modifiers */ 0, $src0,
+ /* src1_modifiers */ 0, $src0,
+ /* src2_modifiers */ 0,
+ $src1, /* clamp */ 0, /* op_sel */ 0)
+>;
+
+def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
+ (V_ALIGNBIT_B32_fake16_e64 0, /* src0_modifiers */
+ (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
+ 0, /* src1_modifiers */
+ (i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
+ 0, /* src2_modifiers */
+ $src1, /* clamp */ 0, /* op_sel */ 0)
+>;
+
+def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
+ (V_ALIGNBIT_B32_fake16_e64 0, /* src0_modifiers */
+ (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
+ 0, /* src1_modifiers */
+ (i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
+ 0, /* src2_modifiers */
+ $src1, /* clamp */ 0, /* op_sel */ 0)
+>;
+
+def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
+ (V_ALIGNBIT_B32_fake16_e64 /* src0_modifiers */ 0, $src0,
+ /* src1_modifiers */ 0, $src1,
+ /* src2_modifiers */ 0,
+ $src2, /* clamp */ 0, /* op_sel */ 0)
+>;
+} // end True16Predicate = UseFakeTrue16Insts
/********** ====================== **********/
/********** Indirect addressing **********/
@@ -3014,6 +3051,7 @@ def : GCNPat <
(i32 (EXTRACT_SUBREG $a, sub0))), (i32 1))
>;
+let True16Predicate = NotHasTrue16BitInsts in
def : GCNPat <
(i32 (bswap i32:$a)),
(V_BFI_B32_e64 (S_MOV_B32 (i32 0x00ff00ff)),
@@ -3021,28 +3059,61 @@ def : GCNPat <
(V_ALIGNBIT_B32_e64 VSrc_b32:$a, VSrc_b32:$a, (i32 8)))
>;
-// FIXME: This should have been narrowed to i32 during legalization.
-// This pattern should also be skipped for GlobalISel
+let True16Predicate = UseFakeTrue16Insts in
+def : GCNPat <
+ (i32 (bswap i32:$a)),
+ (V_BFI_B32_e64 (S_MOV_B32 (i32 0x00ff00ff)),
+ (V_ALIGNBIT_B32_fake16_e64 0, /* src0_modifiers */
+ VSrc_b32:$a,
+ 0, /* src1_modifiers */
+ VSrc_b32:$a,
+ 0, /* src2_modifiers */
+ (i32 24), /* clamp */ 0, /* op_sel */ 0),
+ (V_ALIGNBIT_B32_fake16_e64 0, /* src0_modifiers */
+ VSrc_b32:$a,
+ 0, /* src1_modifiers */
+ VSrc_b32:$a,
+ 0, /* src2_modifiers */
+ (i32 8), /* clamp */ 0, /* op_sel */ 0))
+>;
+
+class AlignBit32Inst<dag op1, dag op2, dag op3, bit isTrue16> {
+ defvar inst = !if(isTrue16, V_ALIGNBIT_B32_fake16_e64, V_ALIGNBIT_B32_e64);
+ defvar NoMods = !if(isTrue16, (inst 0), (inst));
+ dag ret = !con(NoMods, (inst op1), NoMods, (inst op2),
+ NoMods, (inst op3), NoMods, NoMods);
+}
+
+multiclass bswapi64ExtPat<bit hasTrue16> {
def : GCNPat <
(i64 (bswap i64:$a)),
(REG_SEQUENCE VReg_64,
(V_BFI_B32_e64 (S_MOV_B32 (i32 0x00ff00ff)),
- (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
- (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
- (i32 24)),
- (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
- (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
- (i32 8))),
+ AlignBit32Inst<(i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
+ (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
+ (i32 24), hasTrue16>.ret,
+ AlignBit32Inst<(i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
+ (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
+ (i32 8), hasTrue16>.ret),
sub0,
(V_BFI_B32_e64 (S_MOV_B32 (i32 0x00ff00ff)),
- (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
- (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
- (i32 24)),
- (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
- (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
- (i32 8))),
+ AlignBit32Inst<(i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
+ (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
+ (i32 24), hasTrue16>.ret,
+ AlignBit32Inst<(i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
+ (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
+ (i32 8), hasTrue16>.ret),
sub1)
>;
+}
+
+// FIXME: This should have been narrowed to i32 during legalization.
+// This pattern should also be skipped for GlobalISel
+let True16Predicate = NotHasTrue16BitInsts in
+defm : bswapi64ExtPat</*hasTrue16*/0>;
+
+let True16Predicate = UseFakeTrue16Insts in
+defm : bswapi64ExtPat</*hasTrue16*/1>;
// FIXME: The AddedComplexity should not be needed, but in GlobalISel
// the BFI pattern ends up taking precedence without it.
@@ -3455,8 +3526,7 @@ def : GCNPat <
// Take the upper 16 bits from V[0] and the lower 16 bits from V[1]
// Special case, can use V_ALIGNBIT (always uses encoded literal)
-foreach p = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in
-let True16Predicate = p in {
+let True16Predicate = NotHasTrue16BitInsts in
def : GCNPat <
(vecTy (DivergentBinFrag<build_vector>
(Ty !if(!eq(Ty, i16),
@@ -3466,7 +3536,19 @@ def : GCNPat <
(V_ALIGNBIT_B32_e64 VGPR_32:$b, VGPR_32:$a, (i32 16))
>;
+let True16Predicate = UseFakeTrue16Insts in
+def : GCNPat <
+ (vecTy (DivergentBinFrag<build_vector>
+ (Ty !if(!eq(Ty, i16),
+ (Ty (trunc (srl VGPR_32:$a, (i32 16)))),
+ (Ty (bitconvert (i16 (trunc (srl VGPR_32:$a, (i32 16)))))))),
+ (Ty VGPR_32:$b))),
+ (V_ALIGNBIT_B32_fake16_e64 0, VGPR_32:$b, 0, VGPR_32:$a, 0, (i16 16), 0, 0)
+>;
+
// Take the upper 16 bits from each VGPR_32 and concat them
+foreach p = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in
+let True16Predicate = p in
def : GCNPat <
(vecTy (DivergentBinFrag<build_vector>
(Ty !if(!eq(Ty, i16),
@@ -3477,7 +3559,6 @@ def : GCNPat <
(Ty (bitconvert (i16 (trunc (srl VGPR_32:$b, (i32 16)))))))))),
(V_PERM_B32_e64 VGPR_32:$b, VGPR_32:$a, (S_MOV_B32 (i32 0x07060302)))
>;
-}
} // end foreach Ty
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 1447804871809..b80ad366b2796 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -211,9 +211,12 @@ defm V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>,
defm V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>;
defm V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;
defm V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;
-defm V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, fshr>;
+defm V_ALIGNBIT_B32 : VOP3Inst_t16_with_profiles <"v_alignbit_b32",
+ VOP3_Profile<VOP_I32_I32_I32_I32>,
+ VOP3_Profile_True16<VOP_I32_I32_I32_I16, VOP3_OPSEL>,
+ VOP3_Profile_Fake16<VOP_I32_I32_I32_I16, VOP3_OPSEL>,
+ fshr, null_frag>;
-let True16Predicate = NotHasTrue16BitInsts in
defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
let True16Predicate = UseRealTrue16Insts in
defm V_ALIGNBYTE_B32_t16 : VOP3Inst <"v_alignbyte_b32_t16", VOP3_Profile_True16<VOP_I32_I32_I32_I16, VOP3_OPSEL>>;
@@ -1726,7 +1729,7 @@ defm V_BFI_B32 : VOP3_Realtriple_gfx11_gfx12<0x212>;
defm V_FMA_F32 : VOP3_Realtriple_gfx11_gfx12<0x213>;
defm V_FMA_F64 : VOP3_Real_Base_gfx11_gfx12<0x214>;
defm V_LERP_U8 : VOP3_Realtriple_gfx11_gfx12<0x215>;
-defm V_ALIGNBIT_B32 : VOP3_Realtriple_gfx11_gfx12<0x216>;
+defm V_ALIGNBIT_B32 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x216, "v_alignbit_b32">;
defm V_ALIGNBYTE_B32 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x217, "v_alignbyte_b32">;
defm V_MULLIT_F32 : VOP3_Realtriple_gfx11_gfx12<0x218>;
defm V_MIN3_F32 : VOP3_Realtriple_gfx11<0x219>;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
index 4291744d85732..1fb67fe17cb0a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
@@ -3,7 +3,7 @@
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX11 %s
---
@@ -23,6 +23,15 @@ body: |
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN-NEXT: [[V_ALIGNBIT_B32_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_e64_]]
+ ;
+ ; GFX11-LABEL: name: fshr_s32
+ ; GFX11: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX11-NEXT: [[V_ALIGNBIT_B32_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_fake16_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index aafdb1c8cc36f..8467f07b333a3 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -60,21 +60,13 @@ define void @test_load_store(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: test_load_store:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: test_load_store:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: global_load_u16 v0, v[0:1], off
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11FAKE16-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_load_store:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: global_load_u16 v0, v[0:1], off
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%val = load bfloat, ptr addrspace(1) %in
store bfloat %val, ptr addrspace(1) %out
ret void
@@ -2135,23 +2127,14 @@ define void @test_store_fpimm(ptr addrspace(1) %ptr0, ptr addrspace(1) %ptr1) {
; GFX10-NEXT: global_store_short v[2:3], v5, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: test_store_fpimm:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, 0x3f80
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, 0x4228
-; GFX11TRUE16-NEXT: global_store_b16 v[0:1], v4, off
-; GFX11TRUE16-NEXT: global_store_d16_hi_b16 v[2:3], v4, off
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: test_store_fpimm:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_mov_b32_e32 v4, 0x3f80
-; GFX11FAKE16-NEXT: v_mov_b32_e32 v5, 0x4228
-; GFX11FAKE16-NEXT: global_store_b16 v[0:1], v4, off
-; GFX11FAKE16-NEXT: global_store_b16 v[2:3], v5, off
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_store_fpimm:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v4, 0x3f80
+; GFX11-NEXT: v_mov_b32_e32 v5, 0x4228
+; GFX11-NEXT: global_store_b16 v[0:1], v4, off
+; GFX11-NEXT: global_store_b16 v[2:3], v5, off
+; GFX11-NEXT: s_setpc_b64 s[30:31]
store bfloat 1.0, ptr addrspace(1) %ptr0
store bfloat 42.0, ptr addrspace(1) %ptr1
ret void
@@ -3347,19 +3330,12 @@ define amdgpu_gfx void @test_inreg_arg_store(bfloat inreg %in, ptr addrspace(1)
; GFX10-NEXT: global_store_short v[0:1], v2, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: test_inreg_arg_store:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, s4
-; GFX11TRUE16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: test_inreg_arg_store:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_mov_b32_e32 v2, s4
-; GFX11FAKE16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_inreg_arg_store:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v2, s4
+; GFX11-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-NEXT: s_setpc_b64 s[30:31]
store bfloat %in, ptr addrspace(1) %out
ret void
}
@@ -3403,18 +3379,11 @@ define bfloat @test_byval(ptr addrspace(5) byval(bfloat) %bv, bfloat %val) {
; GFX10-NEXT: buffer_store_short v0, off, s[0:3], s32
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: test_byval:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX11TRUE16-NEXT: scratch_store_b16 off, v1, s32
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: test_byval:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: scratch_store_b16 off, v0, s32
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_byval:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: scratch_store_b16 off, v0, s32
+; GFX11-NEXT: s_setpc_b64 s[30:31]
store bfloat %val, ptr addrspace(5) %bv
%retval = load bfloat, ptr addrspace(5) %bv
ret bfloat %retval
@@ -3521,21 +3490,13 @@ define void @test_bitcast_from_bfloat(ptr addrspace(1) %in, ptr addrspace(1) %ou
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: test_bitcast_from_bfloat:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: test_bitcast_from_bfloat:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: global_load_u16 v0, v[0:1], off
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11FAKE16-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_bitcast_from_bfloat:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: global_load_u16 v0, v[0:1], off
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%val = load bfloat, ptr addrspace(1) %in
%val_int = bitcast bfloat %val to i16
store i16 %val_int, ptr addrspace(1) %out
@@ -3595,21 +3556,13 @@ define void @test_bitcast_to_bfloat(ptr addrspace(1) %out, ptr addrspace(1) %in)
; GFX10-NEXT: global_store_short v[0:1], v2, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: test_bitcast_to_bfloat:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: global_load_d16_b16 v2, v[2:3], off
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: test_bitcast_to_bfloat:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: global_load_u16 v2, v[2:3], off
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11FAKE16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_bitcast_to_bfloat:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: global_load_u16 v2, v[2:3], off
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%val = load i16, ptr addrspace(1) %in
%val_fp = bitcast i16 %val to bfloat
store bfloat %val_fp, ptr addrspace(1) %out
@@ -5356,23 +5309,14 @@ define bfloat @test_alloca_load_store_ret(bfloat %in) {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: test_alloca_load_store_ret:
-; GFX11TRUE16: ; %bb.0: ; %entry
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: scratch_store_b16 off, v0, s32 dlc
-; GFX11TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11TRUE16-NEXT: scratch_load_d16_b16 v0, off, s32 glc dlc
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: test_alloca_load_store_ret:
-; GFX11FAKE16: ; %bb.0: ; %entry
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: scratch_store_b16 off, v0, s32 dlc
-; GFX11FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11FAKE16-NEXT: scratch_load_u16 v0, off, s32 glc dlc
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_alloca_load_store_ret:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: scratch_store_b16 off, v0, s32 dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: scratch_load_u16 v0, off, s32 glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%in.addr = alloca bfloat, align 2, addrspace(5)
store volatile bfloat %in, ptr addrspace(5) %in.addr, align 2
@@ -5723,48 +5667,26 @@ define { <32 x i32>, bfloat } @test_overflow_stack(bfloat %a, <32 x i32> %b) {
; GFX10-NEXT: buffer_store_short v1, v0, s[0:3], 0 offen offset:128
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: test_overflow_stack:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: s_clause 0x2
-; GFX11TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
-; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
-; GFX11TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11TRUE16-NEXT: s_clause 0x3
-; GFX11TRUE16-NEXT: scratch_store_b128 v0, v[22:25], off offset:80
-; GFX11TRUE16-NEXT: scratch_store_b128 v0, v[18:21], off offset:64
-; GFX11TRUE16-NEXT: scratch_store_b128 v0, v[14:17], off offset:48
-; GFX11TRUE16-NEXT: scratch_store_b128 v0, v[10:13], off offset:32
-; GFX11TRUE16-NEXT: s_clause 0x1
-; GFX11TRUE16-NEXT: scratch_store_b128 v0, v[6:9], off offset:16
-; GFX11TRUE16-NEXT: scratch_store_b128 v0, v[2:5], off
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: s_clause 0x2
-; GFX11TRUE16-NEXT: scratch_store_b128 v0, v[30:33], off offset:112
-; GFX11TRUE16-NEXT: scratch_store_b128 v0, v[26:29], off offset:96
-; GFX11TRUE16-NEXT: scratch_store_b16 v0, v1, off offset:128
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: test_overflow_stack:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: s_clause 0x2
-; GFX11FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
-; GFX11FAKE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
-; GFX11FAKE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11FAKE16-NEXT: s_clause 0x5
-; GFX11FAKE16-NEXT: scratch_store_b128 v0, v[22:25], off offset:80
-; GFX11FAKE16-NEXT: scratch_store_b128 v0, v[18:21], off offset:64
-; GFX11FAKE16-NEXT: scratch_store_b128 v0, v[14:17], off offset:48
-; GFX11FAKE16-NEXT: scratch_store_b128 v0, v[10:13], off offset:32
-; GFX11FAKE16-NEXT: scratch_store_b128 v0, v[6:9], off offset:16
-; GFX11FAKE16-NEXT: scratch_store_b128 v0, v[2:5], off
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11FAKE16-NEXT: s_clause 0x2
-; GFX11FAKE16-NEXT: scratch_store_b128 v0, v[30:33], off offset:112
-; GFX11FAKE16-NEXT: scratch_store_b128 v0, v[26:29], off offset:96
-; GFX11FAKE16-NEXT: scratch_store_b16 v0, v1, off offset:128
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: test_overflow_stack:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_clause 0x2
+; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8
+; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4
+; GFX11-NEXT: scratch_load_b32 v31, off, s32
+; GFX11-NEXT: s_clause 0x5
+; GFX11-NEXT: scratch_store_b128 v0, v[22:25], off offset:80
+; GFX11-NEXT: scratch_store_b128 v0, v[18:21], off offset:64
+; GFX11-NEXT: scratch_store_b128 v0, v[14:17], off offset:48
+; GFX11-NEXT: scratch_store_b128 v0, v[10:13], off offset:32
+; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:16
+; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_clause 0x2
+; GFX11-NEXT: scratch_store_b128 v0, v[30:33], off offset:112
+; GFX11-NEXT: scratch_store_b128 v0, v[26:29], off offset:96
+; GFX11-NEXT: scratch_store_b16 v0, v1, off offset:128
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%ins.0 = insertvalue { <32 x i32>, bfloat } poison, <32 x i32> %b, 0
%ins.1 = insertvalue { <32 x i32>, bfloat } %ins.0 ,bfloat %a, 1
ret { <32 x i32>, bfloat } %ins.1
@@ -9211,59 +9133,31 @@ define <2 x bfloat> @v_fadd_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fadd_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v3, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fadd_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11FAKE16-NEXT: v_add_f32_e32 v2, v3, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v1, v2, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fadd_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_add_f32_e32 v2, v3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fadd <2 x bfloat> %a, %b
ret <2 x bfloat> %op
}
@@ -9418,40 +9312,35 @@ define <3 x bfloat> @v_fadd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) {
; GFX11TRUE16-LABEL: v_fadd_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_add_f32 v1, v1, v3
+; GFX11TRUE16-NEXT: v_add_f32_e32 v3, v5, v4
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fadd_v3bf16:
@@ -9675,96 +9564,48 @@ define <4 x bfloat> @v_fadd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fadd_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v3, v7, v6 :: v_dual_add_f32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v3, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fadd_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX11FAKE16-NEXT: v_dual_add_f32 v3, v7, v6 :: v_dual_add_f32 v4, v5, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v9, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fadd_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_dual_add_f32 v3, v7, v6 :: v_dual_add_f32 v4, v5, v4
+; GFX11-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v9, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fadd <4 x bfloat> %a, %b
ret <4 x bfloat> %op
}
@@ -10110,176 +9951,88 @@ define <8 x bfloat> @v_fadd_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fadd_v8bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v3, v3, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v7, v11, v7 :: v_dual_add_f32 v2, v2, v6
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v3, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v10, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v3, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_add_f32_e32 v10, v13, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_add_f32_e32 v7, v12, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v11, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v10, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v11, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v4, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fadd_v8bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v3, v3, v7
-; GFX11FAKE16-NEXT: v_add_f32_e32 v7, v10, v9
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v3, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_add_f32 v2, v2, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v6, v10, v6
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v6, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_dual_add_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
-; GFX11FAKE16-NEXT: v_add_f32_e32 v5, v15, v13
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fadd_v8bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_add_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX11-NEXT: v_add_f32_e32 v7, v10, v9
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v8
+; GFX11-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v11, v3, 16, 1
+; GFX11-NEXT: v_bfe_u32 v12, v7, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
+; GFX11-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_add_f32 v2, v2, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_bfe_u32 v13, v2, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add_f32_e32 v6, v10, v6
+; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v2
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX11-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
+; GFX11-NEXT: v_dual_add_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
+; GFX11-NEXT: v_add_f32_e32 v5, v15, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v13, v0, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11-NEXT: v_bfe_u32 v12, v5, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
+; GFX11-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fadd <8 x bfloat> %a, %b
ret <8 x bfloat> %op
}
@@ -10941,322 +10694,162 @@ define <16 x bfloat> @v_fadd_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fadd_v16bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_add_f32 v18, v19, v18 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v16, v17, v16 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v6, v6, v14 :: v_dual_add_f32 v7, v7, v15
-; GFX11TRUE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v6, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v7
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v15, v14 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_add_f32_e32 v16, v20, v19
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfi_b32 v7, 0xffff, v7, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v18, v19, v18 :: v_dual_add_f32 v5, v5, v13
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v15, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_bfi_b32 v6, 0xffff, v6, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v5, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v17, v20 :: v_dual_lshlrev_b32 v20, 16, v11
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v3, v3, v11 :: v_dual_add_f32 v4, v4, v12
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v4, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
-; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0xffff, v5, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v16, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v19 :: v_dual_lshlrev_b32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v17, v18, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v3, 16, 1
-; GFX11TRUE16-NEXT: v_add_f32_e32 v2, v2, v10
-; GFX11TRUE16-NEXT: v_add_f32_e32 v16, v21, v20
-; GFX11TRUE16-NEXT: v_bfi_b32 v4, 0xffff, v4, v15
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v11, v11, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v18, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v17, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v11, v11, v17, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v18, v21 :: v_dual_lshlrev_b32 v21, 16, v8
-; GFX11TRUE16-NEXT: v_add_f32_e32 v18, v23, v22
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v11, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_add_f32_e32 v11, v22, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v21, v11, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v20, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v20, v22, vcc_lo
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v21, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v18
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v0, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v11
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v8, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v16, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v8, v3
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fadd_v16bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v17, v18, v17
-; GFX11FAKE16-NEXT: v_add_f32_e32 v6, v6, v14
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v7, v7, v15
-; GFX11FAKE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v4, v4, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v11
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_add_f32_e32 v5, v5, v13
-; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v6, v16, v13 :: v_dual_add_f32 v13, v19, v18
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v20, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_add_f32_e32 v12, v18, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v13, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v13
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v17, v12, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v18, v19, v18
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_add_f32_e32 v3, v3, v11
-; GFX11FAKE16-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v3, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v9
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_add_f32_e32 v19, v22, v20
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v8
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v19, 16, 1
-; GFX11FAKE16-NEXT: v_dual_add_f32 v0, v0, v8 :: v_dual_add_f32 v1, v1, v9
-; GFX11FAKE16-NEXT: v_add_f32_e32 v9, v22, v20
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v9
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v23, v24, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v20, v25, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v11, v21, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fadd_v16bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_add_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add_f32_e32 v17, v18, v17
+; GFX11-NEXT: v_add_f32_e32 v6, v6, v14
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v7, v7, v15
+; GFX11-NEXT: v_bfe_u32 v15, v16, 16, 1
+; GFX11-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
+; GFX11-NEXT: v_bfe_u32 v19, v7, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v19, 0x400000, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v18, v6, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_dual_add_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
+; GFX11-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-NEXT: v_bfe_u32 v20, v17, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v4, v4, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_add_f32_e32 v5, v5, v13
+; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v16, v13 :: v_dual_add_f32 v13, v19, v18
+; GFX11-NEXT: v_add3_u32 v16, v20, v17, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v17
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11-NEXT: v_bfe_u32 v21, v5, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v5
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_add_f32_e32 v12, v18, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v21, v13, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v10
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
+; GFX11-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-NEXT: v_bfe_u32 v20, v4, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v21, 0x400000, v4
+; GFX11-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v17, v12, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v2
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v18, v19, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v23, v18, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v18
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_add_f32_e32 v3, v3, v11
+; GFX11-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
+; GFX11-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v20, v3, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v19, v2, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v9
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
+; GFX11-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
+; GFX11-NEXT: v_add_f32_e32 v19, v22, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_bfe_u32 v23, v19, 16, 1
+; GFX11-NEXT: v_dual_add_f32 v0, v0, v8 :: v_dual_add_f32 v1, v1, v9
+; GFX11-NEXT: v_add_f32_e32 v9, v22, v20
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v19
+; GFX11-NEXT: v_or_b32_e32 v25, 0x400000, v0
+; GFX11-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v23, v9, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v24, 0x400000, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_bfe_u32 v20, v0, 16, 1
+; GFX11-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v22, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v23, v24, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v20, v25, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v11, v21, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fadd <16 x bfloat> %a, %b
ret <16 x bfloat> %op
}
@@ -12676,587 +12269,284 @@ define <32 x bfloat> @v_fadd_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fadd_v32bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_add_f32_e32 v5, v5, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v3, v3, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_add_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11TRUE16-NEXT: v_add_f32_e32 v2, v2, v18
-; GFX11TRUE16-NEXT: v_add_f32_e32 v18, v84, v83
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add_f32_e32 v17, v86, v85
-; GFX11TRUE16-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_and_b32 v39, 0xffff0000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_add_f32_e32 v9, v9, v25
-; GFX11TRUE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_add_f32 v24, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_add_f32_e32 v7, v7, v23
-; GFX11TRUE16-NEXT: v_dual_add_f32 v23, v66, v65 :: v_dual_lshlrev_b32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_add_f32_e32 v4, v4, v20
-; GFX11TRUE16-NEXT: v_add_f32_e32 v20, v80, v71
-; GFX11TRUE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11TRUE16-NEXT: v_dual_add_f32 v21, v70, v69 :: v_dual_lshlrev_b32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_dual_add_f32 v10, v10, v26 :: v_dual_lshlrev_b32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_dual_add_f32 v26, v52, v51 :: v_dual_add_f32 v25, v54, v53
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v6, v6, v22
-; GFX11TRUE16-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_add_f32_e32 v22, v68, v67
-; GFX11TRUE16-NEXT: v_dual_add_f32 v27, v50, v49 :: v_dual_and_b32 v38, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_dual_add_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v29, v38, v37 :: v_dual_lshlrev_b32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_dual_add_f32 v12, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v14, v14, v30
-; GFX11TRUE16-NEXT: v_add_f32_e32 v28, v48, v39
-; GFX11TRUE16-NEXT: v_dual_add_f32 v30, v36, v35 :: v_dual_add_f32 v33, v34, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11TRUE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11TRUE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11TRUE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11TRUE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_bfi_b32 v11, 0xffff, v11, v28
-; GFX11TRUE16-NEXT: v_bfi_b32 v10, 0xffff, v10, v27
-; GFX11TRUE16-NEXT: v_bfi_b32 v12, 0xffff, v12, v29
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_bfi_b32 v9, 0xffff, v9, v26
-; GFX11TRUE16-NEXT: v_bfi_b32 v13, 0xffff, v13, v30
-; GFX11TRUE16-NEXT: v_bfi_b32 v14, 0xffff, v14, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v8, 0xffff, v8, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v7, 0xffff, v7, v24
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v6, 0xffff, v6, v23
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0xffff, v5, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v4, 0xffff, v4, v21
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v3, v20
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v19
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v18
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v0, v147, v33 :: v_dual_lshlrev_b32 v33, 16, v32
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v15, v15, v33
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v32
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: v_add_f32_e32 v17, v31, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v15, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v19, v20, v17, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v18, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v15, 0xffff, v15, v17
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fadd_v32bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v21
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v17
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
-; GFX11FAKE16-NEXT: v_dual_add_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
-; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v16
-; GFX11FAKE16-NEXT: v_dual_add_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
-; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
-; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11FAKE16-NEXT: v_add_f32_e32 v2, v2, v18
-; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v16
-; GFX11FAKE16-NEXT: v_dual_add_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
-; GFX11FAKE16-NEXT: v_add_f32_e32 v7, v7, v23
-; GFX11FAKE16-NEXT: v_dual_add_f32 v23, v66, v65 :: v_dual_add_f32 v18, v84, v83
-; GFX11FAKE16-NEXT: v_dual_add_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v20
-; GFX11FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_add_f32_e32 v4, v4, v20
-; GFX11FAKE16-NEXT: v_add_f32_e32 v20, v80, v71
-; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; GFX11FAKE16-NEXT: v_dual_add_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11FAKE16-NEXT: v_dual_add_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
-; GFX11FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11FAKE16-NEXT: v_add_f32_e32 v26, v52, v51
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v6, v6, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
-; GFX11FAKE16-NEXT: v_dual_add_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
-; GFX11FAKE16-NEXT: v_dual_add_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_dual_add_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
-; GFX11FAKE16-NEXT: v_dual_add_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v29, v38, v37
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15
-; GFX11FAKE16-NEXT: v_dual_add_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v14, v14, v30
-; GFX11FAKE16-NEXT: v_add_f32_e32 v28, v48, v39
-; GFX11FAKE16-NEXT: v_dual_add_f32 v30, v36, v35 :: v_dual_add_f32 v33, v34, v33
-; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11FAKE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11FAKE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11FAKE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11FAKE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
-; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v18, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v17, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v19, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v20, 0x7060302
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v32
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_dual_add_f32 v17, v31, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
-; GFX11FAKE16-NEXT: v_add_f32_e32 v15, v15, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v18, v17, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
-; GFX11FAKE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fadd_v32bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: scratch_load_b32 v32, off, s32
+; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17
+; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX11-NEXT: v_dual_add_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
+; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19
+; GFX11-NEXT: v_bfe_u32 v103, v5, 16, 1
+; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v112, 0x400000, v5
+; GFX11-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_add_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16
+; GFX11-NEXT: v_dual_add_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v129, v19, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v130, 0x400000, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11-NEXT: v_bfe_u32 v119, v3, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_add_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
+; GFX11-NEXT: v_or_b32_e32 v128, 0x400000, v3
+; GFX11-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v145, v17, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4
+; GFX11-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v18
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v16
+; GFX11-NEXT: v_dual_add_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
+; GFX11-NEXT: v_add_f32_e32 v7, v7, v23
+; GFX11-NEXT: v_dual_add_f32 v23, v66, v65 :: v_dual_add_f32 v18, v84, v83
+; GFX11-NEXT: v_dual_add_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v85, v24, 16, 1
+; GFX11-NEXT: v_bfe_u32 v97, v23, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v86, 0x400000, v24
+; GFX11-NEXT: v_or_b32_e32 v98, 0x400000, v23
+; GFX11-NEXT: v_bfe_u32 v87, v7, 16, 1
+; GFX11-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20
+; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_or_b32_e32 v96, 0x400000, v7
+; GFX11-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_add_f32_e32 v4, v4, v20
+; GFX11-NEXT: v_add_f32_e32 v20, v80, v71
+; GFX11-NEXT: v_bfe_u32 v71, v9, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v80, 0x400000, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX11-NEXT: v_dual_add_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-NEXT: v_dual_add_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-NEXT: v_add_f32_e32 v26, v52, v51
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_add_f32_e32 v6, v6, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
+; GFX11-NEXT: v_dual_add_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
+; GFX11-NEXT: v_dual_add_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_dual_add_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_dual_add_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add_f32_e32 v29, v38, v37
+; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v15
+; GFX11-NEXT: v_dual_add_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add_f32_e32 v14, v14, v30
+; GFX11-NEXT: v_add_f32_e32 v28, v48, v39
+; GFX11-NEXT: v_dual_add_f32 v30, v36, v35 :: v_dual_add_f32 v33, v34, v33
+; GFX11-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11-NEXT: v_bfe_u32 v35, v14, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v36, 0x400000, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v37, v30, 16, 1
+; GFX11-NEXT: v_bfe_u32 v16, v33, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
+; GFX11-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v48, 0x400000, v13
+; GFX11-NEXT: v_bfe_u32 v49, v29, 16, 1
+; GFX11-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-NEXT: v_or_b32_e32 v50, 0x400000, v29
+; GFX11-NEXT: v_bfe_u32 v51, v12, 16, 1
+; GFX11-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v52, 0x400000, v12
+; GFX11-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-NEXT: v_bfe_u32 v53, v28, 16, 1
+; GFX11-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v54, 0x400000, v28
+; GFX11-NEXT: v_bfe_u32 v55, v11, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v64, 0x400000, v11
+; GFX11-NEXT: v_bfe_u32 v65, v27, 16, 1
+; GFX11-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-NEXT: v_or_b32_e32 v66, 0x400000, v27
+; GFX11-NEXT: v_bfe_u32 v67, v10, 16, 1
+; GFX11-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v68, 0x400000, v10
+; GFX11-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-NEXT: v_bfe_u32 v69, v26, 16, 1
+; GFX11-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11-NEXT: v_bfe_u32 v81, v25, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v82, 0x400000, v25
+; GFX11-NEXT: v_bfe_u32 v83, v8, 16, 1
+; GFX11-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-NEXT: v_or_b32_e32 v84, 0x400000, v8
+; GFX11-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v99, v6, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-NEXT: v_bfe_u32 v101, v22, 16, 1
+; GFX11-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v102, 0x400000, v22
+; GFX11-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v114, 0x400000, v21
+; GFX11-NEXT: v_bfe_u32 v115, v4, 16, 1
+; GFX11-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-NEXT: v_or_b32_e32 v116, 0x400000, v4
+; GFX11-NEXT: v_bfe_u32 v117, v20, 16, 1
+; GFX11-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v118, 0x400000, v20
+; GFX11-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v133, v18, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v134, 0x400000, v18
+; GFX11-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v33, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-NEXT: v_or_b32_e32 v132, 0x400000, v2
+; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
+; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v1, v1, v18, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_perm_b32 v0, v0, v17, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v2, v2, v19, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
+; GFX11-NEXT: v_perm_b32 v3, v3, v20, 0x7060302
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v32
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_add_f32 v17, v31, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
+; GFX11-NEXT: v_add_f32_e32 v15, v15, v18
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v18, v17, 16, 1
+; GFX11-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_or_b32_e32 v21, 0x400000, v15
+; GFX11-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
+; GFX11-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fadd <32 x bfloat> %a, %b
ret <32 x bfloat> %op
}
@@ -13612,59 +12902,31 @@ define <2 x bfloat> @v_fsub_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fsub_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX11TRUE16-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v3, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fsub_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX11FAKE16-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v1, v2, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fsub_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fsub <2 x bfloat> %a, %b
ret <2 x bfloat> %op
}
@@ -13819,40 +13081,35 @@ define <3 x bfloat> @v_fsub_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) {
; GFX11TRUE16-LABEL: v_fsub_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_sub_f32 v1, v1, v3
+; GFX11TRUE16-NEXT: v_sub_f32_e32 v3, v5, v4
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fsub_v3bf16:
@@ -14076,96 +13333,48 @@ define <4 x bfloat> @v_fsub_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fsub_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_sub_f32 v3, v7, v6 :: v_dual_sub_f32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v3, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fsub_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX11FAKE16-NEXT: v_dual_sub_f32 v3, v7, v6 :: v_dual_sub_f32 v4, v5, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v9, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fsub_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_dual_sub_f32 v3, v7, v6 :: v_dual_sub_f32 v4, v5, v4
+; GFX11-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v9, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fsub <4 x bfloat> %a, %b
ret <4 x bfloat> %op
}
@@ -14363,59 +13572,31 @@ define <2 x bfloat> @v_fmul_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fmul_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v3, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fmul_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v2, v3, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v1, v2, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fmul_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fmul <2 x bfloat> %a, %b
ret <2 x bfloat> %op
}
@@ -14570,40 +13751,35 @@ define <3 x bfloat> @v_fmul_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) {
; GFX11TRUE16-LABEL: v_fmul_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v3, v5, v4
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmul_v3bf16:
@@ -14827,96 +14003,48 @@ define <4 x bfloat> @v_fmul_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fmul_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v3, v7, v6 :: v_dual_mul_f32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v3, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fmul_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v3, v7, v6 :: v_dual_mul_f32 v4, v5, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v9, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fmul_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_dual_mul_f32 v3, v7, v6 :: v_dual_mul_f32 v4, v5, v4
+; GFX11-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v9, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fmul <4 x bfloat> %a, %b
ret <4 x bfloat> %op
}
@@ -15262,176 +14390,88 @@ define <8 x bfloat> @v_fmul_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fmul_v8bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v3, v3, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v7, v11, v7 :: v_dual_mul_f32 v2, v2, v6
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v3, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v10, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v3, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v10, v13, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v7, v12, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v11, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v10, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v11, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v4, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fmul_v8bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v3, v3, v7
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v7, v10, v9
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v3, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_mul_f32 v2, v2, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v6, v10, v6
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v6, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v0, v0, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v5, v15, v13
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fmul_v8bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mul_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_mul_f32_e32 v3, v3, v7
+; GFX11-NEXT: v_mul_f32_e32 v7, v10, v9
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v8
+; GFX11-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v11, v3, 16, 1
+; GFX11-NEXT: v_bfe_u32 v12, v7, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
+; GFX11-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_mul_f32 v2, v2, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_bfe_u32 v13, v2, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_mul_f32_e32 v6, v10, v6
+; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v2
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v4
+; GFX11-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
+; GFX11-NEXT: v_dual_mul_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
+; GFX11-NEXT: v_mul_f32_e32 v5, v15, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v13, v0, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11-NEXT: v_bfe_u32 v12, v5, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
+; GFX11-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fmul <8 x bfloat> %a, %b
ret <8 x bfloat> %op
}
@@ -16093,322 +15133,162 @@ define <16 x bfloat> @v_fmul_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fmul_v16bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v18, v19, v18 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v16, v17, v16 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v6, v6, v14 :: v_dual_mul_f32 v7, v7, v15
-; GFX11TRUE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v6, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v7
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v15, v14 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v16, v20, v19
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfi_b32 v7, 0xffff, v7, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v18, v19, v18 :: v_dual_mul_f32 v5, v5, v13
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v15, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_bfi_b32 v6, 0xffff, v6, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v5, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v17, v20 :: v_dual_lshlrev_b32 v20, 16, v11
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v3, v3, v11 :: v_dual_mul_f32 v4, v4, v12
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v4, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
-; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0xffff, v5, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v16, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v19 :: v_dual_lshlrev_b32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v17, v18, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v3, 16, 1
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v2, v2, v10
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v16, v21, v20
-; GFX11TRUE16-NEXT: v_bfi_b32 v4, 0xffff, v4, v15
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v11, v11, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v18, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v17, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v11, v11, v17, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v18, v21 :: v_dual_lshlrev_b32 v21, 16, v8
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v18, v23, v22
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v11, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v11, v22, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v21, v11, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v20, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v20, v22, vcc_lo
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v21, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v18
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v0, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v11
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v8, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v16, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v8, v3
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fmul_v16bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v17, v18, v17
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v6, v6, v14
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v7, v7, v15
-; GFX11FAKE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v4, v4, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v11
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v5, v5, v13
-; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v6, v16, v13 :: v_dual_mul_f32 v13, v19, v18
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v20, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v12, v18, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v13, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v13
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v17, v12, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v18, v19, v18
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v3, v3, v11
-; GFX11FAKE16-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v3, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v9
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v19, v22, v20
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v8
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v19, 16, 1
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v0, v0, v8 :: v_dual_mul_f32 v1, v1, v9
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v9, v22, v20
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v9
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v23, v24, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v20, v25, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v11, v21, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fmul_v16bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mul_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mul_f32_e32 v17, v18, v17
+; GFX11-NEXT: v_mul_f32_e32 v6, v6, v14
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v7, v7, v15
+; GFX11-NEXT: v_bfe_u32 v15, v16, 16, 1
+; GFX11-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
+; GFX11-NEXT: v_bfe_u32 v19, v7, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v19, 0x400000, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v18, v6, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mul_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
+; GFX11-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-NEXT: v_bfe_u32 v20, v17, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v4, v4, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_mul_f32_e32 v5, v5, v13
+; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v16, v13 :: v_dual_mul_f32 v13, v19, v18
+; GFX11-NEXT: v_add3_u32 v16, v20, v17, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v17
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11-NEXT: v_bfe_u32 v21, v5, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v5
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_mul_f32_e32 v12, v18, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v21, v13, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v10
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
+; GFX11-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-NEXT: v_bfe_u32 v20, v4, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v21, 0x400000, v4
+; GFX11-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v17, v12, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v2
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_f32_e32 v18, v19, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v23, v18, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v18
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_mul_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_mul_f32_e32 v3, v3, v11
+; GFX11-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
+; GFX11-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v20, v3, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v19, v2, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v9
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
+; GFX11-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
+; GFX11-NEXT: v_mul_f32_e32 v19, v22, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_bfe_u32 v23, v19, 16, 1
+; GFX11-NEXT: v_dual_mul_f32 v0, v0, v8 :: v_dual_mul_f32 v1, v1, v9
+; GFX11-NEXT: v_mul_f32_e32 v9, v22, v20
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v19
+; GFX11-NEXT: v_or_b32_e32 v25, 0x400000, v0
+; GFX11-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v23, v9, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v24, 0x400000, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_bfe_u32 v20, v0, 16, 1
+; GFX11-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v22, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v23, v24, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v20, v25, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v11, v21, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fmul <16 x bfloat> %a, %b
ret <16 x bfloat> %op
}
@@ -17828,587 +16708,284 @@ define <32 x bfloat> @v_fmul_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fmul_v32bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v5, v5, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v3, v3, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v2, v2, v18
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v18, v84, v83
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v17, v86, v85
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_and_b32 v39, 0xffff0000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v9, v9, v25
-; GFX11TRUE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v24, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v7, v7, v23
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v23, v66, v65 :: v_dual_lshlrev_b32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v4, v4, v20
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v20, v80, v71
-; GFX11TRUE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v21, v70, v69 :: v_dual_lshlrev_b32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v10, v10, v26 :: v_dual_lshlrev_b32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v26, v52, v51 :: v_dual_mul_f32 v25, v54, v53
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v6, v6, v22
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v22, v68, v67
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v27, v50, v49 :: v_dual_and_b32 v38, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v29, v38, v37 :: v_dual_lshlrev_b32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v12, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v14, v14, v30
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v28, v48, v39
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v30, v36, v35 :: v_dual_mul_f32 v33, v34, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11TRUE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11TRUE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11TRUE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11TRUE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_bfi_b32 v11, 0xffff, v11, v28
-; GFX11TRUE16-NEXT: v_bfi_b32 v10, 0xffff, v10, v27
-; GFX11TRUE16-NEXT: v_bfi_b32 v12, 0xffff, v12, v29
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_bfi_b32 v9, 0xffff, v9, v26
-; GFX11TRUE16-NEXT: v_bfi_b32 v13, 0xffff, v13, v30
-; GFX11TRUE16-NEXT: v_bfi_b32 v14, 0xffff, v14, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v8, 0xffff, v8, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v7, 0xffff, v7, v24
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v6, 0xffff, v6, v23
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0xffff, v5, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v4, 0xffff, v4, v21
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v3, v20
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v19
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v18
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v0, v147, v33 :: v_dual_lshlrev_b32 v33, 16, v32
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v15, v15, v33
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v32
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v17, v31, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v15, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v19, v20, v17, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v18, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v15, 0xffff, v15, v17
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fmul_v32bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v21
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v17
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
-; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v16
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
-; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
-; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v2, v2, v18
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v0, v0, v16
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v7, v7, v23
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v23, v66, v65 :: v_dual_mul_f32 v18, v84, v83
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v20
-; GFX11FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v4, v4, v20
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v20, v80, v71
-; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
-; GFX11FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v26, v52, v51
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v6, v6, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v29, v38, v37
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v14, v14, v30
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v28, v48, v39
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v30, v36, v35 :: v_dual_mul_f32 v33, v34, v33
-; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11FAKE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11FAKE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11FAKE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11FAKE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
-; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v18, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v17, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v19, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v20, 0x7060302
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v32
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v17, v31, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v15, v15, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v18, v17, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
-; GFX11FAKE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fmul_v32bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: scratch_load_b32 v32, off, s32
+; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17
+; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX11-NEXT: v_dual_mul_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
+; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19
+; GFX11-NEXT: v_bfe_u32 v103, v5, 16, 1
+; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v112, 0x400000, v5
+; GFX11-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_mul_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16
+; GFX11-NEXT: v_dual_mul_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v129, v19, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v130, 0x400000, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11-NEXT: v_bfe_u32 v119, v3, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_mul_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
+; GFX11-NEXT: v_or_b32_e32 v128, 0x400000, v3
+; GFX11-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v145, v17, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4
+; GFX11-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX11-NEXT: v_mul_f32_e32 v2, v2, v18
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v16
+; GFX11-NEXT: v_dual_mul_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
+; GFX11-NEXT: v_mul_f32_e32 v7, v7, v23
+; GFX11-NEXT: v_dual_mul_f32 v23, v66, v65 :: v_dual_mul_f32 v18, v84, v83
+; GFX11-NEXT: v_dual_mul_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v85, v24, 16, 1
+; GFX11-NEXT: v_bfe_u32 v97, v23, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v86, 0x400000, v24
+; GFX11-NEXT: v_or_b32_e32 v98, 0x400000, v23
+; GFX11-NEXT: v_bfe_u32 v87, v7, 16, 1
+; GFX11-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20
+; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_or_b32_e32 v96, 0x400000, v7
+; GFX11-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_mul_f32_e32 v4, v4, v20
+; GFX11-NEXT: v_mul_f32_e32 v20, v80, v71
+; GFX11-NEXT: v_bfe_u32 v71, v9, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v80, 0x400000, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX11-NEXT: v_dual_mul_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-NEXT: v_dual_mul_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-NEXT: v_mul_f32_e32 v26, v52, v51
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_mul_f32_e32 v6, v6, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
+; GFX11-NEXT: v_dual_mul_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
+; GFX11-NEXT: v_dual_mul_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_dual_mul_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_dual_mul_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_mul_f32_e32 v29, v38, v37
+; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v15
+; GFX11-NEXT: v_dual_mul_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_mul_f32_e32 v14, v14, v30
+; GFX11-NEXT: v_mul_f32_e32 v28, v48, v39
+; GFX11-NEXT: v_dual_mul_f32 v30, v36, v35 :: v_dual_mul_f32 v33, v34, v33
+; GFX11-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11-NEXT: v_bfe_u32 v35, v14, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v36, 0x400000, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v37, v30, 16, 1
+; GFX11-NEXT: v_bfe_u32 v16, v33, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
+; GFX11-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v48, 0x400000, v13
+; GFX11-NEXT: v_bfe_u32 v49, v29, 16, 1
+; GFX11-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-NEXT: v_or_b32_e32 v50, 0x400000, v29
+; GFX11-NEXT: v_bfe_u32 v51, v12, 16, 1
+; GFX11-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v52, 0x400000, v12
+; GFX11-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-NEXT: v_bfe_u32 v53, v28, 16, 1
+; GFX11-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v54, 0x400000, v28
+; GFX11-NEXT: v_bfe_u32 v55, v11, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v64, 0x400000, v11
+; GFX11-NEXT: v_bfe_u32 v65, v27, 16, 1
+; GFX11-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-NEXT: v_or_b32_e32 v66, 0x400000, v27
+; GFX11-NEXT: v_bfe_u32 v67, v10, 16, 1
+; GFX11-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v68, 0x400000, v10
+; GFX11-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-NEXT: v_bfe_u32 v69, v26, 16, 1
+; GFX11-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11-NEXT: v_bfe_u32 v81, v25, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v82, 0x400000, v25
+; GFX11-NEXT: v_bfe_u32 v83, v8, 16, 1
+; GFX11-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-NEXT: v_or_b32_e32 v84, 0x400000, v8
+; GFX11-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v99, v6, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-NEXT: v_bfe_u32 v101, v22, 16, 1
+; GFX11-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v102, 0x400000, v22
+; GFX11-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v114, 0x400000, v21
+; GFX11-NEXT: v_bfe_u32 v115, v4, 16, 1
+; GFX11-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-NEXT: v_or_b32_e32 v116, 0x400000, v4
+; GFX11-NEXT: v_bfe_u32 v117, v20, 16, 1
+; GFX11-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v118, 0x400000, v20
+; GFX11-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v133, v18, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v134, 0x400000, v18
+; GFX11-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v33, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-NEXT: v_or_b32_e32 v132, 0x400000, v2
+; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
+; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v1, v1, v18, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_perm_b32 v0, v0, v17, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v2, v2, v19, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
+; GFX11-NEXT: v_perm_b32 v3, v3, v20, 0x7060302
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v32
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mul_f32 v17, v31, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
+; GFX11-NEXT: v_mul_f32_e32 v15, v15, v18
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v18, v17, 16, 1
+; GFX11-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_or_b32_e32 v21, 0x400000, v15
+; GFX11-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
+; GFX11-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fmul <32 x bfloat> %a, %b
ret <32 x bfloat> %op
}
@@ -19074,59 +17651,31 @@ define <2 x bfloat> @v_minnum_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_minnum_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11TRUE16-NEXT: v_min_f32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v3, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_minnum_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11FAKE16-NEXT: v_min_f32_e32 v2, v3, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v1, v2, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_minnum_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_min_f32_e32 v2, v3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <2 x bfloat> @llvm.minnum.v2bf16(<2 x bfloat> %a, <2 x bfloat> %b)
ret <2 x bfloat> %op
}
@@ -19281,40 +17830,35 @@ define <3 x bfloat> @v_minnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) {
; GFX11TRUE16-LABEL: v_minnum_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: v_min_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_min_f32 v1, v1, v3
+; GFX11TRUE16-NEXT: v_min_f32_e32 v3, v5, v4
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_minnum_v3bf16:
@@ -19538,96 +18082,48 @@ define <4 x bfloat> @v_minnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_minnum_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v3, v7, v6 :: v_dual_min_f32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v3, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_minnum_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v1, v1, v3
-; GFX11FAKE16-NEXT: v_dual_min_f32 v3, v7, v6 :: v_dual_min_f32 v4, v5, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v9, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_minnum_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_dual_min_f32 v3, v7, v6 :: v_dual_min_f32 v4, v5, v4
+; GFX11-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v9, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <4 x bfloat> @llvm.minnum.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b)
ret <4 x bfloat> %op
}
@@ -19973,176 +18469,88 @@ define <8 x bfloat> @v_minnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_minnum_v8bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v3, v3, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v7, v11, v7 :: v_dual_min_f32 v2, v2, v6
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v3, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v10, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v3, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_min_f32_e32 v10, v13, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_min_f32_e32 v7, v12, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v11, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v10, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v11, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v4, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_minnum_v8bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v3, v3, v7
-; GFX11FAKE16-NEXT: v_min_f32_e32 v7, v10, v9
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v3, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_min_f32 v2, v2, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v6, v10, v6
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v6, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v0, v0, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_dual_min_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
-; GFX11FAKE16-NEXT: v_min_f32_e32 v5, v15, v13
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_minnum_v8bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_min_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_min_f32_e32 v3, v3, v7
+; GFX11-NEXT: v_min_f32_e32 v7, v10, v9
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v8
+; GFX11-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v11, v3, 16, 1
+; GFX11-NEXT: v_bfe_u32 v12, v7, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
+; GFX11-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_min_f32 v2, v2, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_bfe_u32 v13, v2, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_min_f32_e32 v6, v10, v6
+; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v2
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_min_f32_e32 v0, v0, v4
+; GFX11-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
+; GFX11-NEXT: v_dual_min_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
+; GFX11-NEXT: v_min_f32_e32 v5, v15, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v13, v0, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11-NEXT: v_bfe_u32 v12, v5, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
+; GFX11-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <8 x bfloat> @llvm.minnum.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b)
ret <8 x bfloat> %op
}
@@ -20804,322 +19212,162 @@ define <16 x bfloat> @v_minnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_minnum_v16bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_min_f32 v18, v19, v18 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v16, v17, v16 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v6, v6, v14 :: v_dual_min_f32 v7, v7, v15
-; GFX11TRUE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v6, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v7
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v15, v14 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_min_f32_e32 v16, v20, v19
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfi_b32 v7, 0xffff, v7, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v18, v19, v18 :: v_dual_min_f32 v5, v5, v13
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v15, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_bfi_b32 v6, 0xffff, v6, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v5, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v17, v20 :: v_dual_lshlrev_b32 v20, 16, v11
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v3, v3, v11 :: v_dual_min_f32 v4, v4, v12
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v4, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
-; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0xffff, v5, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v16, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v19 :: v_dual_lshlrev_b32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v17, v18, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v3, 16, 1
-; GFX11TRUE16-NEXT: v_min_f32_e32 v2, v2, v10
-; GFX11TRUE16-NEXT: v_min_f32_e32 v16, v21, v20
-; GFX11TRUE16-NEXT: v_bfi_b32 v4, 0xffff, v4, v15
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v11, v11, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v18, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v17, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v11, v11, v17, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v18, v21 :: v_dual_lshlrev_b32 v21, 16, v8
-; GFX11TRUE16-NEXT: v_min_f32_e32 v18, v23, v22
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v11, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_min_f32_e32 v11, v22, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v21, v11, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v20, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v20, v22, vcc_lo
-; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v21, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v18
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v0, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v11
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v8, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v16, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v8, v3
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_minnum_v16bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v17, v18, v17
-; GFX11FAKE16-NEXT: v_min_f32_e32 v6, v6, v14
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v7, v7, v15
-; GFX11FAKE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v4, v4, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v11
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_min_f32_e32 v5, v5, v13
-; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v6, v16, v13 :: v_dual_min_f32 v13, v19, v18
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v20, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_min_f32_e32 v12, v18, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v13, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v13
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v17, v12, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v18, v19, v18
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_min_f32_e32 v3, v3, v11
-; GFX11FAKE16-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v3, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v9
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_min_f32_e32 v19, v22, v20
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v8
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v19, 16, 1
-; GFX11FAKE16-NEXT: v_dual_min_f32 v0, v0, v8 :: v_dual_min_f32 v1, v1, v9
-; GFX11FAKE16-NEXT: v_min_f32_e32 v9, v22, v20
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v9
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v23, v24, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v20, v25, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v11, v21, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_minnum_v16bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_min_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_min_f32_e32 v17, v18, v17
+; GFX11-NEXT: v_min_f32_e32 v6, v6, v14
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_min_f32_e32 v7, v7, v15
+; GFX11-NEXT: v_bfe_u32 v15, v16, 16, 1
+; GFX11-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
+; GFX11-NEXT: v_bfe_u32 v19, v7, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v19, 0x400000, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v18, v6, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_dual_min_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
+; GFX11-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-NEXT: v_bfe_u32 v20, v17, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_min_f32_e32 v4, v4, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_min_f32_e32 v5, v5, v13
+; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v16, v13 :: v_dual_min_f32 v13, v19, v18
+; GFX11-NEXT: v_add3_u32 v16, v20, v17, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v17
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11-NEXT: v_bfe_u32 v21, v5, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v5
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_min_f32_e32 v12, v18, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v21, v13, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v10
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
+; GFX11-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-NEXT: v_bfe_u32 v20, v4, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v21, 0x400000, v4
+; GFX11-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v17, v12, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v2
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_f32_e32 v18, v19, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v23, v18, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v18
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_min_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_min_f32_e32 v3, v3, v11
+; GFX11-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
+; GFX11-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v20, v3, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v19, v2, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v9
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
+; GFX11-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
+; GFX11-NEXT: v_min_f32_e32 v19, v22, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_bfe_u32 v23, v19, 16, 1
+; GFX11-NEXT: v_dual_min_f32 v0, v0, v8 :: v_dual_min_f32 v1, v1, v9
+; GFX11-NEXT: v_min_f32_e32 v9, v22, v20
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v19
+; GFX11-NEXT: v_or_b32_e32 v25, 0x400000, v0
+; GFX11-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v23, v9, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v24, 0x400000, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_bfe_u32 v20, v0, 16, 1
+; GFX11-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v22, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v23, v24, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v20, v25, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v11, v21, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <16 x bfloat> @llvm.minnum.v16bf16(<16 x bfloat> %a, <16 x bfloat> %b)
ret <16 x bfloat> %op
}
@@ -22539,587 +20787,284 @@ define <32 x bfloat> @v_minnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_minnum_v32bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_min_f32_e32 v5, v5, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v3, v3, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_min_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11TRUE16-NEXT: v_min_f32_e32 v2, v2, v18
-; GFX11TRUE16-NEXT: v_min_f32_e32 v18, v84, v83
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11TRUE16-NEXT: v_min_f32_e32 v17, v86, v85
-; GFX11TRUE16-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_and_b32 v39, 0xffff0000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_min_f32_e32 v9, v9, v25
-; GFX11TRUE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_min_f32 v24, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_min_f32_e32 v7, v7, v23
-; GFX11TRUE16-NEXT: v_dual_min_f32 v23, v66, v65 :: v_dual_lshlrev_b32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_min_f32_e32 v4, v4, v20
-; GFX11TRUE16-NEXT: v_min_f32_e32 v20, v80, v71
-; GFX11TRUE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11TRUE16-NEXT: v_dual_min_f32 v21, v70, v69 :: v_dual_lshlrev_b32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_dual_min_f32 v10, v10, v26 :: v_dual_lshlrev_b32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_dual_min_f32 v26, v52, v51 :: v_dual_min_f32 v25, v54, v53
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v6, v6, v22
-; GFX11TRUE16-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_min_f32_e32 v22, v68, v67
-; GFX11TRUE16-NEXT: v_dual_min_f32 v27, v50, v49 :: v_dual_and_b32 v38, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_dual_min_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v29, v38, v37 :: v_dual_lshlrev_b32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_dual_min_f32 v12, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v14, v14, v30
-; GFX11TRUE16-NEXT: v_min_f32_e32 v28, v48, v39
-; GFX11TRUE16-NEXT: v_dual_min_f32 v30, v36, v35 :: v_dual_min_f32 v33, v34, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11TRUE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11TRUE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11TRUE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11TRUE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_bfi_b32 v11, 0xffff, v11, v28
-; GFX11TRUE16-NEXT: v_bfi_b32 v10, 0xffff, v10, v27
-; GFX11TRUE16-NEXT: v_bfi_b32 v12, 0xffff, v12, v29
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_bfi_b32 v9, 0xffff, v9, v26
-; GFX11TRUE16-NEXT: v_bfi_b32 v13, 0xffff, v13, v30
-; GFX11TRUE16-NEXT: v_bfi_b32 v14, 0xffff, v14, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v8, 0xffff, v8, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v7, 0xffff, v7, v24
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v6, 0xffff, v6, v23
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0xffff, v5, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v4, 0xffff, v4, v21
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v3, v20
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v19
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v18
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v0, v147, v33 :: v_dual_lshlrev_b32 v33, 16, v32
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v15, v15, v33
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v32
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: v_min_f32_e32 v17, v31, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v15, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v19, v20, v17, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v18, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v15, 0xffff, v15, v17
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_minnum_v32bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v21
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v17
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
-; GFX11FAKE16-NEXT: v_dual_min_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
-; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v16
-; GFX11FAKE16-NEXT: v_dual_min_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
-; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
-; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11FAKE16-NEXT: v_min_f32_e32 v2, v2, v18
-; GFX11FAKE16-NEXT: v_min_f32_e32 v0, v0, v16
-; GFX11FAKE16-NEXT: v_dual_min_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
-; GFX11FAKE16-NEXT: v_min_f32_e32 v7, v7, v23
-; GFX11FAKE16-NEXT: v_dual_min_f32 v23, v66, v65 :: v_dual_min_f32 v18, v84, v83
-; GFX11FAKE16-NEXT: v_dual_min_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v20
-; GFX11FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_min_f32_e32 v4, v4, v20
-; GFX11FAKE16-NEXT: v_min_f32_e32 v20, v80, v71
-; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; GFX11FAKE16-NEXT: v_dual_min_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11FAKE16-NEXT: v_dual_min_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
-; GFX11FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11FAKE16-NEXT: v_min_f32_e32 v26, v52, v51
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v6, v6, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
-; GFX11FAKE16-NEXT: v_dual_min_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
-; GFX11FAKE16-NEXT: v_dual_min_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_dual_min_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
-; GFX11FAKE16-NEXT: v_dual_min_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v29, v38, v37
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15
-; GFX11FAKE16-NEXT: v_dual_min_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_min_f32_e32 v14, v14, v30
-; GFX11FAKE16-NEXT: v_min_f32_e32 v28, v48, v39
-; GFX11FAKE16-NEXT: v_dual_min_f32 v30, v36, v35 :: v_dual_min_f32 v33, v34, v33
-; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11FAKE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11FAKE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11FAKE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11FAKE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
-; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v18, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v17, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v19, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v20, 0x7060302
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v32
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_dual_min_f32 v17, v31, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
-; GFX11FAKE16-NEXT: v_min_f32_e32 v15, v15, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v18, v17, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
-; GFX11FAKE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_minnum_v32bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: scratch_load_b32 v32, off, s32
+; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17
+; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX11-NEXT: v_dual_min_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
+; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19
+; GFX11-NEXT: v_bfe_u32 v103, v5, 16, 1
+; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v112, 0x400000, v5
+; GFX11-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_min_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16
+; GFX11-NEXT: v_dual_min_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v129, v19, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v130, 0x400000, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11-NEXT: v_bfe_u32 v119, v3, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_min_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
+; GFX11-NEXT: v_or_b32_e32 v128, 0x400000, v3
+; GFX11-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v145, v17, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4
+; GFX11-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX11-NEXT: v_min_f32_e32 v2, v2, v18
+; GFX11-NEXT: v_min_f32_e32 v0, v0, v16
+; GFX11-NEXT: v_dual_min_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
+; GFX11-NEXT: v_min_f32_e32 v7, v7, v23
+; GFX11-NEXT: v_dual_min_f32 v23, v66, v65 :: v_dual_min_f32 v18, v84, v83
+; GFX11-NEXT: v_dual_min_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v85, v24, 16, 1
+; GFX11-NEXT: v_bfe_u32 v97, v23, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v86, 0x400000, v24
+; GFX11-NEXT: v_or_b32_e32 v98, 0x400000, v23
+; GFX11-NEXT: v_bfe_u32 v87, v7, 16, 1
+; GFX11-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20
+; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_or_b32_e32 v96, 0x400000, v7
+; GFX11-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_min_f32_e32 v4, v4, v20
+; GFX11-NEXT: v_min_f32_e32 v20, v80, v71
+; GFX11-NEXT: v_bfe_u32 v71, v9, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v80, 0x400000, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX11-NEXT: v_dual_min_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-NEXT: v_dual_min_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-NEXT: v_min_f32_e32 v26, v52, v51
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_min_f32_e32 v6, v6, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
+; GFX11-NEXT: v_dual_min_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
+; GFX11-NEXT: v_dual_min_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_dual_min_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_dual_min_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_min_f32_e32 v29, v38, v37
+; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v15
+; GFX11-NEXT: v_dual_min_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_min_f32_e32 v14, v14, v30
+; GFX11-NEXT: v_min_f32_e32 v28, v48, v39
+; GFX11-NEXT: v_dual_min_f32 v30, v36, v35 :: v_dual_min_f32 v33, v34, v33
+; GFX11-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11-NEXT: v_bfe_u32 v35, v14, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v36, 0x400000, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v37, v30, 16, 1
+; GFX11-NEXT: v_bfe_u32 v16, v33, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
+; GFX11-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v48, 0x400000, v13
+; GFX11-NEXT: v_bfe_u32 v49, v29, 16, 1
+; GFX11-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-NEXT: v_or_b32_e32 v50, 0x400000, v29
+; GFX11-NEXT: v_bfe_u32 v51, v12, 16, 1
+; GFX11-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v52, 0x400000, v12
+; GFX11-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-NEXT: v_bfe_u32 v53, v28, 16, 1
+; GFX11-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v54, 0x400000, v28
+; GFX11-NEXT: v_bfe_u32 v55, v11, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v64, 0x400000, v11
+; GFX11-NEXT: v_bfe_u32 v65, v27, 16, 1
+; GFX11-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-NEXT: v_or_b32_e32 v66, 0x400000, v27
+; GFX11-NEXT: v_bfe_u32 v67, v10, 16, 1
+; GFX11-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v68, 0x400000, v10
+; GFX11-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-NEXT: v_bfe_u32 v69, v26, 16, 1
+; GFX11-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11-NEXT: v_bfe_u32 v81, v25, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v82, 0x400000, v25
+; GFX11-NEXT: v_bfe_u32 v83, v8, 16, 1
+; GFX11-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-NEXT: v_or_b32_e32 v84, 0x400000, v8
+; GFX11-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v99, v6, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-NEXT: v_bfe_u32 v101, v22, 16, 1
+; GFX11-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v102, 0x400000, v22
+; GFX11-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v114, 0x400000, v21
+; GFX11-NEXT: v_bfe_u32 v115, v4, 16, 1
+; GFX11-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-NEXT: v_or_b32_e32 v116, 0x400000, v4
+; GFX11-NEXT: v_bfe_u32 v117, v20, 16, 1
+; GFX11-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v118, 0x400000, v20
+; GFX11-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v133, v18, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v134, 0x400000, v18
+; GFX11-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v33, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-NEXT: v_or_b32_e32 v132, 0x400000, v2
+; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
+; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v1, v1, v18, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_perm_b32 v0, v0, v17, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v2, v2, v19, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
+; GFX11-NEXT: v_perm_b32 v3, v3, v20, 0x7060302
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v32
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_min_f32 v17, v31, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
+; GFX11-NEXT: v_min_f32_e32 v15, v15, v18
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v18, v17, 16, 1
+; GFX11-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_or_b32_e32 v21, 0x400000, v15
+; GFX11-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
+; GFX11-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <32 x bfloat> @llvm.minnum.v32bf16(<32 x bfloat> %a, <32 x bfloat> %b)
ret <32 x bfloat> %op
}
@@ -23326,59 +21271,31 @@ define <2 x bfloat> @v_maxnum_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_maxnum_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11TRUE16-NEXT: v_max_f32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v3, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_maxnum_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11FAKE16-NEXT: v_max_f32_e32 v2, v3, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v1, v2, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_maxnum_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_max_f32_e32 v2, v3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <2 x bfloat> @llvm.maxnum.v2bf16(<2 x bfloat> %a, <2 x bfloat> %b)
ret <2 x bfloat> %op
}
@@ -23533,40 +21450,35 @@ define <3 x bfloat> @v_maxnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) {
; GFX11TRUE16-LABEL: v_maxnum_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: v_max_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_max_f32 v1, v1, v3
+; GFX11TRUE16-NEXT: v_max_f32_e32 v3, v5, v4
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_maxnum_v3bf16:
@@ -23790,96 +21702,48 @@ define <4 x bfloat> @v_maxnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_maxnum_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v3, v7, v6 :: v_dual_max_f32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v3, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_maxnum_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v1, v1, v3
-; GFX11FAKE16-NEXT: v_dual_max_f32 v3, v7, v6 :: v_dual_max_f32 v4, v5, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v9, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_maxnum_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_max_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_dual_max_f32 v3, v7, v6 :: v_dual_max_f32 v4, v5, v4
+; GFX11-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v9, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <4 x bfloat> @llvm.maxnum.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b)
ret <4 x bfloat> %op
}
@@ -24225,176 +22089,88 @@ define <8 x bfloat> @v_maxnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_maxnum_v8bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v3, v3, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v7, v11, v7 :: v_dual_max_f32 v2, v2, v6
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v3, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v10, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v3, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_max_f32_e32 v10, v13, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_max_f32_e32 v7, v12, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v11, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v10, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v11, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v4, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_maxnum_v8bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v3, v3, v7
-; GFX11FAKE16-NEXT: v_max_f32_e32 v7, v10, v9
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v3, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_max_f32 v2, v2, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v6, v10, v6
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v6, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v0, v0, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_dual_max_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
-; GFX11FAKE16-NEXT: v_max_f32_e32 v5, v15, v13
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
-; GFX11FAKE16-NEXT: v_bfe_u32 v12, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_maxnum_v8bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_max_f32 v8, v9, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_max_f32_e32 v3, v3, v7
+; GFX11-NEXT: v_max_f32_e32 v7, v10, v9
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v8
+; GFX11-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v11, v3, 16, 1
+; GFX11-NEXT: v_bfe_u32 v12, v7, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v14, 0x400000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
+; GFX11-NEXT: v_add3_u32 v11, v12, v7, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v11, v12 :: v_dual_max_f32 v2, v2, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_bfe_u32 v13, v2, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_max_f32_e32 v6, v10, v6
+; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v2
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_add3_u32 v10, v13, v2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_perm_b32 v2, v2, v7, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_max_f32_e32 v0, v0, v4
+; GFX11-NEXT: v_add3_u32 v4, v12, v6, 0x7fff
+; GFX11-NEXT: v_dual_max_f32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v10
+; GFX11-NEXT: v_max_f32_e32 v5, v15, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v13, v0, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v15, 0x400000, v1
+; GFX11-NEXT: v_bfe_u32 v12, v5, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v6, v11, v1, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_add3_u32 v10, v12, v5, 0x7fff
+; GFX11-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v6, v15, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v9, v14, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <8 x bfloat> @llvm.maxnum.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b)
ret <8 x bfloat> %op
}
@@ -25056,322 +22832,162 @@ define <16 x bfloat> @v_maxnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_maxnum_v16bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_max_f32 v18, v19, v18 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v16, v17, v16 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v6, v6, v14 :: v_dual_max_f32 v7, v7, v15
-; GFX11TRUE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v6, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v7
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v15, v14 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_max_f32_e32 v16, v20, v19
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfi_b32 v7, 0xffff, v7, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v18, v19, v18 :: v_dual_max_f32 v5, v5, v13
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v15, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_bfi_b32 v6, 0xffff, v6, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v5, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v17, v20 :: v_dual_lshlrev_b32 v20, 16, v11
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v3, v3, v11 :: v_dual_max_f32 v4, v4, v12
-; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v4, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v12, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
-; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0xffff, v5, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v16, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v19 :: v_dual_lshlrev_b32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v17, v18, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v3, 16, 1
-; GFX11TRUE16-NEXT: v_max_f32_e32 v2, v2, v10
-; GFX11TRUE16-NEXT: v_max_f32_e32 v16, v21, v20
-; GFX11TRUE16-NEXT: v_bfi_b32 v4, 0xffff, v4, v15
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v11, v11, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v18, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v17, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v11, v11, v17, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v18, v21 :: v_dual_lshlrev_b32 v21, 16, v8
-; GFX11TRUE16-NEXT: v_max_f32_e32 v18, v23, v22
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v11, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_max_f32_e32 v11, v22, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v21, v11, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v20, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v20, v22, vcc_lo
-; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v21, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v18
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v0, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v11
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v8, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v16, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v8, v3
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_maxnum_v16bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v17, v18, v17
-; GFX11FAKE16-NEXT: v_max_f32_e32 v6, v6, v14
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v7, v7, v15
-; GFX11FAKE16-NEXT: v_bfe_u32 v15, v16, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v4, v4, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v11
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_max_f32_e32 v5, v5, v13
-; GFX11FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v6, v16, v13 :: v_dual_max_f32 v13, v19, v18
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v20, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v5, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_max_f32_e32 v12, v18, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v21, v13, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v13
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v17, v12, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v18, v19, v18
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_max_f32_e32 v3, v3, v11
-; GFX11FAKE16-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v3, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v2, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v9
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
-; GFX11FAKE16-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_max_f32_e32 v19, v22, v20
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v8
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v19, 16, 1
-; GFX11FAKE16-NEXT: v_dual_max_f32 v0, v0, v8 :: v_dual_max_f32 v1, v1, v9
-; GFX11FAKE16-NEXT: v_max_f32_e32 v9, v22, v20
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v0
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v23, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v9
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v22, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v23, v24, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v20, v25, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v11, v21, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_maxnum_v16bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_max_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_max_f32_e32 v17, v18, v17
+; GFX11-NEXT: v_max_f32_e32 v6, v6, v14
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11-NEXT: v_add3_u32 v14, v21, v17, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_max_f32_e32 v7, v7, v15
+; GFX11-NEXT: v_bfe_u32 v15, v16, 16, 1
+; GFX11-NEXT: v_add3_u32 v15, v15, v16, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_lshlrev_b32 v20, 16, v5
+; GFX11-NEXT: v_bfe_u32 v19, v7, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_add3_u32 v18, v19, v7, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v19, 0x400000, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v18, v6, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_perm_b32 v7, v7, v15, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_dual_max_f32 v17, v20, v19 :: v_dual_cndmask_b32 v14, v14, v16
+; GFX11-NEXT: v_add3_u32 v16, v18, v6, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-NEXT: v_bfe_u32 v20, v17, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_max_f32_e32 v4, v4, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_max_f32_e32 v5, v5, v13
+; GFX11-NEXT: v_or_b32_e32 v13, 0x400000, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v16, v13 :: v_dual_max_f32 v13, v19, v18
+; GFX11-NEXT: v_add3_u32 v16, v20, v17, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v17
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_perm_b32 v6, v6, v14, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11-NEXT: v_bfe_u32 v21, v5, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v5
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_max_f32_e32 v12, v18, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v21, v13, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v10
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
+; GFX11-NEXT: v_add3_u32 v17, v21, v13, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v19, 0x400000, v13
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-NEXT: v_bfe_u32 v20, v4, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v21, 0x400000, v4
+; GFX11-NEXT: v_perm_b32 v5, v5, v16, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v17, v19, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v17, v12, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v2
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_max_f32_e32 v18, v19, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v23, v18, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v17, 0x400000, v18
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_max_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_max_f32_e32 v3, v3, v11
+; GFX11-NEXT: v_add3_u32 v11, v20, v4, 0x7fff
+; GFX11-NEXT: v_add3_u32 v10, v23, v18, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v20, v3, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_add3_u32 v19, v20, v3, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
+; GFX11-NEXT: v_bfe_u32 v19, v2, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v9
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-NEXT: v_or_b32_e32 v18, 0x400000, v2
+; GFX11-NEXT: v_perm_b32 v3, v3, v12, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
+; GFX11-NEXT: v_add3_u32 v17, v19, v2, 0x7fff
+; GFX11-NEXT: v_max_f32_e32 v19, v22, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_bfe_u32 v23, v19, 16, 1
+; GFX11-NEXT: v_dual_max_f32 v0, v0, v8 :: v_dual_max_f32 v1, v1, v9
+; GFX11-NEXT: v_max_f32_e32 v9, v22, v20
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add3_u32 v20, v23, v19, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v19
+; GFX11-NEXT: v_or_b32_e32 v25, 0x400000, v0
+; GFX11-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v23, v9, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v24, 0x400000, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v22, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_bfe_u32 v20, v0, 16, 1
+; GFX11-NEXT: v_add3_u32 v23, v23, v9, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v22, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v23, v24, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v20, v25, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v11, v21, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <16 x bfloat> @llvm.maxnum.v16bf16(<16 x bfloat> %a, <16 x bfloat> %b)
ret <16 x bfloat> %op
}
@@ -26791,587 +24407,284 @@ define <32 x bfloat> @v_maxnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX10-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_maxnum_v32bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_max_f32_e32 v5, v5, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v3, v3, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_max_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11TRUE16-NEXT: v_max_f32_e32 v2, v2, v18
-; GFX11TRUE16-NEXT: v_max_f32_e32 v18, v84, v83
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11TRUE16-NEXT: v_max_f32_e32 v17, v86, v85
-; GFX11TRUE16-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_and_b32 v39, 0xffff0000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_max_f32_e32 v9, v9, v25
-; GFX11TRUE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_max_f32 v24, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_max_f32_e32 v7, v7, v23
-; GFX11TRUE16-NEXT: v_dual_max_f32 v23, v66, v65 :: v_dual_lshlrev_b32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_max_f32_e32 v4, v4, v20
-; GFX11TRUE16-NEXT: v_max_f32_e32 v20, v80, v71
-; GFX11TRUE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11TRUE16-NEXT: v_dual_max_f32 v21, v70, v69 :: v_dual_lshlrev_b32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_dual_max_f32 v10, v10, v26 :: v_dual_lshlrev_b32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_dual_max_f32 v26, v52, v51 :: v_dual_max_f32 v25, v54, v53
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v6, v6, v22
-; GFX11TRUE16-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_max_f32_e32 v22, v68, v67
-; GFX11TRUE16-NEXT: v_dual_max_f32 v27, v50, v49 :: v_dual_and_b32 v38, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_dual_max_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v29, v38, v37 :: v_dual_lshlrev_b32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_dual_max_f32 v12, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v14, v14, v30
-; GFX11TRUE16-NEXT: v_max_f32_e32 v28, v48, v39
-; GFX11TRUE16-NEXT: v_dual_max_f32 v30, v36, v35 :: v_dual_max_f32 v33, v34, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11TRUE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11TRUE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11TRUE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11TRUE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_bfi_b32 v11, 0xffff, v11, v28
-; GFX11TRUE16-NEXT: v_bfi_b32 v10, 0xffff, v10, v27
-; GFX11TRUE16-NEXT: v_bfi_b32 v12, 0xffff, v12, v29
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_bfi_b32 v9, 0xffff, v9, v26
-; GFX11TRUE16-NEXT: v_bfi_b32 v13, 0xffff, v13, v30
-; GFX11TRUE16-NEXT: v_bfi_b32 v14, 0xffff, v14, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v8, 0xffff, v8, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v7, 0xffff, v7, v24
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v6, 0xffff, v6, v23
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0xffff, v5, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v4, 0xffff, v4, v21
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0xffff, v3, v20
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v19
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v18
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v0, v147, v33 :: v_dual_lshlrev_b32 v33, 16, v32
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v15, v15, v33
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v17
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v32
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: v_max_f32_e32 v17, v31, v17
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v15, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v19, v20, v17, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v18, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v15, 0xffff, v15, v17
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_maxnum_v32bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v21
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v83, 16, v17
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v84, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
-; GFX11FAKE16-NEXT: v_dual_max_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v24
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v71, 16, v19
-; GFX11FAKE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
-; GFX11FAKE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v80, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v16
-; GFX11FAKE16-NEXT: v_dual_max_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v86, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
-; GFX11FAKE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11FAKE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v70, 16, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v23
-; GFX11FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11FAKE16-NEXT: v_max_f32_e32 v2, v2, v18
-; GFX11FAKE16-NEXT: v_max_f32_e32 v0, v0, v16
-; GFX11FAKE16-NEXT: v_dual_max_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
-; GFX11FAKE16-NEXT: v_max_f32_e32 v7, v7, v23
-; GFX11FAKE16-NEXT: v_dual_max_f32 v23, v66, v65 :: v_dual_max_f32 v18, v84, v83
-; GFX11FAKE16-NEXT: v_dual_max_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11FAKE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11FAKE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v20
-; GFX11FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11FAKE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11FAKE16-NEXT: v_max_f32_e32 v4, v4, v20
-; GFX11FAKE16-NEXT: v_max_f32_e32 v20, v80, v71
-; GFX11FAKE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v29
-; GFX11FAKE16-NEXT: v_dual_max_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11FAKE16-NEXT: v_dual_max_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
-; GFX11FAKE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11FAKE16-NEXT: v_max_f32_e32 v26, v52, v51
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v6, v6, v22
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v13
-; GFX11FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11FAKE16-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
-; GFX11FAKE16-NEXT: v_dual_max_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
-; GFX11FAKE16-NEXT: v_dual_max_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
-; GFX11FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11FAKE16-NEXT: v_dual_max_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
-; GFX11FAKE16-NEXT: v_dual_max_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v29, v38, v37
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v15
-; GFX11FAKE16-NEXT: v_dual_max_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_max_f32_e32 v14, v14, v30
-; GFX11FAKE16-NEXT: v_max_f32_e32 v28, v48, v39
-; GFX11FAKE16-NEXT: v_dual_max_f32 v30, v36, v35 :: v_dual_max_f32 v33, v34, v33
-; GFX11FAKE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11FAKE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11FAKE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11FAKE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11FAKE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11FAKE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11FAKE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11FAKE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11FAKE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11FAKE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11FAKE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11FAKE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11FAKE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11FAKE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11FAKE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11FAKE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11FAKE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11FAKE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11FAKE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11FAKE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11FAKE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11FAKE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11FAKE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11FAKE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
-; GFX11FAKE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11FAKE16-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
-; GFX11FAKE16-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11FAKE16-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11FAKE16-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v18, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v17, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v2, v2, v19, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
-; GFX11FAKE16-NEXT: v_perm_b32 v3, v3, v20, 0x7060302
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v32
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_dual_max_f32 v17, v31, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
-; GFX11FAKE16-NEXT: v_max_f32_e32 v15, v15, v18
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v18, v17, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
-; GFX11FAKE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_maxnum_v32bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: scratch_load_b32 v32, off, s32
+; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17
+; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX11-NEXT: v_dual_max_f32 v5, v5, v21 :: v_dual_and_b32 v26, 0xffff0000, v26
+; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19
+; GFX11-NEXT: v_bfe_u32 v103, v5, 16, 1
+; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v112, 0x400000, v5
+; GFX11-NEXT: v_or_b32_e32 v144, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_max_f32 v3, v3, v19 :: v_dual_lshlrev_b32 v54, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16
+; GFX11-NEXT: v_dual_max_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v64, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v129, v19, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v130, 0x400000, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11-NEXT: v_bfe_u32 v119, v3, 16, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_max_f32 v17, v86, v85 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_lshlrev_b32 v39, 16, v27
+; GFX11-NEXT: v_or_b32_e32 v128, 0x400000, v3
+; GFX11-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v145, v17, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4
+; GFX11-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX11-NEXT: v_max_f32_e32 v2, v2, v18
+; GFX11-NEXT: v_max_f32_e32 v0, v0, v16
+; GFX11-NEXT: v_dual_max_f32 v24, v64, v55 :: v_dual_lshlrev_b32 v37, 16, v28
+; GFX11-NEXT: v_max_f32_e32 v7, v7, v23
+; GFX11-NEXT: v_dual_max_f32 v23, v66, v65 :: v_dual_max_f32 v18, v84, v83
+; GFX11-NEXT: v_dual_max_f32 v9, v9, v25 :: v_dual_and_b32 v28, 0xffff0000, v28
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v85, v24, 16, 1
+; GFX11-NEXT: v_bfe_u32 v97, v23, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v86, 0x400000, v24
+; GFX11-NEXT: v_or_b32_e32 v98, 0x400000, v23
+; GFX11-NEXT: v_bfe_u32 v87, v7, 16, 1
+; GFX11-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20
+; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_or_b32_e32 v96, 0x400000, v7
+; GFX11-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_max_f32_e32 v4, v4, v20
+; GFX11-NEXT: v_max_f32_e32 v20, v80, v71
+; GFX11-NEXT: v_bfe_u32 v71, v9, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v80, 0x400000, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX11-NEXT: v_dual_max_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-NEXT: v_dual_max_f32 v10, v10, v26 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-NEXT: v_max_f32_e32 v26, v52, v51
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_max_f32_e32 v6, v6, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_lshlrev_b32 v34, 16, v14
+; GFX11-NEXT: v_dual_max_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v33, 16, v30
+; GFX11-NEXT: v_dual_max_f32 v27, v50, v49 :: v_dual_lshlrev_b32 v38, 16, v12
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_dual_max_f32 v25, v54, v53 :: v_dual_and_b32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_dual_max_f32 v13, v13, v29 :: v_dual_and_b32 v30, 0xffff0000, v30
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_max_f32_e32 v29, v38, v37
+; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v15
+; GFX11-NEXT: v_dual_max_f32 v12, v12, v28 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_max_f32_e32 v14, v14, v30
+; GFX11-NEXT: v_max_f32_e32 v28, v48, v39
+; GFX11-NEXT: v_dual_max_f32 v30, v36, v35 :: v_dual_max_f32 v33, v34, v33
+; GFX11-NEXT: v_bfe_u32 v39, v13, 16, 1
+; GFX11-NEXT: v_bfe_u32 v35, v14, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v36, 0x400000, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v37, v30, 16, 1
+; GFX11-NEXT: v_bfe_u32 v16, v33, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
+; GFX11-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v48, 0x400000, v13
+; GFX11-NEXT: v_bfe_u32 v49, v29, 16, 1
+; GFX11-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-NEXT: v_or_b32_e32 v50, 0x400000, v29
+; GFX11-NEXT: v_bfe_u32 v51, v12, 16, 1
+; GFX11-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v52, 0x400000, v12
+; GFX11-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-NEXT: v_bfe_u32 v53, v28, 16, 1
+; GFX11-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v54, 0x400000, v28
+; GFX11-NEXT: v_bfe_u32 v55, v11, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v64, 0x400000, v11
+; GFX11-NEXT: v_bfe_u32 v65, v27, 16, 1
+; GFX11-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-NEXT: v_or_b32_e32 v66, 0x400000, v27
+; GFX11-NEXT: v_bfe_u32 v67, v10, 16, 1
+; GFX11-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v68, 0x400000, v10
+; GFX11-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-NEXT: v_bfe_u32 v69, v26, 16, 1
+; GFX11-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v70, 0x400000, v26
+; GFX11-NEXT: v_bfe_u32 v81, v25, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v82, 0x400000, v25
+; GFX11-NEXT: v_bfe_u32 v83, v8, 16, 1
+; GFX11-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-NEXT: v_or_b32_e32 v84, 0x400000, v8
+; GFX11-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v99, v6, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v100, 0x400000, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-NEXT: v_bfe_u32 v101, v22, 16, 1
+; GFX11-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v102, 0x400000, v22
+; GFX11-NEXT: v_bfe_u32 v113, v21, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v114, 0x400000, v21
+; GFX11-NEXT: v_bfe_u32 v115, v4, 16, 1
+; GFX11-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-NEXT: v_or_b32_e32 v116, 0x400000, v4
+; GFX11-NEXT: v_bfe_u32 v117, v20, 16, 1
+; GFX11-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v118, 0x400000, v20
+; GFX11-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v133, v18, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v134, 0x400000, v18
+; GFX11-NEXT: v_bfe_u32 v147, v0, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v33, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v131, v2, 16, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-NEXT: v_or_b32_e32 v132, 0x400000, v2
+; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
+; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_perm_b32 v14, v14, v16, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v1, v1, v18, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_perm_b32 v0, v0, v17, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v2, v2, v19, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
+; GFX11-NEXT: v_perm_b32 v3, v3, v20, 0x7060302
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v32
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_max_f32 v17, v31, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
+; GFX11-NEXT: v_max_f32_e32 v15, v15, v18
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v18, v17, 16, 1
+; GFX11-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-NEXT: v_or_b32_e32 v21, 0x400000, v15
+; GFX11-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
+; GFX11-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v15, v15, v17, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <32 x bfloat> @llvm.maxnum.v32bf16(<32 x bfloat> %a, <32 x bfloat> %b)
ret <32 x bfloat> %op
}
@@ -27748,7 +25061,8 @@ define bfloat @v_log_bf16(bfloat %a) {
; GCN-NEXT: v_mov_b32_e32 v1, 0x41b17218
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GCN-NEXT: v_ldexp_f32_e32 v0, v0, v2
; GCN-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_and_b32_e32 v2, 0xfffff000, v0
@@ -27774,7 +25088,8 @@ define bfloat @v_log_bf16(bfloat %a) {
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: s_mov_b32 s4, 0x800000
; GFX7-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX7-NEXT: v_log_f32_e32 v0, v0
; GFX7-NEXT: s_mov_b32 s4, 0x3f317217
@@ -27798,7 +25113,8 @@ define bfloat @v_log_bf16(bfloat %a) {
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: s_mov_b32 s4, 0x800000
; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: v_log_f32_e32 v0, v0
; GFX8-NEXT: s_mov_b32 s4, 0x7f800000
@@ -27831,7 +25147,8 @@ define bfloat @v_log_bf16(bfloat %a) {
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: s_mov_b32 s4, 0x800000
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: v_log_f32_e32 v0, v0
; GFX9-NEXT: s_mov_b32 s4, 0x3f317217
@@ -27860,7 +25177,8 @@ define bfloat @v_log_bf16(bfloat %a) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
@@ -27885,28 +25203,30 @@ define bfloat @v_log_bf16(bfloat %a) {
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX11-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
; GFX11-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, vcc_lo
; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call bfloat @llvm.log.bf16(bfloat %a)
@@ -27922,7 +25242,8 @@ define bfloat @v_log2_bf16(bfloat %a) {
; GCN-NEXT: v_mov_b32_e32 v1, 0x42000000
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GCN-NEXT: v_ldexp_f32_e32 v0, v0, v2
; GCN-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
@@ -27937,7 +25258,8 @@ define bfloat @v_log2_bf16(bfloat %a) {
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: s_mov_b32 s4, 0x800000
; GFX7-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX7-NEXT: v_log_f32_e32 v0, v0
; GFX7-NEXT: v_mov_b32_e32 v1, 0x42000000
@@ -27952,7 +25274,8 @@ define bfloat @v_log2_bf16(bfloat %a) {
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: s_mov_b32 s4, 0x800000
; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: v_log_f32_e32 v0, v0
; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000
@@ -27973,7 +25296,8 @@ define bfloat @v_log2_bf16(bfloat %a) {
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: s_mov_b32 s4, 0x800000
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
; GFX9-NEXT: v_log_f32_e32 v0, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000
@@ -27993,8 +25317,9 @@ define bfloat @v_log2_bf16(bfloat %a) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX10-NEXT: v_ldexp_f32 v0, v0, v2
; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_sub_f32_e32 v0, v0, v1
@@ -28012,20 +25337,21 @@ define bfloat @v_log2_bf16(bfloat %a) {
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call bfloat @llvm.log2.bf16(bfloat %a)
@@ -28042,7 +25368,8 @@ define bfloat @v_log10_bf16(bfloat %a) {
; GCN-NEXT: v_mov_b32_e32 v1, 0x411a209b
; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GCN-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GCN-NEXT: v_ldexp_f32_e32 v0, v0, v2
; GCN-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_and_b32_e32 v2, 0xfffff000, v0
@@ -28068,7 +25395,8 @@ define bfloat @v_log10_bf16(bfloat %a) {
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX7-NEXT: s_mov_b32 s4, 0x800000
; GFX7-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX7-NEXT: v_log_f32_e32 v0, v0
; GFX7-NEXT: s_mov_b32 s4, 0x3e9a209a
@@ -28092,7 +25420,8 @@ define bfloat @v_log10_bf16(bfloat %a) {
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: s_mov_b32 s4, 0x800000
; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: v_log_f32_e32 v0, v0
; GFX8-NEXT: s_mov_b32 s4, 0x7f800000
@@ -28125,7 +25454,8 @@ define bfloat @v_log10_bf16(bfloat %a) {
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: s_mov_b32 s4, 0x800000
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: v_log_f32_e32 v0, v0
; GFX9-NEXT: s_mov_b32 s4, 0x3e9a209a
@@ -28154,7 +25484,8 @@ define bfloat @v_log10_bf16(bfloat %a) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1
; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
@@ -28179,28 +25510,30 @@ define bfloat @v_log10_bf16(bfloat %a) {
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX11-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
; GFX11-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, vcc_lo
; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call bfloat @llvm.log10.bf16(bfloat %a)
@@ -31348,8 +28681,8 @@ define <2 x i16> @v_fptosi_v2bf16_to_v2i16(<2 x bfloat> %x) {
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fptosi_v2bf16_to_v2i16:
@@ -31452,9 +28785,9 @@ define <3 x i16> @v_fptosi_v3bf16_to_v3i16(<3 x bfloat> %x) {
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fptosi_v3bf16_to_v3i16:
@@ -31575,18 +28908,18 @@ define <4 x i16> @v_fptosi_v4bf16_to_v4i16(<4 x bfloat> %x) {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fptosi_v4bf16_to_v4i16:
@@ -32992,55 +30325,29 @@ define <2 x bfloat> @v_sitofp_v2i16_to_v2bf16(<2 x i16> %x) {
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_sitofp_v2i16_to_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_bfe_i32 v1, v0, 0, 16
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_sitofp_v2i16_to_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_bfe_i32 v1, v0, 0, 16
-; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_sitofp_v2i16_to_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX11-NEXT: v_ashrrev_i32_e32 v0, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = sitofp <2 x i16> %x to <2 x bfloat>
ret <2 x bfloat> %op
}
@@ -33158,37 +30465,33 @@ define <3 x bfloat> @v_sitofp_v3i16_to_v3bf16(<3 x i16> %x) {
; GFX11TRUE16-LABEL: v_sitofp_v3i16_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11TRUE16-NEXT: v_bfe_i32 v2, v0, 0, 16
; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v3i16_to_v3bf16:
@@ -33364,87 +30667,45 @@ define <4 x bfloat> @v_sitofp_v4i16_to_v4bf16(<4 x i16> %x) {
; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_sitofp_v4i16_to_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_bfe_i32 v2, v1, 0, 16
-; GFX11TRUE16-NEXT: v_bfe_i32 v3, v0, 0, 16
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v10, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v2, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v3, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_sitofp_v4i16_to_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_bfe_i32 v2, v1, 0, 16
-; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v1, 16, v1
-; GFX11FAKE16-NEXT: v_bfe_i32 v3, v0, 0, 16
-; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v3, v3
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v10, v0, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v10, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v10, v11, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_sitofp_v4i16_to_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_bfe_i32 v2, v1, 0, 16
+; GFX11-NEXT: v_ashrrev_i32_e32 v1, 16, v1
+; GFX11-NEXT: v_bfe_i32 v3, v0, 0, 16
+; GFX11-NEXT: v_ashrrev_i32_e32 v0, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cvt_f32_i32_e32 v3, v3
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-NEXT: v_bfe_u32 v10, v0, 16, 1
+; GFX11-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v10, v10, v0, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v10, v11, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = sitofp <4 x i16> %x to <4 x bfloat>
ret <4 x bfloat> %op
}
@@ -33597,49 +30858,26 @@ define <2 x bfloat> @v_sitofp_v2i32_to_v2bf16(<2 x i32> %x) {
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_sitofp_v2i32_to_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v1
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_sitofp_v2i32_to_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_sitofp_v2i32_to_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = sitofp <2 x i32> %x to <2 x bfloat>
ret <2 x bfloat> %op
}
@@ -33752,32 +30990,30 @@ define <3 x bfloat> @v_sitofp_v3i32_to_v3bf16(<3 x i32> %x) {
; GFX11TRUE16-LABEL: v_sitofp_v3i32_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v3i32_to_v3bf16:
@@ -33939,76 +31175,39 @@ define <4 x bfloat> @v_sitofp_v4i32_to_v4bf16(<4 x i32> %x) {
; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_sitofp_v4i32_to_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v3, v3
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v10, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v4, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v1
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v2, v3
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_sitofp_v4i32_to_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v3, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11FAKE16-NEXT: v_bfe_u32 v7, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_sitofp_v4i32_to_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX11-NEXT: v_cvt_f32_i32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-NEXT: v_bfe_u32 v7, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v9, v1, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc_lo
+; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = sitofp <4 x i32> %x to <4 x bfloat>
ret <4 x bfloat> %op
}
@@ -34343,111 +31542,57 @@ define <2 x bfloat> @v_sitofp_v2i64_to_v2bf16(<2 x i64> %x) {
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_sitofp_v2i64_to_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v4, v0, v1
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v5, v1
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v6, v2, v3
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v7, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v4, 31, v4
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v6, 31, v6
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v4, 32, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v6, 32, v6
-; GFX11TRUE16-NEXT: v_min_u32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
-; GFX11TRUE16-NEXT: v_min_u32_e32 v5, v5, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]
-; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v5
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v1
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_sitofp_v2i64_to_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_xor_b32_e32 v4, v0, v1
-; GFX11FAKE16-NEXT: v_xor_b32_e32 v5, v2, v3
-; GFX11FAKE16-NEXT: v_cls_i32_e32 v6, v1
-; GFX11FAKE16-NEXT: v_cls_i32_e32 v7, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v4, 31, v4
-; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v5, 31, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v7, -1, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v4, 32, v4
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v5, 32, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_min_u32_e32 v4, v6, v4
-; GFX11FAKE16-NEXT: v_min_u32_e32 v5, v7, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11FAKE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v2, 32, v4
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v3, 32, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX11FAKE16-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_sitofp_v2i64_to_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_xor_b32_e32 v4, v0, v1
+; GFX11-NEXT: v_xor_b32_e32 v5, v2, v3
+; GFX11-NEXT: v_cls_i32_e32 v6, v1
+; GFX11-NEXT: v_cls_i32_e32 v7, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v4
+; GFX11-NEXT: v_ashrrev_i32_e32 v5, 31, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add_nc_u32_e32 v6, -1, v6
+; GFX11-NEXT: v_add_nc_u32_e32 v7, -1, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 32, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v5, 32, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_u32_e32 v4, v6, v4
+; GFX11-NEXT: v_min_u32_e32 v5, v7, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_u32_e32 v0, 1, v0
+; GFX11-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 32, v4
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, 32, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = sitofp <2 x i64> %x to <2 x bfloat>
ret <2 x bfloat> %op
}
@@ -34725,74 +31870,68 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) {
; GFX11TRUE16-LABEL: v_sitofp_v3i64_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v6, v0, v1
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v7, v1
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v8, v2, v3
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v9, v4, v5
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v10, v3
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v6, 31, v6
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v7, -1, v7
+; GFX11TRUE16-NEXT: v_xor_b32_e32 v7, v4, v5
+; GFX11TRUE16-NEXT: v_cls_i32_e32 v6, v5
+; GFX11TRUE16-NEXT: v_xor_b32_e32 v8, v0, v1
+; GFX11TRUE16-NEXT: v_xor_b32_e32 v9, v2, v3
+; GFX11TRUE16-NEXT: v_cls_i32_e32 v10, v1
+; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v7
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v8, 31, v8
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v11, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v6, 32, v6
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, 32, v8
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v6, v7, v6
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v9
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, -1, v10
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, -1, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cls_i32_e32 v11, v3
+; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v9, 31, v9
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v7, 32, v7
-; GFX11TRUE16-NEXT: v_min_u32_e32 v8, v9, v8
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v7, v10, v7
-; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v8, v[2:3]
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, v1, v0
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, -1, v10
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, 32, v8
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v11, -1, v11
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, 32, v9
+; GFX11TRUE16-NEXT: v_min_u32_e32 v6, v6, v7
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v7, v[4:5]
-; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v4, 32, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v5, v9
+; GFX11TRUE16-NEXT: v_min_u32_e32 v7, v10, v8
+; GFX11TRUE16-NEXT: v_min_u32_e32 v8, v11, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v8, v[2:3]
+; GFX11TRUE16-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: v_ldexp_f32 v3, v5, v4
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v4, 32, v8
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v8
; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v2
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v7
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v6
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v4, v4
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v3, 32, v7
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v5
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v4, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX11TRUE16-NEXT: v_ldexp_f32 v2, v2, v5
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v3i64_to_v3bf16:
@@ -35216,174 +32355,87 @@ define <4 x bfloat> @v_sitofp_v4i64_to_v4bf16(<4 x i64> %x) {
; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_sitofp_v4i64_to_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v8, v6, v7
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v9, v4, v5
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v10, v7
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v11, v5
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v12, v0, v1
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v8, 31, v8
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v9, 31, v9
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, -1, v10
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v11, -1, v11
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v13, v1
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, 32, v8
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, 32, v9
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v12, 31, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v8, v10, v8
-; GFX11TRUE16-NEXT: v_min_u32_e32 v9, v11, v9
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v10, v2, v3
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v11, -1, v13
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v12, 32, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[6:7], v8, v[6:7]
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v13, v3
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v10, 31, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v9, v[4:5]
-; GFX11TRUE16-NEXT: v_min_u32_e32 v11, v11, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v12, -1, v13
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, 32, v10
-; GFX11TRUE16-NEXT: v_min_u32_e32 v6, 1, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v11, v[0:1]
-; GFX11TRUE16-NEXT: v_min_u32_e32 v4, 1, v4
-; GFX11TRUE16-NEXT: v_min_u32_e32 v10, v12, v10
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v7, 32, v11
-; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v5, v6
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v6, 32, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v4, v4
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v8
-; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v5, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v6, 32, v10
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v7
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v7, v0, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11TRUE16-NEXT: v_ldexp_f32 v2, v2, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v7, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v3, v1
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v2
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_sitofp_v4i64_to_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_xor_b32_e32 v8, v4, v5
-; GFX11FAKE16-NEXT: v_cls_i32_e32 v9, v5
-; GFX11FAKE16-NEXT: v_xor_b32_e32 v11, v6, v7
-; GFX11FAKE16-NEXT: v_xor_b32_e32 v13, v0, v1
-; GFX11FAKE16-NEXT: v_cls_i32_e32 v10, v7
-; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v8, 31, v8
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v9, -1, v9
-; GFX11FAKE16-NEXT: v_cls_i32_e32 v12, v1
-; GFX11FAKE16-NEXT: v_xor_b32_e32 v14, v2, v3
-; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v11, 31, v11
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v8, 32, v8
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v10, -1, v10
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v12, -1, v12
-; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v14, 31, v14
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v11, 32, v11
-; GFX11FAKE16-NEXT: v_min_u32_e32 v8, v9, v8
-; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v9, 31, v13
-; GFX11FAKE16-NEXT: v_cls_i32_e32 v13, v3
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v14, 32, v14
-; GFX11FAKE16-NEXT: v_min_u32_e32 v10, v10, v11
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v9, 32, v9
-; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v13, -1, v13
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[6:7], v10, v[6:7]
-; GFX11FAKE16-NEXT: v_min_u32_e32 v9, v12, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_min_u32_e32 v11, v13, v14
-; GFX11FAKE16-NEXT: v_min_u32_e32 v4, 1, v4
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3]
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11FAKE16-NEXT: v_min_u32_e32 v5, 1, v6
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v6, 32, v8
-; GFX11FAKE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11FAKE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v4, v4
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, v7, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_ldexp_f32 v2, v4, v6
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v3, v5
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v4, 32, v10
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v5, 32, v9
-; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v6, 32, v11
-; GFX11FAKE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11FAKE16-NEXT: v_ldexp_f32 v3, v3, v4
-; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v5
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11FAKE16-NEXT: v_ldexp_f32 v1, v1, v6
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v7, v0, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v6, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v5, v7, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_sitofp_v4i64_to_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_xor_b32_e32 v8, v4, v5
+; GFX11-NEXT: v_cls_i32_e32 v9, v5
+; GFX11-NEXT: v_xor_b32_e32 v11, v6, v7
+; GFX11-NEXT: v_xor_b32_e32 v13, v0, v1
+; GFX11-NEXT: v_cls_i32_e32 v10, v7
+; GFX11-NEXT: v_ashrrev_i32_e32 v8, 31, v8
+; GFX11-NEXT: v_add_nc_u32_e32 v9, -1, v9
+; GFX11-NEXT: v_cls_i32_e32 v12, v1
+; GFX11-NEXT: v_xor_b32_e32 v14, v2, v3
+; GFX11-NEXT: v_ashrrev_i32_e32 v11, 31, v11
+; GFX11-NEXT: v_add_nc_u32_e32 v8, 32, v8
+; GFX11-NEXT: v_add_nc_u32_e32 v10, -1, v10
+; GFX11-NEXT: v_add_nc_u32_e32 v12, -1, v12
+; GFX11-NEXT: v_ashrrev_i32_e32 v14, 31, v14
+; GFX11-NEXT: v_add_nc_u32_e32 v11, 32, v11
+; GFX11-NEXT: v_min_u32_e32 v8, v9, v8
+; GFX11-NEXT: v_ashrrev_i32_e32 v9, 31, v13
+; GFX11-NEXT: v_cls_i32_e32 v13, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v14, 32, v14
+; GFX11-NEXT: v_min_u32_e32 v10, v10, v11
+; GFX11-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
+; GFX11-NEXT: v_add_nc_u32_e32 v9, 32, v9
+; GFX11-NEXT: v_add_nc_u32_e32 v13, -1, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b64 v[6:7], v10, v[6:7]
+; GFX11-NEXT: v_min_u32_e32 v9, v12, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_min_u32_e32 v11, v13, v14
+; GFX11-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3]
+; GFX11-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-NEXT: v_min_u32_e32 v5, 1, v6
+; GFX11-NEXT: v_sub_nc_u32_e32 v6, 32, v8
+; GFX11-NEXT: v_min_u32_e32 v0, 1, v0
+; GFX11-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX11-NEXT: v_cvt_f32_i32_e32 v4, v4
+; GFX11-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_ldexp_f32 v2, v4, v6
+; GFX11-NEXT: v_cvt_f32_i32_e32 v3, v5
+; GFX11-NEXT: v_sub_nc_u32_e32 v4, 32, v10
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11-NEXT: v_sub_nc_u32_e32 v5, 32, v9
+; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX11-NEXT: v_sub_nc_u32_e32 v6, 32, v11
+; GFX11-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-NEXT: v_ldexp_f32 v3, v3, v4
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v5
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v6
+; GFX11-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-NEXT: v_bfe_u32 v7, v0, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-NEXT: v_add3_u32 v4, v6, v3, 0x7fff
+; GFX11-NEXT: v_add3_u32 v5, v7, v0, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v9, vcc_lo
+; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = sitofp <4 x i64> %x to <4 x bfloat>
ret <4 x bfloat> %op
}
@@ -35544,55 +32596,29 @@ define <2 x bfloat> @v_uitofp_v2i16_to_v2bf16(<2 x i16> %x) {
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_uitofp_v2i16_to_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_uitofp_v2i16_to_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_uitofp_v2i16_to_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = uitofp <2 x i16> %x to <2 x bfloat>
ret <2 x bfloat> %op
}
@@ -35711,38 +32737,35 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) {
; GFX11TRUE16-LABEL: v_uitofp_v3i16_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v3i16_to_v3bf16:
@@ -35919,89 +32942,47 @@ define <4 x bfloat> @v_uitofp_v4i16_to_v4bf16(<4 x i16> %x) {
; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_uitofp_v4i16_to_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v10, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v2, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v3, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_uitofp_v4i16_to_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v1
-; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v0
-; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v3, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v10, v0, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v10, v0, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v10, v11, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_uitofp_v4i16_to_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-NEXT: v_cvt_f32_u32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v10, v0, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-NEXT: v_add3_u32 v10, v10, v0, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v10, v11, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
+; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = uitofp <4 x i16> %x to <4 x bfloat>
ret <4 x bfloat> %op
}
@@ -36154,49 +33135,26 @@ define <2 x bfloat> @v_uitofp_v2i32_to_v2bf16(<2 x i32> %x) {
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_uitofp_v2i32_to_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v1
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_uitofp_v2i32_to_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_uitofp_v2i32_to_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = uitofp <2 x i32> %x to <2 x bfloat>
ret <2 x bfloat> %op
}
@@ -36309,32 +33267,30 @@ define <3 x bfloat> @v_uitofp_v3i32_to_v3bf16(<3 x i32> %x) {
; GFX11TRUE16-LABEL: v_uitofp_v3i32_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v3i32_to_v3bf16:
@@ -36496,76 +33452,39 @@ define <4 x bfloat> @v_uitofp_v4i32_to_v4bf16(<4 x i32> %x) {
; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_uitofp_v4i32_to_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v3, v3
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v10, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v4, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v1
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v2, v3
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_uitofp_v4i32_to_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v3, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11FAKE16-NEXT: v_bfe_u32 v7, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_uitofp_v4i32_to_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX11-NEXT: v_cvt_f32_u32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-NEXT: v_bfe_u32 v7, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v9, v1, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc_lo
+; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = uitofp <4 x i32> %x to <4 x bfloat>
ret <4 x bfloat> %op
}
@@ -36833,89 +33752,46 @@ define <2 x bfloat> @v_uitofp_v2i64_to_v2bf16(<2 x i64> %x) {
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_uitofp_v2i64_to_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v4, v1
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v5, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v4, 32, v4
-; GFX11TRUE16-NEXT: v_min_u32_e32 v5, 32, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v5
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v1
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_uitofp_v2i64_to_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_clz_i32_u32_e32 v4, v1
-; GFX11FAKE16-NEXT: v_clz_i32_u32_e32 v5, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_min_u32_e32 v4, 32, v4
-; GFX11FAKE16-NEXT: v_min_u32_e32 v5, 32, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11FAKE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v2, 32, v4
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v3, 32, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX11FAKE16-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_uitofp_v2i64_to_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_clz_i32_u32_e32 v4, v1
+; GFX11-NEXT: v_clz_i32_u32_e32 v5, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_u32_e32 v4, 32, v4
+; GFX11-NEXT: v_min_u32_e32 v5, 32, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_u32_e32 v0, 1, v0
+; GFX11-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 32, v4
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, 32, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = uitofp <2 x i64> %x to <2 x bfloat>
ret <2 x bfloat> %op
}
@@ -37133,59 +34009,57 @@ define <3 x bfloat> @v_uitofp_v3i64_to_v3bf16(<3 x i64> %x) {
; GFX11TRUE16-LABEL: v_uitofp_v3i64_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v6, v1
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v7, v3
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v8, v5
+; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v6, v5
+; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v7, v1
+; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v8, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_min_u32_e32 v6, 32, v6
; GFX11TRUE16-NEXT: v_min_u32_e32 v7, 32, v7
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_min_u32_e32 v8, 32, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v7, v[2:3]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v8, v[2:3]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v4, 1, v4
; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, v1, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v8, v[4:5]
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v4, 32, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v5, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: v_ldexp_f32 v3, v5, v4
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v4, 32, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v2
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v6
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v3, 32, v7
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v4, v4
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v8
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v5
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v4, v1
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v3i64_to_v3bf16:
@@ -37517,147 +34391,75 @@ define <4 x bfloat> @v_uitofp_v4i64_to_v4bf16(<4 x i64> %x) {
; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_uitofp_v4i64_to_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v8, v5
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v9, v7
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v10, v1
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v11, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v8, 32, v8
-; GFX11TRUE16-NEXT: v_min_u32_e32 v9, 32, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v10, 32, v10
-; GFX11TRUE16-NEXT: v_min_u32_e32 v11, 32, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[6:7], v9, v[6:7]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v10, v[0:1]
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3]
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v8, 32, v8
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v9, 32, v9
-; GFX11TRUE16-NEXT: v_min_u32_e32 v4, 1, v4
-; GFX11TRUE16-NEXT: v_min_u32_e32 v6, 1, v6
-; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, v7, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v10
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v3, v4
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v4, v5
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v11
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_ldexp_f32 v3, v3, v8
-; GFX11TRUE16-NEXT: v_ldexp_f32 v4, v4, v9
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v2, v5
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v10, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v2, v4
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_uitofp_v4i64_to_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_clz_i32_u32_e32 v8, v5
-; GFX11FAKE16-NEXT: v_clz_i32_u32_e32 v10, v1
-; GFX11FAKE16-NEXT: v_clz_i32_u32_e32 v11, v3
-; GFX11FAKE16-NEXT: v_clz_i32_u32_e32 v9, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_min_u32_e32 v8, 32, v8
-; GFX11FAKE16-NEXT: v_min_u32_e32 v10, 32, v10
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_min_u32_e32 v11, 32, v11
-; GFX11FAKE16-NEXT: v_min_u32_e32 v9, 32, v9
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[0:1], v10, v[0:1]
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3]
-; GFX11FAKE16-NEXT: v_lshlrev_b64 v[6:7], v9, v[6:7]
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v8, 32, v8
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v9, 32, v9
-; GFX11FAKE16-NEXT: v_min_u32_e32 v4, 1, v4
-; GFX11FAKE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11FAKE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11FAKE16-NEXT: v_min_u32_e32 v6, 1, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v5, 32, v10
-; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v3, 32, v11
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v2, v4
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_ldexp_f32 v2, v2, v8
-; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v4, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11FAKE16-NEXT: v_bfe_u32 v7, v0, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_ldexp_f32 v4, v4, v9
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_uitofp_v4i64_to_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_clz_i32_u32_e32 v8, v5
+; GFX11-NEXT: v_clz_i32_u32_e32 v10, v1
+; GFX11-NEXT: v_clz_i32_u32_e32 v11, v3
+; GFX11-NEXT: v_clz_i32_u32_e32 v9, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_min_u32_e32 v8, 32, v8
+; GFX11-NEXT: v_min_u32_e32 v10, 32, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_min_u32_e32 v11, 32, v11
+; GFX11-NEXT: v_min_u32_e32 v9, 32, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v10, v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3]
+; GFX11-NEXT: v_lshlrev_b64 v[6:7], v9, v[6:7]
+; GFX11-NEXT: v_sub_nc_u32_e32 v8, 32, v8
+; GFX11-NEXT: v_sub_nc_u32_e32 v9, 32, v9
+; GFX11-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX11-NEXT: v_min_u32_e32 v0, 1, v0
+; GFX11-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX11-NEXT: v_min_u32_e32 v6, 1, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11-NEXT: v_sub_nc_u32_e32 v5, 32, v10
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, 32, v11
+; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v4
+; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX11-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v8
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX11-NEXT: v_cvt_f32_u32_e32 v4, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v3, v2, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-NEXT: v_bfe_u32 v7, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11-NEXT: v_ldexp_f32 v4, v4, v9
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
+; GFX11-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = uitofp <4 x i64> %x to <4 x bfloat>
ret <4 x bfloat> %op
}
@@ -37971,8 +34773,13 @@ define <2 x bfloat> @v_select_v2bf16(i1 %cond, <2 x bfloat> %a, <2 x bfloat> %b)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v3.l, vcc_lo
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v3.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v1.l, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_select_v2bf16:
@@ -38081,8 +34888,13 @@ define <2 x bfloat> @v_vselect_v2bf16(<2 x i1> %cond, <2 x bfloat> %a, <2 x bflo
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, vcc_lo
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v5.l, v4.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, v2.l, s0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_vselect_v2bf16:
@@ -38274,9 +35086,13 @@ define amdgpu_ps i32 @s_select_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, s0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, vcc_lo
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v1.h, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v1.h, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
@@ -38393,9 +35209,13 @@ define amdgpu_ps i32 @s_vselect_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, s0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s2
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v1.h, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, s2
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v1.h, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
@@ -40119,14 +36939,22 @@ define amdgpu_ps <2 x i32> @s_vselect_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat>
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, s2
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, s0
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, s1
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s6
-; GFX11TRUE16-NEXT: v_cndmask_b16 v4.h, v1.h, v2.l, s4
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, s6
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v2.l, s4
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v4.l, v2.h, v3.l, vcc_lo
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v3.h, s5
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v2.h, v3.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.h, s5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX11TRUE16-NEXT: v_perm_b32 v1, v2, v1, 0x5040100
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v4
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s1, v0
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v0, v3, 0x5040100
+; GFX11TRUE16-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
; GFX11FAKE16-LABEL: s_vselect_v4bf16:
@@ -40302,24 +37130,33 @@ define <4 x bfloat> @v_vselect_v4bf16(<4 x i1> %cond, <4 x bfloat> %a, <4 x bflo
; GFX11TRUE16-LABEL: v_vselect_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v6
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v7
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v2
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 1, v2
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v7
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 1, v0
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v1
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v9.l, v8.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 1, v3
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v5
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v0
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v4.l, s0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v3.l, v2.l, s0
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v4.l, s1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v5.l, s2
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v8.l, v3.l, s1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v5.l, s2
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_vselect_v4bf16:
@@ -40587,39 +37424,51 @@ define <8 x bfloat> @v_vselect_v8bf16(<8 x i1> %cond, <8 x bfloat> %a, <8 x bflo
; GFX11TRUE16-LABEL: v_vselect_v8bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v2
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 1, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 1, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 1, v5
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 1, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v7
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 1, v6
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v2
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 1, v3
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 1, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v15
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v13
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 1, v1
-; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v2.l, v0.l, s5
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v4.l, v3.l, s4
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v5.l, s2
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v16.l, v7.l, s0
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v12.l, v8.l, vcc_lo
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v13.l, v9.l, s1
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v14.l, v10.l, s3
-; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v15.l, v11.l, s6
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 1, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 1, v5
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v15
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v0
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v1
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v11
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 1, v4
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 1, v2
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 1, v3
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v8
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v1.l, s2
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v12
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v9
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v13
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v10
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v14
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v15.l, v11.l, s3
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v14.l, v10.l, s4
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v3.l, v2.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v12.l, v8.l, s0
+; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v5.l, v4.l, s1
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v13.l, v9.l, s5
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v7.l, v6.l, s6
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v4, v5, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v1, v2, v6, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v2, v3, v7, 0x5040100
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_perm_b32 v3, v8, v9, 0x5040100
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_vselect_v8bf16:
@@ -41216,72 +38065,96 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 1, v8
; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v20
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v28
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s7, 1, v9
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s8, 1, v8
; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 1, v4
; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 1, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 1, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 1, v9
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 1, v4
; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 1, v11
-; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 1, v10
; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 1, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 1, v12
; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v19
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v27
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v16
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v24
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v2
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 1, v7
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 1, v6
+; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v28.l, v20.l, s8
+; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v38.l, v37.l, s7
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v30
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v29
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v20
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v28
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v19
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v27
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v26
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v25
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v24
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v1
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 1, v2
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v3
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v4
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 1, v5
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 1, v6
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 1, v7
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s7, 1, v8
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s8, 1, v9
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s9, 1, v10
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s10, 1, v13
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s11, 1, v12
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s12, 1, v11
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s13, 1, v14
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s14, 1, v15
-; GFX11TRUE16-NEXT: v_cndmask_b16 v6.h, v34.l, v33.l, s10
-; GFX11TRUE16-NEXT: v_cndmask_b16 v6.l, v30.l, v22.l, s11
-; GFX11TRUE16-NEXT: v_cndmask_b16 v5.h, v36.l, v35.l, s12
-; GFX11TRUE16-NEXT: v_cndmask_b16 v5.l, v29.l, v21.l, s9
-; GFX11TRUE16-NEXT: v_cndmask_b16 v4.h, v38.l, v37.l, s8
-; GFX11TRUE16-NEXT: v_cndmask_b16 v4.l, v28.l, v20.l, s7
-; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v48.l, v39.l, s6
-; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v27.l, v19.l, s5
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v50.l, v49.l, s4
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v52.l, v51.l, s2
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v54.l, v53.l, s0
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v24.l, v16.l, vcc_lo
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v25.l, v17.l, s1
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v26.l, v18.l, s3
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 1, v3
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v5
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 1, v4
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s9, 1, v11
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s10, 1, v12
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s11, 1, v13
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s12, 1, v10
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s13, 1, v15
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s14, 1, v14
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v27.l, v19.l, s6
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v48.l, v39.l, s5
+; GFX11TRUE16-NEXT: v_cndmask_b16 v4.h, v54.l, v53.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v5.l, v24.l, v16.l, s0
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v30.l, v22.l, s10
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v34.l, v33.l, s11
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v29.l, v21.l, s12
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v36.l, v35.l, s9
+; GFX11TRUE16-NEXT: v_cndmask_b16 v5.h, v52.l, v51.l, s1
+; GFX11TRUE16-NEXT: v_cndmask_b16 v6.l, v25.l, v17.l, s2
+; GFX11TRUE16-NEXT: v_cndmask_b16 v6.h, v50.l, v49.l, s3
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
+; GFX11TRUE16-NEXT: v_cndmask_b16 v4.l, v26.l, v18.l, s4
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v5.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v6.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v6.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v15.l, v1.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v17.l, v0.l
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v7, v8, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v1, v5, v9, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v5, v14, v15, 0x5040100
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v31
-; GFX11TRUE16-NEXT: v_cndmask_b16 v7.l, v31.l, v23.l, s13
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v31
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v31.l, v23.l, s14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v2.l, v32.l, s13
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11TRUE16-NEXT: v_perm_b32 v2, v6, v4, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v4, v12, v13, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v6, v16, v17, 0x5040100
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.h
+; GFX11TRUE16-NEXT: v_perm_b32 v3, v10, v11, 0x5040100
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v7.h, v8.l, v32.l, s14
+; GFX11TRUE16-NEXT: v_perm_b32 v7, v8, v7, 0x5040100
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_vselect_v16bf16:
@@ -42777,201 +39650,230 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: s_clause 0x1f
-; GFX11TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32
-; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:64
-; GFX11TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:128
-; GFX11TRUE16-NEXT: scratch_load_b32 v34, off, s32 offset:60
-; GFX11TRUE16-NEXT: scratch_load_b32 v35, off, s32 offset:124
-; GFX11TRUE16-NEXT: scratch_load_b32 v36, off, s32 offset:56
-; GFX11TRUE16-NEXT: scratch_load_b32 v37, off, s32 offset:120
-; GFX11TRUE16-NEXT: scratch_load_b32 v38, off, s32 offset:52
-; GFX11TRUE16-NEXT: scratch_load_b32 v39, off, s32 offset:116
-; GFX11TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:48
-; GFX11TRUE16-NEXT: scratch_load_b32 v49, off, s32 offset:112
-; GFX11TRUE16-NEXT: scratch_load_b32 v50, off, s32 offset:44
-; GFX11TRUE16-NEXT: scratch_load_b32 v51, off, s32 offset:108
-; GFX11TRUE16-NEXT: scratch_load_b32 v52, off, s32 offset:40
-; GFX11TRUE16-NEXT: scratch_load_b32 v53, off, s32 offset:104
-; GFX11TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:36
-; GFX11TRUE16-NEXT: scratch_load_b32 v55, off, s32 offset:100
-; GFX11TRUE16-NEXT: scratch_load_b32 v64, off, s32 offset:32
-; GFX11TRUE16-NEXT: scratch_load_b32 v65, off, s32 offset:96
-; GFX11TRUE16-NEXT: scratch_load_b32 v66, off, s32 offset:28
-; GFX11TRUE16-NEXT: scratch_load_b32 v67, off, s32 offset:92
-; GFX11TRUE16-NEXT: scratch_load_b32 v68, off, s32 offset:24
-; GFX11TRUE16-NEXT: scratch_load_b32 v69, off, s32 offset:88
-; GFX11TRUE16-NEXT: scratch_load_b32 v70, off, s32 offset:20
-; GFX11TRUE16-NEXT: scratch_load_b32 v71, off, s32 offset:84
-; GFX11TRUE16-NEXT: scratch_load_b32 v80, off, s32 offset:16
-; GFX11TRUE16-NEXT: scratch_load_b32 v81, off, s32 offset:80
-; GFX11TRUE16-NEXT: scratch_load_b32 v82, off, s32 offset:12
-; GFX11TRUE16-NEXT: scratch_load_b32 v83, off, s32 offset:76
-; GFX11TRUE16-NEXT: scratch_load_b32 v84, off, s32 offset:8
-; GFX11TRUE16-NEXT: scratch_load_b32 v85, off, s32 offset:72
-; GFX11TRUE16-NEXT: scratch_load_b32 v86, off, s32 offset:4
-; GFX11TRUE16-NEXT: scratch_load_b32 v87, off, s32 offset:68
-; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX11TRUE16-NEXT: scratch_load_u16 v31, off, s32
+; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:128
+; GFX11TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:64
+; GFX11TRUE16-NEXT: scratch_load_b32 v34, off, s32 offset:124
+; GFX11TRUE16-NEXT: scratch_load_b32 v35, off, s32 offset:60
+; GFX11TRUE16-NEXT: scratch_load_b32 v36, off, s32 offset:120
+; GFX11TRUE16-NEXT: scratch_load_b32 v37, off, s32 offset:56
+; GFX11TRUE16-NEXT: scratch_load_b32 v38, off, s32 offset:116
+; GFX11TRUE16-NEXT: scratch_load_b32 v39, off, s32 offset:52
+; GFX11TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:112
+; GFX11TRUE16-NEXT: scratch_load_b32 v49, off, s32 offset:48
+; GFX11TRUE16-NEXT: scratch_load_b32 v50, off, s32 offset:108
+; GFX11TRUE16-NEXT: scratch_load_b32 v51, off, s32 offset:44
+; GFX11TRUE16-NEXT: scratch_load_b32 v52, off, s32 offset:104
+; GFX11TRUE16-NEXT: scratch_load_b32 v53, off, s32 offset:40
+; GFX11TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:100
+; GFX11TRUE16-NEXT: scratch_load_b32 v55, off, s32 offset:36
+; GFX11TRUE16-NEXT: scratch_load_b32 v64, off, s32 offset:96
+; GFX11TRUE16-NEXT: scratch_load_b32 v65, off, s32 offset:32
+; GFX11TRUE16-NEXT: scratch_load_b32 v66, off, s32 offset:92
+; GFX11TRUE16-NEXT: scratch_load_b32 v67, off, s32 offset:28
+; GFX11TRUE16-NEXT: scratch_load_b32 v68, off, s32 offset:88
+; GFX11TRUE16-NEXT: scratch_load_b32 v69, off, s32 offset:24
+; GFX11TRUE16-NEXT: scratch_load_b32 v70, off, s32 offset:84
+; GFX11TRUE16-NEXT: scratch_load_b32 v71, off, s32 offset:20
+; GFX11TRUE16-NEXT: scratch_load_b32 v80, off, s32 offset:80
+; GFX11TRUE16-NEXT: scratch_load_b32 v81, off, s32 offset:16
+; GFX11TRUE16-NEXT: scratch_load_b32 v82, off, s32 offset:76
+; GFX11TRUE16-NEXT: scratch_load_b32 v83, off, s32 offset:12
+; GFX11TRUE16-NEXT: scratch_load_b32 v84, off, s32 offset:72
+; GFX11TRUE16-NEXT: scratch_load_b32 v85, off, s32 offset:8
+; GFX11TRUE16-NEXT: scratch_load_b32 v86, off, s32 offset:68
+; GFX11TRUE16-NEXT: scratch_load_b32 v87, off, s32 offset:4
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 1, v14
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 1, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 1, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 1, v8
; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 1, v22
; GFX11TRUE16-NEXT: v_and_b32_e32 v24, 1, v24
; GFX11TRUE16-NEXT: v_and_b32_e32 v26, 1, v26
; GFX11TRUE16-NEXT: v_and_b32_e32 v28, 1, v28
; GFX11TRUE16-NEXT: v_and_b32_e32 v30, 1, v30
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s15, 1, v16
; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 1, v4
; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 1, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 1, v8
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 1, v9
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 1, v10
; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 1, v11
-; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 1, v10
; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 1, v12
; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 1, v14
; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 1, v17
+; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 1, v16
; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 1, v19
+; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 1, v18
; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 1, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 1, v20
; GFX11TRUE16-NEXT: v_and_b32_e32 v23, 1, v23
; GFX11TRUE16-NEXT: v_and_b32_e32 v25, 1, v25
; GFX11TRUE16-NEXT: v_and_b32_e32 v27, 1, v27
; GFX11TRUE16-NEXT: v_and_b32_e32 v29, 1, v29
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s13, 1, v14
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s17, 1, v18
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s19, 1, v20
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s21, 1, v22
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s23, 1, v24
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s25, 1, v26
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s27, 1, v28
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s28, 1, v30
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v1
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 1, v2
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v3
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v4
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 1, v5
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 1, v6
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 1, v7
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s7, 1, v8
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s8, 1, v9
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s9, 1, v10
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s10, 1, v11
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s11, 1, v12
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s12, 1, v13
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s14, 1, v15
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s16, 1, v17
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s18, 1, v19
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s20, 1, v21
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s22, 1, v23
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s24, 1, v25
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s26, 1, v27
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s29, 1, v29
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s8, 1, v8
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s22, 1, v22
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s24, 1, v24
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s26, 1, v30
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s27, 1, v26
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s29, 1, v28
+; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 1, v3
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v2
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v5
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 1, v4
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 1, v7
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s7, 1, v9
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s9, 1, v11
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s10, 1, v10
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s11, 1, v13
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s12, 1, v12
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s13, 1, v15
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s14, 1, v14
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s15, 1, v17
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s16, 1, v16
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s17, 1, v19
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s18, 1, v18
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s19, 1, v21
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s20, 1, v20
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s21, 1, v23
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s23, 1, v25
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s25, 1, v27
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s28, 1, v29
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 1, v6
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(32)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v16.l, v31.l
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 1, v31
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(31)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v32
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(30)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v33
-; GFX11TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v32.l, s28
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(29)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v34
-; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v32.l, v33.l, s26
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v33
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(28)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v35
-; GFX11TRUE16-NEXT: v_cndmask_b16 v14.l, v35.l, v34.l, s27
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(27)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v36
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v34.l, v35.l, s29
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v35
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v34
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(26)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v37
-; GFX11TRUE16-NEXT: v_cndmask_b16 v13.l, v37.l, v36.l, s25
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v38
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v36.l, v37.l, s27
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v37
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v36
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(24)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v39
-; GFX11TRUE16-NEXT: v_cndmask_b16 v12.l, v39.l, v38.l, s23
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(23)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v48
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v38.l, v39.l, s24
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v39
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v38
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(22)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v49
-; GFX11TRUE16-NEXT: v_cndmask_b16 v11.l, v49.l, v48.l, s21
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(21)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v50
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(20)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v51
-; GFX11TRUE16-NEXT: v_cndmask_b16 v10.l, v51.l, v50.l, s19
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(19)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v52
+; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v48.l, v49.l, s22
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v49
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v48
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(18)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v53
-; GFX11TRUE16-NEXT: v_cndmask_b16 v9.l, v53.l, v52.l, s17
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(17)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v54
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(16)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v55
-; GFX11TRUE16-NEXT: v_cndmask_b16 v8.l, v55.l, v54.l, s15
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(15)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v64
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v53
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v52
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(14)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v65
-; GFX11TRUE16-NEXT: v_cndmask_b16 v7.l, v65.l, v64.l, s13
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v66
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v67
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v65
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v64
+; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v50.l, v51.l, s20
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v68
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v68
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(10)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v69
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v69
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(9)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v70
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v70
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v71
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v71
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v80
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v80
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v81
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v81
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v82
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v82
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v83
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v83
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v84
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v84
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v85
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v85
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v86
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v86
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v87
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v87.l, v86.l, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
-; GFX11TRUE16-NEXT: v_cndmask_b16 v6.l, v67.l, v66.l, s11
-; GFX11TRUE16-NEXT: v_cndmask_b16 v5.l, v69.l, v68.l, s9
-; GFX11TRUE16-NEXT: v_cndmask_b16 v4.l, v71.l, v70.l, s7
-; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v81.l, v80.l, s5
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v83.l, v82.l, s3
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v85.l, v84.l, s1
-; GFX11TRUE16-NEXT: v_cndmask_b16 v14.h, v20.l, v19.l, s29
-; GFX11TRUE16-NEXT: v_cndmask_b16 v13.h, v22.l, v21.l, s26
-; GFX11TRUE16-NEXT: v_cndmask_b16 v12.h, v24.l, v23.l, s24
-; GFX11TRUE16-NEXT: v_cndmask_b16 v11.h, v26.l, v25.l, s22
-; GFX11TRUE16-NEXT: v_cndmask_b16 v10.h, v28.l, v27.l, s20
-; GFX11TRUE16-NEXT: v_cndmask_b16 v9.h, v30.l, v29.l, s18
-; GFX11TRUE16-NEXT: v_cndmask_b16 v8.h, v32.l, v31.l, s16
-; GFX11TRUE16-NEXT: v_cndmask_b16 v7.h, v34.l, v33.l, s14
-; GFX11TRUE16-NEXT: v_cndmask_b16 v6.h, v36.l, v35.l, s12
-; GFX11TRUE16-NEXT: v_cndmask_b16 v5.h, v38.l, v37.l, s10
-; GFX11TRUE16-NEXT: v_cndmask_b16 v4.h, v48.l, v39.l, s8
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v64.l, v55.l, s0
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v54.l, v53.l, s2
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v52.l, v51.l, s4
-; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v50.l, v49.l, s6
-; GFX11TRUE16-NEXT: v_cndmask_b16 v15.h, v18.l, v17.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v7.h, v86.l, v87.l, s0
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v87
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v8
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v51
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v50
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v52.l, v53.l, s18
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v54.l, v55.l, s16
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v55
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v54
+; GFX11TRUE16-NEXT: v_cndmask_b16 v4.l, v64.l, v65.l, s14
+; GFX11TRUE16-NEXT: v_cndmask_b16 v4.h, v66.l, v67.l, s12
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v67
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v66
+; GFX11TRUE16-NEXT: v_cndmask_b16 v5.h, v70.l, v71.l, s8
+; GFX11TRUE16-NEXT: v_cndmask_b16 v6.h, v82.l, v83.l, s4
+; GFX11TRUE16-NEXT: v_cndmask_b16 v8.l, v10.l, v9.l, s28
+; GFX11TRUE16-NEXT: v_cndmask_b16 v8.h, v12.l, v11.l, s25
+; GFX11TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v13.l, s23
+; GFX11TRUE16-NEXT: v_cndmask_b16 v9.h, v18.l, v15.l, s21
+; GFX11TRUE16-NEXT: v_cndmask_b16 v10.h, v22.l, v21.l, s17
+; GFX11TRUE16-NEXT: v_cndmask_b16 v11.h, v26.l, v25.l, s13
+; GFX11TRUE16-NEXT: v_cndmask_b16 v12.h, v30.l, v29.l, s9
+; GFX11TRUE16-NEXT: v_cndmask_b16 v13.l, v32.l, v31.l, s7
+; GFX11TRUE16-NEXT: v_cndmask_b16 v13.h, v34.l, v33.l, s5
+; GFX11TRUE16-NEXT: v_cndmask_b16 v14.l, v36.l, v35.l, s3
+; GFX11TRUE16-NEXT: v_cndmask_b16 v14.h, v38.l, v37.l, s1
+; GFX11TRUE16-NEXT: v_cndmask_b16 v15.l, v48.l, v39.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v15.h, v17.l, v16.l, s0
+; GFX11TRUE16-NEXT: v_cndmask_b16 v5.l, v68.l, v69.l, s10
+; GFX11TRUE16-NEXT: v_cndmask_b16 v6.l, v80.l, v81.l, s6
+; GFX11TRUE16-NEXT: v_cndmask_b16 v7.l, v84.l, v85.l, s2
+; GFX11TRUE16-NEXT: v_cndmask_b16 v10.l, v20.l, v19.l, s19
+; GFX11TRUE16-NEXT: v_cndmask_b16 v11.l, v24.l, v23.l, s15
+; GFX11TRUE16-NEXT: v_cndmask_b16 v12.l, v28.l, v27.l, s11
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v18.l, v7.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v19.l, v6.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v20.l, v5.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v22.l, v4.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v23.l, v3.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v24.l, v3.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v25.l, v2.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v26.l, v2.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v27.l, v1.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v28.l, v1.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v29.l, v0.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v30.l, v0.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v15.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v14.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v14.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v13.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v13.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v12.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v31.l, v9.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v32.l, v8.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v33.l, v8.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v15.l, v15.h
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v0, v18, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v1, v1, v7, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v2, v2, v19, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v3, v3, v6, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v4, v4, v20, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v5, v13, v5, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v6, v12, v21, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v7, v14, v22, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v8, v11, v23, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v9, v16, v24, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v10, v10, v25, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v11, v17, v26, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v12, v31, v27, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v13, v32, v28, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v14, v33, v29, 0x5040100
+; GFX11TRUE16-NEXT: v_perm_b32 v15, v15, v30, 0x5040100
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_vselect_v32bf16:
@@ -43397,60 +40299,32 @@ define <2 x bfloat> @v_fma_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat>
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fma_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v2, v0, v1 :: v_dual_fmac_f32 v3, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v0, v4, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v4, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v1
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fma_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v2, v0, v1 :: v_dual_fmac_f32 v3, v5, v4
-; GFX11FAKE16-NEXT: v_bfe_u32 v1, v2, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_bfe_u32 v0, v3, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fma_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_fmac_f32 v2, v0, v1 :: v_dual_fmac_f32 v3, v5, v4
+; GFX11-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v0, v3, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <2 x bfloat> @llvm.fma.v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c)
ret <2 x bfloat> %op
}
@@ -43626,41 +40500,40 @@ define <3 x bfloat> @v_fma_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfloat>
; GFX11TRUE16-LABEL: v_fma_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v4, v0, v2 :: v_dual_fmac_f32 v5, v1, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v6, v8, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v7, v6, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v0, 0x400000, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v4, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v1, v3
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v6, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v7, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v2, v1, 0x7060302
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fma_v3bf16:
@@ -43918,105 +40791,53 @@ define <4 x bfloat> @v_fma_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat>
; GFX10-NEXT: v_perm_b32 v1, v4, v1, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fma_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v1, v3
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v7, 16, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v6, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v7, v9, v8
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v4, v0, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v0, v8, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v3, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v2
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fma_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v5, v1, v3
-; GFX11FAKE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v7, 16, v4
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v6
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v4, v0, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v0, v10, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v5, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc_lo
-; GFX11FAKE16-NEXT: v_fmac_f32_e32 v7, v9, v8
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v4, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v0, v2, v5, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v7, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v6, v8, v4, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v3, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v7
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v4, v0, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v3, v2, 0x7060302
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fma_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_fmac_f32_e32 v5, v1, v3
+; GFX11-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v7, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v1, 0x400000, v6
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_fmac_f32_e32 v4, v0, v2
+; GFX11-NEXT: v_add3_u32 v0, v10, v6, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc_lo
+; GFX11-NEXT: v_fmac_f32_e32 v7, v9, v8
+; GFX11-NEXT: v_bfe_u32 v8, v4, 16, 1
+; GFX11-NEXT: v_add3_u32 v0, v2, v5, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v3, v7, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_add3_u32 v6, v8, v4, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-NEXT: v_add3_u32 v2, v3, v7, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v3, 0x400000, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v0, v9, vcc_lo
+; GFX11-NEXT: v_perm_b32 v0, v3, v2, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v1, v4, v1, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <4 x bfloat> @llvm.fma.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat> %c)
ret <4 x bfloat> %op
}
@@ -44328,95 +41149,50 @@ define <2 x bfloat> @v_fmuladd_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfl
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fmuladd_v2bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v3, v4, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v0, v5, v4 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fmuladd_v2bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v3, v4, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v1, v3, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
-; GFX11FAKE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v0, v4, v6 :: v_dual_add_f32 v1, v1, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fmuladd_v2bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mul_f32 v3, v4, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v1, v3, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v6 :: v_dual_add_f32 v1, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <2 x bfloat> @llvm.fmuladd.v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c)
ret <2 x bfloat> %op
}
@@ -44670,68 +41446,65 @@ define <3 x bfloat> @v_fmuladd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfl
; GFX11TRUE16-LABEL: v_fmuladd_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v6, v7, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v7, v6, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v1, v6, v9 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_dual_add_f32 v2, v2, v3 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v3, v7, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v3
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmuladd_v3bf16:
@@ -45117,163 +41890,82 @@ define <4 x bfloat> @v_fmuladd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfl
; GFX10-NEXT: v_perm_b32 v1, v1, v3, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: v_fmuladd_v4bf16:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v6, v7, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v7
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v1, v1, v3 :: v_dual_and_b32 v8, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v7, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_dual_add_f32 v1, v1, v5 :: v_dual_mul_f32 v2, v10, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v6, v10 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_add_f32_e32 v3, v3, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v7, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v2, v2, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v3
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v2, v0
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_fmuladd_v4bf16:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v6, v7, v6 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX11FAKE16-NEXT: v_dual_mul_f32 v1, v1, v3 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11FAKE16-NEXT: v_mul_f32_e32 v7, v9, v7
-; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add3_u32 v10, v10, v6, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
-; GFX11FAKE16-NEXT: v_bfe_u32 v9, v7, 16, 1
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v3, v10, v3 :: v_dual_mul_f32 v0, v0, v2
-; GFX11FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
-; GFX11FAKE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v11, v0, 16, 1
-; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_add3_u32 v11, v11, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v1, v2, v6 :: v_dual_lshlrev_b32 v6, 16, v4
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_dual_cndmask_b32 v2, v9, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_dual_add_f32 v1, v1, v5 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v12, vcc_lo
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11FAKE16-NEXT: v_add_f32_e32 v2, v2, v6
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11FAKE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11FAKE16-NEXT: v_add_f32_e32 v3, v3, v8
-; GFX11FAKE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v7, v3, 0x7fff
-; GFX11FAKE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
-; GFX11FAKE16-NEXT: v_add3_u32 v4, v6, v1, 0x7fff
-; GFX11FAKE16-NEXT: v_add3_u32 v5, v7, v2, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11FAKE16-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
-; GFX11FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
-; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
-; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v3, 0x7060302
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_fmuladd_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mul_f32 v6, v7, v6 :: v_dual_and_b32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX11-NEXT: v_dual_mul_f32 v1, v1, v3 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-NEXT: v_mul_f32_e32 v7, v9, v7
+; GFX11-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add3_u32 v10, v10, v6, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-NEXT: v_dual_cndmask_b32 v3, v10, v3 :: v_dual_mul_f32 v0, v0, v2
+; GFX11-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: v_or_b32_e32 v10, 0x400000, v7
+; GFX11-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v11, v0, 16, 1
+; GFX11-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v12, 0x400000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add3_u32 v11, v11, v0, 0x7fff
+; GFX11-NEXT: v_dual_cndmask_b32 v1, v2, v6 :: v_dual_lshlrev_b32 v6, 16, v4
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v9, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_dual_add_f32 v1, v1, v5 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v11, v12, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v3, v3, v8
+; GFX11-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-NEXT: v_add3_u32 v4, v7, v3, 0x7fff
+; GFX11-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
+; GFX11-NEXT: v_add3_u32 v4, v6, v1, 0x7fff
+; GFX11-NEXT: v_add3_u32 v5, v7, v2, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v6, 0x400000, v2
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
+; GFX11-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
+; GFX11-NEXT: v_perm_b32 v1, v1, v3, 0x7060302
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <4 x bfloat> @llvm.fmuladd.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat> %c)
ret <4 x bfloat> %op
}
diff --git a/llvm/test/CodeGen/AMDGPU/bswap.ll b/llvm/test/CodeGen/AMDGPU/bswap.ll
index a95a1aba0c914..b98ca1ff55f59 100644
--- a/llvm/test/CodeGen/AMDGPU/bswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/bswap.ll
@@ -737,15 +737,25 @@ define i64 @v_bswap_i48(i64 %src) {
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_bswap_i48:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_perm_b32 v2, 0, v0, 0x10203
-; GFX11-NEXT: v_perm_b32 v0, 0, v1, 0x10203
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-REAL16-LABEL: v_bswap_i48:
+; GFX11-REAL16: ; %bb.0:
+; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REAL16-NEXT: v_perm_b32 v2, 0, v0, 0x10203
+; GFX11-REAL16-NEXT: v_perm_b32 v1, 0, v1, 0x10203
+; GFX11-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REAL16-NEXT: v_lshrrev_b64 v[0:1], 16, v[1:2]
+; GFX11-REAL16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-REAL16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_bswap_i48:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, 0, v0, 0x10203
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, 0, v1, 0x10203
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v2, v0, 16
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%trunc = trunc i64 %src to i48
%bswap = call i48 @llvm.bswap.i48(i48 %trunc)
%zext = zext i48 %bswap to i64
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
index 857a1359b00d9..ce452957b0198 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
@@ -416,11 +416,11 @@ v_alignbit_b32 v5, s1, v255, s3
v_alignbit_b32 v5, s105, s105, s105
// GFX11: v_alignbit_b32 v5, s105, s105, s105 ; encoding: [0x05,0x00,0x16,0xd6,0x69,0xd2,0xa4,0x01]
-v_alignbit_b32 v5, vcc_lo, ttmp15, v3
-// GFX11: v_alignbit_b32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
+v_alignbit_b32 v5, vcc_lo, ttmp15, v3.l
+// GFX11: v_alignbit_b32 v5, vcc_lo, ttmp15, v3.l ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
-v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255
-// GFX11: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.l
+// GFX11: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.l ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
v_alignbit_b32 v5, ttmp15, src_scc, ttmp15
// GFX11: v_alignbit_b32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x16,0xd6,0x7b,0xfa,0xed,0x01]
@@ -449,6 +449,9 @@ v_alignbit_b32 v5, src_scc, vcc_lo, -1
v_alignbit_b32 v255, 0xaf123456, vcc_hi, null
// GFX11: v_alignbit_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x16,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.h
+// GFX11: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.h op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
v_alignbyte_b32 v5, v1, v2, s3
// GFX11: v_alignbyte_b32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x17,0xd6,0x01,0x05,0x0e,0x00]
@@ -543,13 +546,13 @@ v_and_b16 v255.l, 0xfe0b, vcc_hi
// GFX11: v_and_b16 v255.l, 0xfe0b, vcc_hi ; encoding: [0xff,0x00,0x62,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
v_and_b16 v5.l, v1.h, v2.l
-// GFX11: [0x05,0x08,0x62,0xd7,0x01,0x05,0x02,0x00]
+// GFX11: v_and_b16 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x62,0xd7,0x01,0x05,0x02,0x00]
v_and_b16 v5.l, v255.l, v255.h
-// GFX11: [0x05,0x10,0x62,0xd7,0xff,0xff,0x03,0x00]
+// GFX11: v_and_b16 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x62,0xd7,0xff,0xff,0x03,0x00]
v_and_b16 v255.h, 0xfe0b, vcc_hi
-// GFX11: [0xff,0x40,0x62,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+// GFX11: v_and_b16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1] ; encoding: [0xff,0x40,0x62,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
v_and_or_b32 v5, v1, v2, s3
// GFX11: v_and_or_b32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x57,0xd6,0x01,0x05,0x0e,0x00]
@@ -5577,13 +5580,13 @@ v_or_b16 v255.l, 0xfe0b, vcc_hi
// GFX11: v_or_b16 v255.l, 0xfe0b, vcc_hi ; encoding: [0xff,0x00,0x63,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
v_or_b16 v5.l, v1.h, v2.l
-// GFX11: [0x05,0x08,0x63,0xd7,0x01,0x05,0x02,0x00]
+// GFX11: v_or_b16 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x63,0xd7,0x01,0x05,0x02,0x00]
v_or_b16 v5.l, v255.l, v255.h
-// GFX11: [0x05,0x10,0x63,0xd7,0xff,0xff,0x03,0x00]
+// GFX11: v_or_b16 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x63,0xd7,0xff,0xff,0x03,0x00]
v_or_b16 v255.h, 0xfe0b, vcc_hi
-// GFX11: [0xff,0x40,0x63,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+// GFX11: v_or_b16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1] ; encoding: [0xff,0x40,0x63,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
v_pack_b32_f16 v5, v1.l, v2.l
// GFX11: v_pack_b32_f16 v5, v1.l, v2.l ; encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x00]
@@ -6632,10 +6635,10 @@ v_xor_b16 v255.l, 0xfe0b, vcc_hi
// GFX11: v_xor_b16 v255.l, 0xfe0b, vcc_hi ; encoding: [0xff,0x00,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
v_xor_b16 v5.l, v1.h, v2.l
-// GFX11: [0x05,0x08,0x64,0xd7,0x01,0x05,0x02,0x00]
+// GFX11: v_xor_b16 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x64,0xd7,0x01,0x05,0x02,0x00]
v_xor_b16 v5.l, v255.l, v255.h
-// GFX11: [0x05,0x10,0x64,0xd7,0xff,0xff,0x03,0x00]
+// GFX11: v_xor_b16 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x64,0xd7,0xff,0xff,0x03,0x00]
v_xor_b16 v255.h, 0xfe0b, vcc_hi
-// GFX11: [0xff,0x40,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
+// GFX11: v_xor_b16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1] ; encoding: [0xff,0x40,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
index 1864996b26028..6b514a02d843f 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
@@ -321,20 +321,23 @@ v_add_nc_u16_e64_dpp v5.l, v1.l, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bou
v_add_nc_u16_e64_dpp v255.h, v255.l, v255.l clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_add_nc_u16_e64_dpp v255.h, v255.l, v255.l op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0xc0,0x03,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
-v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
-// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[3,2,1,0]
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
-v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3]
-// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[0,1,2,3]
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
-v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_mirror
-// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_mirror
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
-v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_half_mirror
-// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_half_mirror
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
-v_alignbit_b32_e64_dpp v5, v1, v2, v255 row_shl:1
-// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v255 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+v_alignbit_b32_e64_dpp v5, v1, v2, v255.l row_shl:1
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v255.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, v255.h row_shl:1
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
v_alignbit_b32_e64_dpp v5, v1, v2, s105 row_shl:15
// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, s105 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
@@ -345,7 +348,7 @@ v_alignbit_b32_e64_dpp v5, v1, v2, vcc_hi row_shr:1
v_alignbit_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:15
// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
-v_alignbit_b32_e64_dpp v5, v1, v2, ttmp15 row_ror:1
+v_alignbit_b32_e64_dpp v5, v1, v2, ttmp15 row_ror:1 row_mask:0xf bank_mask:0xf
// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, ttmp15 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
v_alignbit_b32_e64_dpp v5, v1, v2, exec_hi row_ror:15
@@ -363,6 +366,24 @@ v_alignbit_b32_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bou
v_alignbit_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_alignbit_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x00,0x16,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+v_alignbit_b32_e64_dpp v5, v1, v2, v255.l row_mirror
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v255.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, s3 row_half_mirror
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, s3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, s105 row_shl:1
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, ttmp15 row_shl:15
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, ttmp15 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xee,0x01,0x01,0x0f,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, m0 row_ror:1
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, m0 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xf6,0x01,0x01,0x21,0x01,0xff]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, v255.h row_mirror
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+
v_alignbyte_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[3,2,1,0]
// GFX11: v_alignbyte_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
@@ -466,16 +487,16 @@ v_and_b16_e64_dpp v255.l, v255.l, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0
// GFX11: v_and_b16_e64_dpp v255.l, v255.l, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x00,0x62,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
v_and_b16_e64_dpp v5.h, v1.h, v2.h row_share:0 row_mask:0xf bank_mask:0xf
-// GFX11: [0x05,0x58,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// GFX11: v_and_b16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
v_and_b16_e64_dpp v5.l, v1.h, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX11: [0x05,0x08,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// GFX11: v_and_b16_e64_dpp v5.l, v1.h, v2.l op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x08,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
v_and_b16_e64_dpp v5.l, v1.l, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX11: [0x05,0x10,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// GFX11: v_and_b16_e64_dpp v5.l, v1.l, v2.h op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x10,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
v_and_b16_e64_dpp v255.h, v255.l, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX11: [0xff,0x40,0x62,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+// GFX11: v_and_b16_e64_dpp v255.h, v255.l, v255.l op_sel:[0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x40,0x62,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
v_and_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
// GFX11: v_and_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
@@ -4272,16 +4293,16 @@ v_or_b16_e64_dpp v255.l, v255.l, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0
// GFX11: v_or_b16_e64_dpp v255.l, v255.l, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x00,0x63,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
v_or_b16_e64_dpp v5.h, v1.h, v2.h row_share:0 row_mask:0xf bank_mask:0xf
-// GFX11: [0x05,0x58,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// GFX11: v_or_b16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
v_or_b16_e64_dpp v5.l, v1.h, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX11: [0x05,0x08,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// GFX11: v_or_b16_e64_dpp v5.l, v1.h, v2.l op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x08,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
v_or_b16_e64_dpp v5.l, v1.l, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX11: [0x05,0x10,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// GFX11: v_or_b16_e64_dpp v5.l, v1.l, v2.h op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x10,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
v_or_b16_e64_dpp v255.h, v255.l, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX11: [0xff,0x40,0x63,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+// GFX11: v_or_b16_e64_dpp v255.h, v255.l, v255.l op_sel:[0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x40,0x63,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
v_pack_b32_f16_e64_dpp v5, v1.l, v2.l quad_perm:[3,2,1,0]
// GFX11: v_pack_b32_f16_e64_dpp v5, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
@@ -5008,16 +5029,16 @@ v_xor_b16_e64_dpp v255.l, v255.l, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0
// GFX11: v_xor_b16_e64_dpp v255.l, v255.l, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x00,0x64,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
v_xor_b16_e64_dpp v5.h, v1.h, v2.h row_share:0 row_mask:0xf bank_mask:0xf
-// GFX11: [0x05,0x58,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+// GFX11: v_xor_b16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
v_xor_b16_e64_dpp v5.l, v1.h, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX11: [0x05,0x08,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+// GFX11: v_xor_b16_e64_dpp v5.l, v1.h, v2.l op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x08,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
v_xor_b16_e64_dpp v5.l, v1.l, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX11: [0x05,0x10,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+// GFX11: v_xor_b16_e64_dpp v5.l, v1.l, v2.h op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x10,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
v_xor_b16_e64_dpp v255.h, v255.l, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX11: [0xff,0x40,0x64,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
+// GFX11: v_xor_b16_e64_dpp v255.h, v255.l, v255.l op_sel:[0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x40,0x64,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1.h, |v2.l| op_sel:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3
// GFX11: v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1.h, |v2.l| op_sel:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x0a,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
index 300e5ef22f5ae..80ee725db319f 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
@@ -154,11 +154,11 @@ v_add_nc_u16_e64_dpp v5.l, v1.l, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
v_add_nc_u16_e64_dpp v255.h, v255.l, v255.l clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_add_nc_u16_e64_dpp v255.h, v255.l, v255.l op_sel:[0,0,1] clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0xc0,0x03,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
-v_alignbit_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+v_alignbit_b32_e64_dpp v5, v1, v2, v3.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
-v_alignbit_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+v_alignbit_b32_e64_dpp v5, v1, v2, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
v_alignbit_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
@@ -187,6 +187,15 @@ v_alignbit_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
v_alignbit_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_alignbit_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x00,0x16,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+v_alignbit_b32_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, m0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xf6,0x01,0x01,0x77,0x39,0x05]
+
+v_alignbit_b32_e64_dpp v5, v1, v2, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
v_alignbyte_b32_e64_dpp v5, v1, v2, v3.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_alignbyte_b32_e64_dpp v5, v1, v2, v3.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
@@ -239,16 +248,16 @@ v_and_b16_e64_dpp v255.l, v255.l, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_and_b16_e64_dpp v255.l, v255.l, v255.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x00,0x62,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
v_and_b16_e64_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: [0x05,0x58,0x62,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// GFX11: v_and_b16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x62,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
v_and_b16_e64_dpp v5.l, v1.h, v2.l dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: [0x05,0x08,0x62,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// GFX11: v_and_b16_e64_dpp v5.l, v1.h, v2.l op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x62,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
v_and_b16_e64_dpp v5.l, v1.l, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX11: [0x05,0x10,0x62,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// GFX11: v_and_b16_e64_dpp v5.l, v1.l, v2.h op_sel:[0,1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x10,0x62,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
v_and_b16_e64_dpp v255.h, v255.l, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX11: [0xff,0x40,0x62,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+// GFX11: v_and_b16_e64_dpp v255.h, v255.l, v255.l op_sel:[0,0,1] dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x40,0x62,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
v_and_or_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_and_or_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x57,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
@@ -2855,16 +2864,16 @@ v_or_b16_e64_dpp v255.l, v255.l, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_or_b16_e64_dpp v255.l, v255.l, v255.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x00,0x63,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
v_or_b16_e64_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: [0x05,0x58,0x63,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// GFX11: v_or_b16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x63,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
v_or_b16_e64_dpp v5.l, v1.h, v2.l dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: [0x05,0x08,0x63,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// GFX11: v_or_b16_e64_dpp v5.l, v1.h, v2.l op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x63,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
v_or_b16_e64_dpp v5.l, v1.l, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX11: [0x05,0x10,0x63,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// GFX11: v_or_b16_e64_dpp v5.l, v1.l, v2.h op_sel:[0,1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x10,0x63,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
v_or_b16_e64_dpp v255.h, v255.l, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX11: [0xff,0x40,0x63,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+// GFX11: v_or_b16_e64_dpp v255.h, v255.l, v255.l op_sel:[0,0,1] dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x40,0x63,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
v_pack_b32_f16_e64_dpp v5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_pack_b32_f16_e64_dpp v5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
@@ -3263,16 +3272,16 @@ v_xor_b16_e64_dpp v255.l, v255.l, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_xor_b16_e64_dpp v255.l, v255.l, v255.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x00,0x64,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
v_xor_b16_e64_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: [0x05,0x58,0x64,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// GFX11: v_xor_b16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x64,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
v_xor_b16_e64_dpp v5.l, v1.h, v2.l dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: [0x05,0x08,0x64,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// GFX11: v_xor_b16_e64_dpp v5.l, v1.h, v2.l op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0x64,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
v_xor_b16_e64_dpp v5.l, v1.l, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX11: [0x05,0x10,0x64,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+// GFX11: v_xor_b16_e64_dpp v5.l, v1.l, v2.h op_sel:[0,1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x10,0x64,0xd7,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
v_xor_b16_e64_dpp v255.h, v255.l, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX11: [0xff,0x40,0x64,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
+// GFX11: v_xor_b16_e64_dpp v255.h, v255.l, v255.l op_sel:[0,0,1] dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x40,0x64,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1.h, |v2.l| op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1.h, |v2.l| op_sel:[1,0,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0a,0x12,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
index 72d201e060df7..afd4af92b4f27 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
@@ -407,6 +407,9 @@ v_alignbit_b32 v5, src_scc, vcc_lo, -1
v_alignbit_b32 v255, 0xaf123456, vcc_hi, null
// GFX12: v_alignbit_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x16,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.h
+// GFX12: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.h op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
v_alignbyte_b32 v5, v1, v2, s3
// GFX12: v_alignbyte_b32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x17,0xd6,0x01,0x05,0x0e,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
index 08be9225890c2..cfd01ee02aa7e 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
@@ -437,6 +437,9 @@ v_alignbit_b32_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bou
v_alignbit_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX12: v_alignbit_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x00,0x16,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
+v_alignbit_b32_e64_dpp v5, v1, v2, v255.h row_mirror
+// GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+
v_alignbyte_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
// GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
index 0523b0fe8c9a4..b6d395c8ede89 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
@@ -249,6 +249,9 @@ v_alignbit_b32_e64_dpp v5, v1, v2, -1 dpp8:[7,6,5,4,3,2,1,0] fi:1
v_alignbit_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX12: v_alignbit_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x00,0x16,0xd6,0xe9,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+v_alignbit_b32_e64_dpp v5, v1, v2, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
v_alignbyte_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
// GFX12: v_alignbyte_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
index b74128b21f563..1b29ddcb20a91 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
@@ -463,10 +463,16 @@
# GFX11: v_alignbit_b32 v5, s105, s105, s105 ; encoding: [0x05,0x00,0x16,0xd6,0x69,0xd2,0xa4,0x01]
0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04
-# GFX11: v_alignbit_b32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
+# W32-REAL16: v_alignbit_b32 v5, vcc_lo, ttmp15, v3.l ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
+# W32-FAKE16: v_alignbit_b32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
+# W64-REAL16: v_alignbit_b32 v5, vcc_lo, ttmp15, v3.l ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
+# W64-FAKE16: v_alignbit_b32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
-# GFX11: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W32-REAL16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.l ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W32-FAKE16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W64-REAL16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.l ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W64-FAKE16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
0x05,0x00,0x16,0xd6,0x7b,0xfa,0xed,0x01
# GFX11: v_alignbit_b32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x16,0xd6,0x7b,0xfa,0xed,0x01]
@@ -495,6 +501,12 @@
0xff,0x00,0x16,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
# GFX11: v_alignbit_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x16,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+# W32-REAL16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.h op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W32-FAKE16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W64-REAL16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.h op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W64-FAKE16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
0x05,0x00,0x17,0xd6,0x01,0x05,0x0e,0x00
# GFX11: v_alignbyte_b32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x17,0xd6,0x01,0x05,0x0e,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
index 8e7122b902326..0f47d33761475 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
@@ -186,19 +186,34 @@
# GFX11: v_add_nc_i32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x26,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
-# GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
-# GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
-# GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff
-# GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff
-# GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v255 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
0x05,0x00,0x16,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff
# GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, s105 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
@@ -227,6 +242,12 @@
0xff,0x00,0x16,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
# GFX11: v_alignbit_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x16,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 op_sel:[0,0,1,0] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 op_sel:[0,0,1,0] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+
0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
# W32-REAL16: v_alignbyte_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
# W32-FAKE16: v_alignbyte_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
index f67eb32385407..67bafd71d01e5 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
@@ -102,10 +102,16 @@
# GFX11: v_add_nc_i32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x26,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
-# GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
-# GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
0x05,0x00,0x16,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
# GFX11: v_alignbit_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
@@ -134,6 +140,12 @@
0xff,0x00,0x16,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
# GFX11: v_alignbit_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x16,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
0x05,0x00,0x17,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
# W32-REAL16: v_alignbyte_b32_e64_dpp v5, v1, v2, v3.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
# W32-FAKE16: v_alignbyte_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
index 3d5e78c86bc22..e7d92af7511f5 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
@@ -427,10 +427,16 @@
# GFX12: v_alignbit_b32 v5, s105, s105, s105 ; encoding: [0x05,0x00,0x16,0xd6,0x69,0xd2,0xa4,0x01]
0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04
-# GFX12: v_alignbit_b32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
+# W32-REAL16: v_alignbit_b32 v5, vcc_lo, ttmp15, v3.l ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
+# W32-FAKE16: v_alignbit_b32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
+# W64-REAL16: v_alignbit_b32 v5, vcc_lo, ttmp15, v3.l ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
+# W64-FAKE16: v_alignbit_b32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
-# GFX12: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W32-REAL16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.l ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W32-FAKE16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W64-REAL16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.l ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W64-FAKE16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
0x05,0x00,0x16,0xd6,0x7b,0xfa,0xed,0x01
# GFX12: v_alignbit_b32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x16,0xd6,0x7b,0xfa,0xed,0x01]
@@ -459,6 +465,12 @@
0xff,0x00,0x16,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf
# GFX12: v_alignbit_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x16,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
+0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf
+# W32-REAL16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.h op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W32-FAKE16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W64-REAL16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.h op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+# W64-FAKE16: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
+
0x05,0x00,0x17,0xd6,0x01,0x05,0x0e,0x00
# GFX12: v_alignbyte_b32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x17,0xd6,0x01,0x05,0x0e,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
index c63c09b6b24c5..a84e0e1734ff5 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
@@ -195,22 +195,40 @@
# GFX12: v_add_nc_i32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x80,0x26,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
-# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
0x05,0x00,0x16,0xd6,0xfa,0x06,0x0c,0x04,0x01,0x1b,0x00,0xff
-# GFX12: v_alignbit_b32_e64_dpp v5, v1, s3, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x06,0x0c,0x04,0x01,0x1b,0x00,0xff]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, s3, v3.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x06,0x0c,0x04,0x01,0x1b,0x00,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, s3, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x06,0x0c,0x04,0x01,0x1b,0x00,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, s3, v3.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x06,0x0c,0x04,0x01,0x1b,0x00,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, s3, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x06,0x0c,0x04,0x01,0x1b,0x00,0xff]
0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff
-# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff
-# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff
-# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff
-# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v255 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
0x05,0x00,0x16,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff
# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, s105 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
@@ -239,6 +257,12 @@
0xff,0x00,0x16,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30
# GFX12: v_alignbit_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x16,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
+0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 op_sel:[0,0,1,0] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 op_sel:[0,0,1,0] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x40,0x01,0xff]
+
0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
# W32-REAL16: v_alignbyte_b32_e64_dpp v5, v1, v2, v3.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
# W32-FAKE16: v_alignbyte_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
index 4182cd93f813c..e4bef0a17385c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
@@ -111,13 +111,22 @@
# GFX12: v_add_nc_i32_e64_dpp v255, v255, v255 clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x80,0x26,0xd7,0xea,0xfe,0x03,0x00,0xff,0x00,0x00,0x00]
0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
-# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v3.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
0x05,0x00,0x16,0xd6,0xe9,0x06,0x0c,0x04,0x01,0x77,0x39,0x05
-# GFX12: v_alignbit_b32_e64_dpp v5, v1, s3, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x06,0x0c,0x04,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, s3, v3.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x06,0x0c,0x04,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, s3, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x06,0x0c,0x04,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, s3, v3.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x06,0x0c,0x04,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, s3, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x06,0x0c,0x04,0x01,0x77,0x39,0x05]
0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
-# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
0x05,0x00,0x16,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05
# GFX12: v_alignbit_b32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x16,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05]
@@ -146,6 +155,12 @@
0xff,0x00,0x16,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00
# GFX12: v_alignbit_b32_e64_dpp v255, v255, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x16,0xd6,0xea,0xfe,0xf7,0x03,0xff,0x00,0x00,0x00]
+0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05
+# W32-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_alignbit_b32_e64_dpp v5, v1, v2, v255.h op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_alignbit_b32_e64_dpp v5, v1, v2, v255 op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05]
+
0x05,0x00,0x17,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
# W32-REAL16: v_alignbyte_b32_e64_dpp v5, v1, v2, v3.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
# W32-FAKE16: v_alignbyte_b32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x17,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
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