[llvm] AMDGPU: Drop legacy r600.read.global.size intrinsics from amdgcn (PR #128700)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 25 03:34:05 PST 2025
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/128700
These ancient intrinsics were still consumed by the backend for libclc,
which no longer uses them.
>From 1297ab34a5ee68f983979d69e12ca800243d6162 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 25 Feb 2025 18:25:51 +0700
Subject: [PATCH] AMDGPU: Drop legacy r600.read.global.size intrinsics from
amdgcn
These ancient intrinsics were still consumed by the backend for libclc,
which no longer uses them.
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 9 +---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 21 --------
.../amdgpu.work-item-intrinsics.deprecated.ll | 49 -------------------
3 files changed, 2 insertions(+), 77 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 649deee346e90..ef8aaf22aded0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -7400,13 +7400,8 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
return legalizeKernargMemParameter(MI, B, SI::KernelInputOffsets::LOCAL_SIZE_Y);
// TODO: Could insert G_ASSERT_ZEXT from s16
case Intrinsic::r600_read_local_size_z:
- return legalizeKernargMemParameter(MI, B, SI::KernelInputOffsets::LOCAL_SIZE_Z);
- case Intrinsic::r600_read_global_size_x:
- return legalizeKernargMemParameter(MI, B, SI::KernelInputOffsets::GLOBAL_SIZE_X);
- case Intrinsic::r600_read_global_size_y:
- return legalizeKernargMemParameter(MI, B, SI::KernelInputOffsets::GLOBAL_SIZE_Y);
- case Intrinsic::r600_read_global_size_z:
- return legalizeKernargMemParameter(MI, B, SI::KernelInputOffsets::GLOBAL_SIZE_Z);
+ return legalizeKernargMemParameter(MI, B,
+ SI::KernelInputOffsets::LOCAL_SIZE_Z);
case Intrinsic::amdgcn_fdiv_fast:
return legalizeFDIVFastIntrin(MI, MRI, B);
case Intrinsic::amdgcn_is_shared:
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 6ed09253c51e1..be7cdde802b51 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -8770,27 +8770,6 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
SI::KernelInputOffsets::NGROUPS_Z, Align(4),
false);
- case Intrinsic::r600_read_global_size_x:
- if (Subtarget->isAmdHsaOS())
- return emitNonHSAIntrinsicError(DAG, DL, VT);
-
- return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
- SI::KernelInputOffsets::GLOBAL_SIZE_X,
- Align(4), false);
- case Intrinsic::r600_read_global_size_y:
- if (Subtarget->isAmdHsaOS())
- return emitNonHSAIntrinsicError(DAG, DL, VT);
-
- return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
- SI::KernelInputOffsets::GLOBAL_SIZE_Y,
- Align(4), false);
- case Intrinsic::r600_read_global_size_z:
- if (Subtarget->isAmdHsaOS())
- return emitNonHSAIntrinsicError(DAG, DL, VT);
-
- return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
- SI::KernelInputOffsets::GLOBAL_SIZE_Z,
- Align(4), false);
case Intrinsic::r600_read_local_size_x:
if (Subtarget->isAmdHsaOS())
return emitNonHSAIntrinsicError(DAG, DL, VT);
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll b/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
index ad646a36a7443..e2510bb976be7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
@@ -53,51 +53,6 @@ entry:
ret void
}
-; FUNC-LABEL: {{^}}global_size_x:
-; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x3
-; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0xc
-; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; GCN-NOHSA: buffer_store_dword [[VVAL]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
-; EG: MOV {{\*? *}}[[VAL]], KC0[0].W
-define amdgpu_kernel void @global_size_x (ptr addrspace(1) %out) {
-entry:
- %0 = call i32 @llvm.r600.read.global.size.x() #0
- store i32 %0, ptr addrspace(1) %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}global_size_y:
-; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x4
-; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x10
-; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; GCN-NOHSA: buffer_store_dword [[VVAL]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
-; EG: MOV {{\*? *}}[[VAL]], KC0[1].X
-define amdgpu_kernel void @global_size_y (ptr addrspace(1) %out) {
-entry:
- %0 = call i32 @llvm.r600.read.global.size.y() #0
- store i32 %0, ptr addrspace(1) %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}global_size_z:
-; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x5
-; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x14
-; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; GCN-NOHSA: buffer_store_dword [[VVAL]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
-; EG: MOV {{\*? *}}[[VAL]], KC0[1].Y
-define amdgpu_kernel void @global_size_z (ptr addrspace(1) %out) {
-entry:
- %0 = call i32 @llvm.r600.read.global.size.z() #0
- store i32 %0, ptr addrspace(1) %out
- ret void
-}
-
; FUNC-LABEL: {{^}}local_size_x:
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x6
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x18
@@ -147,10 +102,6 @@ declare i32 @llvm.r600.read.ngroups.x() #0
declare i32 @llvm.r600.read.ngroups.y() #0
declare i32 @llvm.r600.read.ngroups.z() #0
-declare i32 @llvm.r600.read.global.size.x() #0
-declare i32 @llvm.r600.read.global.size.y() #0
-declare i32 @llvm.r600.read.global.size.z() #0
-
declare i32 @llvm.r600.read.local.size.x() #0
declare i32 @llvm.r600.read.local.size.y() #0
declare i32 @llvm.r600.read.local.size.z() #0
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