[llvm] [PowerPC] Do not rely on MachineSink threshold to optimize CR spilling (PR #128745)

[Guy David via llvm-commits]

https://github.com/guy-david updated https://github.com/llvm/llvm-project/pull/128745

>From cebcc2fe2049e1ef39b0c50ec974540d789b7985 Mon Sep 17 00:00:00 2001
From: Guy David <guyda96 at gmail.com>
Date: Tue, 25 Feb 2025 09:02:46 -0800
Subject: [PATCH] [PowerPC] Do not rely on MachineSink threshold to optimize CR
 spilling

spill_p0_setb.ll and knowCRBitSpill.ll rely on a probability threshold
in MachineSink to pull down CRSET/CRUNSET. It's worth to do so anyway
and let register allocation decide otherwise.
Additionally, make the interface accept a const MI.
---
 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp      |  7 ++++
 llvm/lib/Target/PowerPC/PPCInstrInfo.h        |  1 +
 .../CodeGen/PowerPC/sink-crset-crunset.mir    | 36 +++++++++++++++++++
 llvm/test/CodeGen/PowerPC/spill_p9_setb.ll    |  8 ++---
 4 files changed, 48 insertions(+), 4 deletions(-)
 create mode 100644 llvm/test/CodeGen/PowerPC/sink-crset-crunset.mir

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 9b526066fe75b..b1e170f9316e4 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1072,6 +1072,13 @@ Register PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   return 0;
 }
 
+/// Sink down CodeGen-only, cheap instructions to allow further
+/// optimizations which are only applied intra-block.
+bool PPCInstrInfo::shouldBreakCriticalEdgeToSink(MachineInstr &MI) const {
+  // These can turn into immediates, see PPCRegisterInfo::lowerCRBitRestore.
+  return MI.getOpcode() == PPC::CRSET || MI.getOpcode() == PPC::CRUNSET;
+}
+
 // For opcodes with the ReMaterializable flag set, this function is called to
 // verify the instruction is really rematable.
 bool PPCInstrInfo::isReallyTriviallyReMaterializable(
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index d4554379cdb1d..b53720d2322cb 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -424,6 +424,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
                              unsigned &SubIdx) const override;
   Register isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
+  bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override;
   bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
   Register isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
diff --git a/llvm/test/CodeGen/PowerPC/sink-crset-crunset.mir b/llvm/test/CodeGen/PowerPC/sink-crset-crunset.mir
new file mode 100644
index 0000000000000..d3ba8e0246eac
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/sink-crset-crunset.mir
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -run-pass=machine-sink -mtriple=powerpc64-unknown-linux-gnu -o - %s | FileCheck %s
+
+---
+name:            sink_crset_crunset
+body:             |
+  ; CHECK-LABEL: name: sink_crset_crunset
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $r3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %cond:crrc = CMPLWI killed renamable $r3, 0
+  ; CHECK-NEXT:   BCC 76, killed %cond, %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %a:crbitrc = CRSET
+  ; CHECK-NEXT:   %b:crbitrc = CRUNSET
+  ; CHECK-NEXT:   %and:crbitrc = CRAND killed %a, %b
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   BLR implicit $lr, implicit $rm
+  bb.0.entry:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: $r3
+    %cond:crrc = CMPLWI killed renamable $r3, 0
+    %a:crbitrc = CRSET
+    %b:crbitrc = CRUNSET
+    BCC 76, killed %cond, %bb.2
+  bb.1:
+    %and:crbitrc = CRAND killed %a, %b
+  bb.2:
+    BLR implicit $lr, implicit $rm
+
+...
diff --git a/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll b/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
index 81c43ce85d59a..a8afb0124c494 100644
--- a/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
+++ b/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
@@ -16,21 +16,21 @@
 
 define void @p9_setb_spill() {
 ; CHECK-P9-LABEL: p9_setb_spill:
-; CHECK-P9:       # %bb.1: # %if.then
+; CHECK-P9:       .LBB0_2: # %if.then
 ; CHECK-P9-DAG:    crnot 4*cr[[CREG:.*]]+lt, eq
 ; CHECK-P9-DAG:    setb [[REG1:.*]], cr[[CREG]]
 ; CHECK-P9-DAG:    stw [[REG1]]
 ; CHECK-P9:        blr
-; CHECK-P9:        .LBB0_4: # %if.then1
+; CHECK-P9:       .LBB0_5: # %if.then1
 ;
 ; CHECK-P8-LABEL: p9_setb_spill:
-; CHECK-P8:       # %bb.1: # %if.then
+; CHECK-P8:       .LBB0_2: # %if.then
 ; CHECK-P8-DAG:    crnot 4*cr[[CREG2:.*]]+lt, eq
 ; CHECK-P8-DAG:    mfocrf [[REG2:.*]],
 ; CHECK-P8-DAG:    rlwinm [[REG2]], [[REG2]]
 ; CHECK-P8-DAG:    stw [[REG2]]
 ; CHECK-P8:        blr
-; CHECK-P8:        .LBB0_4: # %if.then1
+; CHECK-P8:       .LBB0_5: # %if.then1
 entry:
   br i1 undef, label %if.end, label %if.then