[llvm] [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (PR #128978)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 26 17:13:07 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Min-Yih Hsu (mshockwave)
<details>
<summary>Changes</summary>
It seems like we had been picking the wrong VPseudo scheduling class for indexed memory operations in RISCVMCACustomBehavior: the VPseudo opcode of indexed memory ops encode two EMULs, one for index and the other for data. However, in RISCVInversePseudoTable, we're only able to look up against one of them, yielding an incorrect VPseudo opcode with the wrong data EEW (index EEW is encoded in the opcode). Since scheduling classes for indexed memory ops uses data EMUL / EEW in their scheduling class, we would eventually fetch the wrong scheduling classes with faulty data EEW.
This patch fixes this issue by deducting the correct index EMUL with LMUL (data EMUL), SEW (data EEW), and index EEW. With these parameters we can thus fetch the correct VPseudo opcode with `getVLXPseudo` / `getVLXSEGPseudo` and friends.
The new search table, RISCVBaseVXMemOpTable, is created to extract the NF and index EEW info from MC opcode. Otherwise we need to write a gigantic switch statement to decode this info.
---
Patch is 155.86 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/128978.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp (+65-7)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoV.td (+24)
- (modified) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s (+135-135)
- (modified) llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s (+135-135)
``````````diff
diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
index 0881de90700ab..5798af8608444 100644
--- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
+++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
@@ -14,12 +14,33 @@
#include "RISCVCustomBehaviour.h"
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "RISCV.h"
+#include "RISCVISelDAGToDAG.h"
#include "TargetInfo/RISCVTargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Debug.h"
#define DEBUG_TYPE "llvm-mca-riscv-custombehaviour"
+namespace llvm::RISCV::mca {
+struct VXMemOpInfo {
+ unsigned Log2IdxEEW : 3;
+ unsigned IsOrdered : 1;
+ unsigned IsStore : 1;
+ unsigned NF : 4;
+ unsigned BaseInstr;
+};
+
+#define GET_RISCVBaseVXMemOpTable_DECL
+#define GET_RISCVBaseVXMemOpTable_IMPL
+// We need to include the implementation code here because RISCVCustomBehavior
+// is not linked against RISCVCodeGen.
+#define GET_RISCVVLXSEGTable_IMPL
+#define GET_RISCVVSXSEGTable_IMPL
+#define GET_RISCVVLXTable_IMPL
+#define GET_RISCVVSXTable_IMPL
+#include "RISCVGenSearchableTables.inc"
+} // namespace llvm::RISCV::mca
+
namespace llvm {
namespace mca {
@@ -247,21 +268,58 @@ unsigned RISCVInstrumentManager::getSchedClassID(
// and SEW, or (Opcode, LMUL, 0) if does not depend on SEW.
uint8_t SEW = SI ? SI->getSEW() : 0;
- const RISCVVInversePseudosTable::PseudoInfo *RVV = nullptr;
- if (opcodeHasEEWAndEMULInfo(Opcode)) {
+ std::optional<unsigned> VPOpcode;
+ if (const auto *VXMO = RISCV::mca::getVXMemOpInfo(Opcode)) {
+ // Calculate the expected index EMUL. For indexed operations,
+ // the DataEEW and DataEMUL are equal to SEW and LMUL, respectively.
+ unsigned IndexEMUL = ((1 << VXMO->Log2IdxEEW) * LMUL) / SEW;
+
+ if (!VXMO->NF) {
+ // Indexed Load / Store.
+ if (VXMO->IsStore) {
+ if (const auto *VXP = RISCV::mca::getVSXPseudo(
+ /*Masked=*/0, VXMO->IsOrdered, VXMO->Log2IdxEEW, LMUL,
+ IndexEMUL))
+ VPOpcode = VXP->Pseudo;
+ } else {
+ if (const auto *VXP = RISCV::mca::getVLXPseudo(
+ /*Masked=*/0, VXMO->IsOrdered, VXMO->Log2IdxEEW, LMUL,
+ IndexEMUL))
+ VPOpcode = VXP->Pseudo;
+ }
+ } else {
+ // Segmented Indexed Load / Store.
+ if (VXMO->IsStore) {
+ if (const auto *VXP = RISCV::mca::getVSXSEGPseudo(
+ VXMO->NF, /*Masked=*/0, VXMO->IsOrdered, VXMO->Log2IdxEEW, LMUL,
+ IndexEMUL))
+ VPOpcode = VXP->Pseudo;
+ } else {
+ if (const auto *VXP = RISCV::mca::getVLXSEGPseudo(
+ VXMO->NF, /*Masked=*/0, VXMO->IsOrdered, VXMO->Log2IdxEEW, LMUL,
+ IndexEMUL))
+ VPOpcode = VXP->Pseudo;
+ }
+ }
+ } else if (opcodeHasEEWAndEMULInfo(Opcode)) {
RISCVVType::VLMUL VLMUL = static_cast<RISCVVType::VLMUL>(LMUL);
auto [EEW, EMUL] = getEEWAndEMUL(Opcode, VLMUL, SEW);
- RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW);
+ if (const auto *RVV =
+ RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW))
+ VPOpcode = RVV->Pseudo;
} else {
// Check if it depends on LMUL and SEW
- RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);
+ const auto *RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);
// Check if it depends only on LMUL
if (!RVV)
RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);
+
+ if (RVV)
+ VPOpcode = RVV->Pseudo;
}
// Not a RVV instr
- if (!RVV) {
+ if (!VPOpcode) {
LLVM_DEBUG(
dbgs() << "RVCB: Could not find PseudoInstruction for Opcode "
<< MCII.getName(Opcode)
@@ -277,8 +335,8 @@ unsigned RISCVInstrumentManager::getSchedClassID(
<< MCII.getName(Opcode) << ", LMUL=" << LI->getData()
<< ", SEW=" << (SI ? SI->getData() : "Unspecified")
<< ". Overriding original SchedClassID=" << SchedClassID
- << " with " << MCII.getName(RVV->Pseudo) << '\n');
- return MCII.get(RVV->Pseudo).getSchedClass();
+ << " with " << MCII.getName(*VPOpcode) << '\n');
+ return MCII.get(*VPOpcode).getSchedClass();
}
} // namespace mca
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index fdb2334b131da..35a93315db18a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -316,6 +316,22 @@ class VSXSEGSched<int nf, int eew, bit isOrdered, string emul,
class VSXSEGSchedMC<int nf, int eew, bit isOrdered>:
VSXSEGSched<nf, eew, isOrdered, "WorstCase", forceMasked=1>;
+class RISCVVXMemOpMC<bits<3> E, bit Ordered, bit Store, bits<4> N = 0> {
+ bits<3> Log2EEW = E;
+ bits<1> IsOrdered = Ordered;
+ bits<1> IsStore = Store;
+ bits<4> NF = N;
+ Instruction BaseInstr = !cast<Instruction>(NAME);
+}
+
+def RISCVBaseVXMemOpTable : GenericTable {
+ let FilterClass = "RISCVVXMemOpMC";
+ let CppTypeName = "VXMemOpInfo";
+ let Fields = ["Log2EEW", "IsOrdered", "IsStore", "NF", "BaseInstr"];
+ let PrimaryKey = ["BaseInstr"];
+ let PrimaryKeyName = "getVXMemOpInfo";
+}
+
//===----------------------------------------------------------------------===//
// Instruction class templates
//===----------------------------------------------------------------------===//
@@ -560,16 +576,20 @@ multiclass VIndexLoadStore<int eew> {
def VLUXEI # eew # _V :
VIndexedLoad<MOPLDIndexedUnord, w, "vluxei" # eew # ".v">,
+ RISCVVXMemOpMC<!logtwo(eew), Ordered=false, Store=false>,
VLXSchedMC<eew, isOrdered=0>;
def VLOXEI # eew # _V :
VIndexedLoad<MOPLDIndexedOrder, w, "vloxei" # eew # ".v">,
+ RISCVVXMemOpMC<!logtwo(eew), Ordered=true, Store=false>,
VLXSchedMC<eew, isOrdered=1>;
def VSUXEI # eew # _V :
VIndexedStore<MOPSTIndexedUnord, w, "vsuxei" # eew # ".v">,
+ RISCVVXMemOpMC<!logtwo(eew), Ordered=false, Store=true>,
VSXSchedMC<eew, isOrdered=0>;
def VSOXEI # eew # _V :
VIndexedStore<MOPSTIndexedOrder, w, "vsoxei" # eew # ".v">,
+ RISCVVXMemOpMC<!logtwo(eew), Ordered=true, Store=true>,
VSXSchedMC<eew, isOrdered=1>;
}
@@ -1760,18 +1780,22 @@ let Predicates = [HasVInstructions] in {
def VLUXSEG#nf#EI#eew#_V :
VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, w,
"vluxseg"#nf#"ei"#eew#".v">,
+ RISCVVXMemOpMC<!logtwo(eew), Ordered=false, Store=false, N=nf>,
VLXSEGSchedMC<nf, eew, isOrdered=0>;
def VLOXSEG#nf#EI#eew#_V :
VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, w,
"vloxseg"#nf#"ei"#eew#".v">,
+ RISCVVXMemOpMC<!logtwo(eew), Ordered=true, Store=false, N=nf>,
VLXSEGSchedMC<nf, eew, isOrdered=1>;
def VSUXSEG#nf#EI#eew#_V :
VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, w,
"vsuxseg"#nf#"ei"#eew#".v">,
+ RISCVVXMemOpMC<!logtwo(eew), Ordered=false, Store=true, N=nf>,
VSXSEGSchedMC<nf, eew, isOrdered=0>;
def VSOXSEG#nf#EI#eew#_V :
VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, w,
"vsoxseg"#nf#"ei"#eew#".v">,
+ RISCVVXMemOpMC<!logtwo(eew), Ordered=true, Store=true, N=nf>,
VSXSEGSchedMC<nf, eew, isOrdered=1>;
}
}
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
index a3f14f316e874..41e9101486ead 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
@@ -1606,13 +1606,13 @@ vsoxseg8ei64.v v8, (a0), v16
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 1540
-# CHECK-NEXT: Total Cycles: 28335
+# CHECK-NEXT: Total Cycles: 28599
# CHECK-NEXT: Total uOps: 1540
# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.05
# CHECK-NEXT: IPC: 0.05
-# CHECK-NEXT: Block RThroughput: 17896.0
+# CHECK-NEXT: Block RThroughput: 18160.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -2492,27 +2492,27 @@ vsoxseg8ei64.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 44 44.00 * vluxseg2ei8.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 76 76.00 * vluxseg2ei8.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 140 140.00 * vluxseg2ei8.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 16 16.00 * vluxseg2ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 20 20.00 * vluxseg2ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 28 28.00 * vluxseg2ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 44 44.00 * vluxseg2ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 76 76.00 * vluxseg2ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 16 16.00 * vluxseg2ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 20 20.00 * vluxseg2ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
# CHECK-NEXT: 1 28 28.00 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg2ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 16 16.00 * vluxseg2ei64.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
@@ -2528,21 +2528,21 @@ vsoxseg8ei64.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 60 60.00 * vluxseg3ei8.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 108 108.00 * vluxseg3ei8.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 18 18.00 * vluxseg3ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 24 24.00 * vluxseg3ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 36 36.00 * vluxseg3ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 60 60.00 * vluxseg3ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 18 18.00 * vluxseg3ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 24 24.00 * vluxseg3ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 36 36.00 * vluxseg3ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 18 18.00 * vluxseg3ei64.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
@@ -2556,21 +2556,21 @@ vsoxseg8ei64.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 76 76.00 * vluxseg4ei8.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 140 140.00 * vluxseg4ei8.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 20 20.00 * vluxseg4ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 28 28.00 * vluxseg4ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 44 44.00 * vluxseg4ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 76 76.00 * vluxseg4ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 20 20.00 * vluxseg4ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 28 28.00 * vluxseg4ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 44 44.00 * vluxseg4ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 20 20.00 * vluxseg4ei64.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
@@ -2584,13 +2584,13 @@ vsoxseg8ei64.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 92 92.00 * vluxseg5ei8.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 22 22.00 * vluxseg5ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 32 32.00 * vluxseg5ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 52 52.00 * vluxseg5ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 22 22.00 * vluxseg5ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 32 32.00 * vluxseg5ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
@@ -2604,13 +2604,13 @@ vsoxseg8ei64.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 108 108.00 * vluxseg6ei8.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 24 24.00 * vluxseg6ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 36 36.00 * vluxseg6ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 60 60.00 * vluxseg6ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 24 24.00 * vluxseg6ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 36 36.00 * vluxseg6ei32.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
@@ -2624,13 +2624,13 @@ vsoxseg8ei64.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 124 124.00 * vluxseg7ei8.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 26 26.00 * vluxseg7ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 40 40.00 * vluxseg7ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 68 68.00 * vluxseg7ei16.v v8, (a0), v16
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 40 40.00 * ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/128978
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