[llvm] [CodeGen][NVPTX] Add a TRI function get the Dwarf register number for a virtual register. (PR #129017)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/129017

NVPTX needs to be able to get the Dwarf register number for a virtual register. The interface we have for this today is on MCRegisterInfo and take a MCRegister argument. It shouldn't be legal to convert a Register containing a virtual register to an MCRegister.

This patch adds a getDwarfRegNumForVirtReg function that takes a Register to TRI and splits the NVPTX override of getDwarfRegNum.

>From c9aaa9386ea410cbec091cba56862b64589c7a4e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 26 Feb 2025 22:51:30 -0800
Subject: [PATCH] [CodeGen][NVPTX] Add a TRI function get the Dwarf register
 number for a virtual register.

NVPTX needs to be able to get the Dwarf register number for a virtual
register. The interface we have for this today is on MCRegisterInfo
and take a MCRegister argument. It shouldn't be legal to convert a
Register containing a virtual register to an MCRegister.

This patch adds a getDwarfRegNumForVirtReg function to TRI and splits
the NVPTX override of getDwarfRegNum.
---
 .../include/llvm/CodeGen/TargetRegisterInfo.h |  4 ++++
 .../CodeGen/AsmPrinter/DwarfExpression.cpp    |  2 +-
 llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp   | 21 +++++++++++--------
 llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h     |  1 +
 4 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 79f014edb58c8..3206cc4518821 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1111,6 +1111,10 @@ class TargetRegisterInfo : public MCRegisterInfo {
   prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
                           const StackOffset &Offset) const;
 
+  virtual int64_t getDwarfRegNumForVirtReg(Register RegNum, bool isEH) const {
+    llvm_unreachable("getDwarfRegNumForVirtReg does not exist on this target");
+  }
+
   /// Spill the register so it can be used by the register scavenger.
   /// Return true if the register was spilled, false otherwise.
   /// If this function does not spill the register, the scavenger
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
index f5d2863ae70b7..e684054ffa3e4 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
@@ -106,7 +106,7 @@ bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
       return true;
     }
     // Try getting dwarf register for virtual register anyway, eg. for NVPTX.
-    int64_t Reg = TRI.getDwarfRegNum(MachineReg, false);
+    int64_t Reg = TRI.getDwarfRegNumForVirtReg(MachineReg, false);
     if (Reg > 0) {
       DwarfRegs.push_back(Register::createRegister(Reg, nullptr));
       return true;
diff --git a/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
index 229c438edf723..142388893082a 100644
--- a/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
@@ -170,15 +170,18 @@ void NVPTXRegisterInfo::addToDebugRegisterMap(
 }
 
 int64_t NVPTXRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
-  if (RegNum.isPhysical()) {
-    StringRef Name = NVPTXInstPrinter::getRegisterName(RegNum.id());
-    // In NVPTXFrameLowering.cpp, we do arrange for %Depot to be accessible from
-    // %SP. Using the %Depot register doesn't provide any debug info in
-    // cuda-gdb, but switching it to %SP does.
-    if (RegNum.id() == NVPTX::VRDepot)
-      Name = "%SP";
-    return encodeRegisterForDwarf(Name);
-  }
+  StringRef Name = NVPTXInstPrinter::getRegisterName(RegNum.id());
+  // In NVPTXFrameLowering.cpp, we do arrange for %Depot to be accessible from
+  // %SP. Using the %Depot register doesn't provide any debug info in
+  // cuda-gdb, but switching it to %SP does.
+  if (RegNum.id() == NVPTX::VRDepot)
+    Name = "%SP";
+  return encodeRegisterForDwarf(Name);
+}
+
+int64_t NVPTXRegisterInfo::getDwarfRegNumForVirtReg(Register RegNum,
+                                                    bool isEH) const {
+  assert(RegNum.isVirtual());
   uint64_t lookup = debugRegisterMap.lookup(RegNum.id());
   if (lookup)
     return lookup;
diff --git a/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h b/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
index cfec7377fd634..1334bfa035a96 100644
--- a/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
@@ -72,6 +72,7 @@ class NVPTXRegisterInfo : public NVPTXGenRegisterInfo {
                              StringRef RegisterName) const;
   void clearDebugRegisterMap() const;
   int64_t getDwarfRegNum(MCRegister RegNum, bool isEH) const override;
+  int64_t getDwarfRegNumForVirtReg(Register RegNum, bool isEH) const override;
 };
 
 StringRef getNVPTXRegClassName(const TargetRegisterClass *RC);