[llvm] [AMDGPU] Add custom MachineValueType entries for buffer fat poiners (PR #127692)

[Krzysztof Drewniak via llvm-commits]

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@@ -331,6 +331,10 @@ def i64x8     : ValueType<512,  231>;  // 8 Consecutive GPRs (AArch64)
 def aarch64svcount
               : ValueType<16,  232>;  // AArch64 predicate-as-counter
 def spirvbuiltin : ValueType<0, 233>; // SPIR-V's builtin type
+// AMDGPU buffer fat pointer, buffer rsrc + offset, rewritten before MIR translation
+def amdgpuBufferFatPointer : ValueType<160, 234>;
+// AMDGPU buffer strided pointer, buffer rsrc + index + offset, doesn't reach MIR
+def amdgpuBufferStridedPointer : ValueType<192, 235>;
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krzysz00 wrote:

And since these are special-purpose MVT entries that shouldn't hit codegen (and that would need special handling if they did - if we were to do address space 7 at the MIR level, we'd wouldn't want the usual `sexts` that come with GEP) I figure this is something that makes more sense as a standalone MVT instead of trying to make i160 happen.

https://github.com/llvm/llvm-project/pull/127692