[llvm] 0a0775e - [gn] port 32dffdce0511 (more RISCV depedency things)

[Nico Weber via llvm-commits]

Author: Nico Weber
Date: 2025-02-28T21:16:40-05:00
New Revision: 0a0775e795850503e1d7da3543e663f584c1810c

URL: https://github.com/llvm/llvm-project/commit/0a0775e795850503e1d7da3543e663f584c1810c
DIFF: https://github.com/llvm/llvm-project/commit/0a0775e795850503e1d7da3543e663f584c1810c.diff

LOG: [gn] port 32dffdce0511 (more RISCV depedency things)

Looks like RISCV is picking up AMDGPU's bad habits wrt generated files.

Added: 
    

Modified: 
    llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
    llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn

Removed: 
    


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diff  --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
index 1d76bc9e8974c..559101e830961 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
@@ -72,6 +72,7 @@ tablegen("RISCVGenPostLegalizeGICombiner") {
 tablegen("RISCVGenRegisterBank") {
   visibility = [
     ":LLVMRISCVCodeGen",
+    "MCA",
     "//llvm/tools/llvm-exegesis/lib/RISCV",
   ]
   args = [ "-gen-register-bank" ]

diff  --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn
index a4d95f5381afc..3c0b866238be0 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn
@@ -8,6 +8,10 @@ static_library("MCA") {
     "//llvm/lib/Support",
     "//llvm/lib/Target/RISCV/MCTargetDesc",
     "//llvm/lib/Target/RISCV/TargetInfo",
+
+    # RISCVCustomBehaviour.cpp after 32dffdce0511 includes
+    # RISCVGenRegisterBank.inc via RISCVSubtarget.h :/
+    "../:RISCVGenRegisterBank",
   ]
   include_dirs = [ ".." ]
   sources = [ "RISCVCustomBehaviour.cpp" ]