[llvm] [X86] Enhance FABS/FNEG lowering for scalar _Float16 with bitwise operations (PR #128637)

[Simon Pilgrim via llvm-commits]

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@@ -22313,7 +22344,7 @@ static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
   // generate a 16-byte vector constant and logic op even for the scalar case.
   // Using a 16-byte mask allows folding the load of the mask with
   // the logic op, so it can save (~4 bytes) on code size.
-  bool IsFakeVector = !VT.isVector() && !IsF128;
+  bool IsFakeVector = !VT.isVector() && !IsF128 && VT != MVT::f16;
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RKSimon wrote:

Looks like the IsFakeVector/LogicVT code already handles MVT::f16 cases - so my guess is the ISD::FABS/FNEG/FCOPYSIGN actions aren't set to Custom for SSE2+ targets?

https://github.com/llvm/llvm-project/pull/128637