[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)

[Sudharsan Veeravalli via llvm-commits]

================
@@ -485,6 +498,43 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasVendorXqcilia, IsRV32]
 
+let Predicates = [HasVendorXqcisim, IsRV32] in {
+let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
+  def QC_PSYSCALLI : RVInstI<0b010, OPC_OP_IMM, (outs),
+                                  (ins uimm10:$imm10), "qc.psyscalli",
+                                  "$imm10"> {
+    bits<10> imm10;
+
+    let rs1 = 0;
+    let rd = 0;
+    let imm12 = {0b00, imm10};
+  }
+
+  def QC_PPUTCI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm8:$imm8),
+                               "qc.pputci", "$imm8"> {
----------------
svs-quic wrote:

Done

https://github.com/llvm/llvm-project/pull/128833